src/northbridge/intel/i3100/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman
   5  * Copyright (C) 2008 Arastra, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  *
  20  */
  21
  22 #include <cpu/x86/mtrr.h>
  23 #include <cpu/x86/cache.h>
  24 #include <stdlib.h>
  25 #include "raminit.h"
  26 #include "i3100.h"
  27
  28 /* DDR2 memory controller register space */
  29 #define MCBAR 0x90000000
  30
  31 static void sdram_set_registers(const struct mem_controller *ctrl)
  32 {
  33         static const u32 register_values[] = {
  34
  35                 /* CKDIS 0x8c disable clocks */
  36         PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
  37
  38                 /* 0x9c Device present and extended RAM control
  39                  * DEVPRES is very touchy, hard code the initialization
  40                  * of PCI-E ports here.
  41                  */
  42         PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
  43
  44                 /* 0xc8 Remap RAM base and limit off */
  45         PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
  46
  47                 /* ??? */
  48         PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
  49         PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
  50
  51                 /* 0x50 scrub */
  52         PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
  53
  54                 /* 0x58 0x5c PAM */
  55         PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
  56         PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
  57
  58                 /* 0xf4 */
  59         PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
  60
  61                 /* 0x14 */
  62         PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, MCBAR |0,
  63         };
  64         int i;
  65         int max;
  66
  67         max = ARRAY_SIZE(register_values);
  68         for(i = 0; i < max; i += 3) {
  69                 device_t dev;
  70                 u32 where;
  71                 u32 reg;
  72                 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
  73                 where = register_values[i] & 0xff;
  74                 reg = pci_read_config32(dev, where);
  75                 reg &= register_values[i+1];
  76                 reg |= register_values[i+2];
  77                 pci_write_config32(dev, where, reg);
  78         }
  79         print_spew("done.\r\n");
  80 }
  81
  82 struct dimm_size {
  83         u32 side1;
  84         u32 side2;
  85 };
  86
  87 static struct dimm_size spd_get_dimm_size(u16 device)
  88 {
  89         /* Calculate the log base 2 size of a DIMM in bits */
  90         struct dimm_size sz;
  91         int value, low, ddr2;
  92         sz.side1 = 0;
  93         sz.side2 = 0;
  94
  95         /* Note it might be easier to use byte 31 here, it has the DIMM size as
  96          * a multiple of 4MB.  The way we do it now we can size both
  97          * sides of an assymetric dimm.
  98          */
  99         value = spd_read_byte(device, 3);       /* rows */
 100         if (value < 0) goto hw_err;
 101         if ((value & 0xf) == 0) goto val_err;
 102         sz.side1 += value & 0xf;
 103
 104         value = spd_read_byte(device, 4);       /* columns */
 105         if (value < 0) goto hw_err;
 106         if ((value & 0xf) == 0) goto val_err;
 107         sz.side1 += value & 0xf;
 108
 109         value = spd_read_byte(device, 17);      /* banks */
 110         if (value < 0) goto hw_err;
 111         if ((value & 0xff) == 0) goto val_err;
 112         sz.side1 += log2(value & 0xff);
 113
 114         /* Get the module data width and convert it to a power of two */
 115         value = spd_read_byte(device, 7);       /* (high byte) */
 116         if (value < 0) goto hw_err;
 117         value &= 0xff;
 118         value <<= 8;
 119
 120         low = spd_read_byte(device, 6); /* (low byte) */
 121         if (low < 0) goto hw_err;
 122         value = value | (low & 0xff);
 123         if ((value != 72) && (value != 64)) goto val_err;
 124         sz.side1 += log2(value);
 125
 126         /* side 2 */
 127         value = spd_read_byte(device, 5);       /* number of physical banks */
 128
 129         if (value < 0) goto hw_err;
 130         value &= 7;
 131         value++;
 132         if (value == 1) goto out;
 133         if (value != 2) goto val_err;
 134
 135         /* Start with the symmetrical case */
 136         sz.side2 = sz.side1;
 137
 138         value = spd_read_byte(device, 3);       /* rows */
 139         if (value < 0) goto hw_err;
 140         if ((value & 0xf0) == 0) goto out;      /* If symmetrical we are done */
 141         sz.side2 -= (value & 0x0f);             /* Subtract out rows on side 1 */
 142         sz.side2 += ((value >> 4) & 0x0f);      /* Add in rows on side 2 */
 143
 144         value = spd_read_byte(device, 4);       /* columns */
 145         if (value < 0) goto hw_err;
 146         if ((value & 0xff) == 0) goto val_err;
 147         sz.side2 -= (value & 0x0f);             /* Subtract out columns on side 1 */
 148         sz.side2 += ((value >> 4) & 0x0f);      /* Add in columns on side 2 */
 149         goto out;
 150
 151  val_err:
 152         die("Bad SPD value\r\n");
 153         /* If an hw_error occurs report that I have no memory */
 154  hw_err:
 155         sz.side1 = 0;
 156         sz.side2 = 0;
 157  out:
 158         return sz;
 159
 160 }
 161
 162 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 163 {
 164         int i;
 165         int cum;
 166
 167         for(i = cum = 0; i < DIMM_SOCKETS; i++) {
 168                 struct dimm_size sz;
 169                 if (dimm_mask & (1 << i)) {
 170                         sz = spd_get_dimm_size(ctrl->channel0[i]);
 171                         if (sz.side1 < 29) {
 172                                 return -1; /* Report SPD error */
 173                         }
 174                         /* convert bits to multiples of 64MB */
 175                         sz.side1 -= 29;
 176                         cum += (1 << sz.side1);
 177                         /* DRB = 0x60 */
 178                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 179                         if( sz.side2 > 28) {
 180                                 sz.side2 -= 29;
 181                                 cum += (1 << sz.side2);
 182                         }
 183                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 184                 }
 185                 else {
 186                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 187                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 188                 }
 189         }
 190         cum >>= 1;
 191         /* set TOM top of memory 0xcc */
 192         pci_write_config16(ctrl->f0, TOM, cum);
 193         /* set TOLM top of low memory */
 194         if(cum > 0x18) {
 195                 cum = 0x18;
 196         }
 197         cum <<= 11;
 198         /* 0xc4 TOLM */
 199         pci_write_config16(ctrl->f0, TOLM, cum);
 200         return 0;
 201 }
 202
 203
 204 static u32 spd_detect_dimms(const struct mem_controller *ctrl)
 205 {
 206         u32 dimm_mask;
 207         int i;
 208         dimm_mask = 0;
 209         for(i = 0; i < DIMM_SOCKETS; i++) {
 210                 int byte;
 211                 u16 device;
 212                 device = ctrl->channel0[i];
 213                 if (device) {
 214                         byte = spd_read_byte(device, 2);  /* Type */
 215                         if (byte == 8) {
 216                                 dimm_mask |= (1 << i);
 217                         }
 218                 }
 219                 device = ctrl->channel1[i];
 220                 if (device) {
 221                         byte = spd_read_byte(device, 2);
 222                         if (byte == 8) {
 223                                 dimm_mask |= (1 << (i + DIMM_SOCKETS));
 224                         }
 225                 }
 226         }
 227         return dimm_mask;
 228 }
 229
 230
 231 static int spd_set_row_attributes(const struct mem_controller *ctrl,
 232                 long dimm_mask)
 233 {
 234         int value;
 235         int reg;
 236         int dra;
 237         int cnt;
 238
 239         dra = 0;
 240         for(cnt=0; cnt < 4; cnt++) {
 241                 if (!(dimm_mask & (1 << cnt))) {
 242                         continue;
 243                 }
 244                 reg =0;
 245                 value = spd_read_byte(ctrl->channel0[cnt], 3);  /* rows */
 246                 if (value < 0) goto hw_err;
 247                 if ((value & 0xf) == 0) goto val_err;
 248                 reg += value & 0xf;
 249
 250                 value = spd_read_byte(ctrl->channel0[cnt], 4);  /* columns */
 251                 if (value < 0) goto hw_err;
 252                 if ((value & 0xf) == 0) goto val_err;
 253                 reg += value & 0xf;
 254
 255                 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
 256                 if (value < 0) goto hw_err;
 257                 if ((value & 0xff) == 0) goto val_err;
 258                 reg += log2(value & 0xff);
 259
 260                 /* Get the device width and convert it to a power of two */
 261                 value = spd_read_byte(ctrl->channel0[cnt], 13);
 262                 if (value < 0) goto hw_err;
 263                 value = log2(value & 0xff);
 264                 reg += value;
 265                 if(reg < 27) goto hw_err;
 266                 reg -= 27;
 267                 reg += (value << 2);
 268
 269                 dra += reg << (cnt*8);
 270                 value = spd_read_byte(ctrl->channel0[cnt], 5);
 271                 if (value & 2)
 272                         dra += reg << ((cnt*8)+4);
 273         }
 274
 275         /* 0x70 DRA */
 276         pci_write_config32(ctrl->f0, DRA, dra);
 277         goto out;
 278
 279  val_err:
 280         die("Bad SPD value\r\n");
 281         /* If an hw_error occurs report that I have no memory */
 282  hw_err:
 283         dra = 0;
 284  out:
 285         return dra;
 286
 287 }
 288
 289
 290 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 291                 long dimm_mask, u32 drc)
 292 {
 293         int value;
 294         int reg;
 295         u32 drt;
 296         int cnt;
 297         int first_dimm;
 298         int cas_latency=0;
 299         int latency;
 300         u32 index = 0;
 301         u32 index2 = 0;
 302         static const u8 cycle_time[3] = { 0x75, 0x60, 0x50 };
 303         static const u8 latency_indicies[] = { 26, 23, 9 };
 304
 305         /* 0x78 DRT */
 306         drt = pci_read_config32(ctrl->f0, DRT);
 307         drt &= 3;  /* save bits 1:0 */
 308
 309         for(first_dimm = 0; first_dimm < 4; first_dimm++) {
 310                 if (dimm_mask & (1 << first_dimm))
 311                         break;
 312         }
 313
 314         drt |= (1<<6); /* back to back write turn around */
 315
 316         drt |= (3<<18);  /* Trasmax */
 317
 318         for(cnt=0; cnt < 4; cnt++) {
 319                 if (!(dimm_mask & (1 << cnt))) {
 320                         continue;
 321                 }
 322                 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
 323                 /* Compute the lowest cas latency supported */
 324                 latency = log2(reg) -2;
 325
 326                 /* Loop through and find a fast clock with a low latency */
 327                 for(index = 0; index < 3; index++, latency++) {
 328                         if ((latency < 2) || (latency > 4) ||
 329                                 (!(reg & (1 << latency)))) {
 330                                 continue;
 331                         }
 332                         value = spd_read_byte(ctrl->channel0[cnt],
 333                                         latency_indicies[index]);
 334
 335                         if(value <= cycle_time[drc&3]) {
 336                                 if( latency > cas_latency) {
 337                                         cas_latency = latency;
 338                                 }
 339                                 break;
 340                         }
 341                 }
 342         }
 343         index = (cas_latency-2);
 344         if((index)==0) cas_latency = 20;
 345         else if((index)==1) cas_latency = 25;
 346         else cas_latency = 30;
 347
 348         for(cnt=0;cnt<4;cnt++) {
 349                 if (!(dimm_mask & (1 << cnt))) {
 350                         continue;
 351                 }
 352                 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
 353                 if(((index>>8)&0x0ff)<reg) {
 354                         index &= ~(0x0ff << 8);
 355                         index |= (reg << 8);
 356                 }
 357                 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
 358                 if(((index>>16)&0x0ff)<reg) {
 359                         index &= ~(0x0ff << 16);
 360                         index |= (reg<<16);
 361                 }
 362                 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
 363                 if(((index2>>0)&0x0ff)<reg) {
 364                         index2 &= ~(0x0ff << 0);
 365                         index2 |= (reg<<0);
 366                 }
 367                 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
 368                 if(((index2>>8)&0x0ff)<reg) {
 369                         index2 &= ~(0x0ff << 8);
 370                         index2 |= (reg<<8);
 371                 }
 372                 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
 373                 if(((index2>>16)&0x0ff)<reg) {
 374                         index2 &= ~(0x0ff << 16);
 375                         index2 |= (reg<<16);
 376                 }
 377         }
 378
 379         /* get dimm speed */
 380         value = cycle_time[drc&3];
 381         if(value <= 0x50) {  /* 200 MHz */
 382                 if((index&7) > 2) {
 383                         drt |= (2<<2);  /* CAS latency 4 */
 384                         cas_latency = 40;
 385                 } else {
 386                         drt |= (1<<2);  /* CAS latency 3 */
 387                         cas_latency = 30;
 388                 }
 389                 if((index&0x0ff00)<=0x03c00) {
 390                         drt |= (1<<8);  /* Trp RAS Precharg */
 391                 } else {
 392                         drt |= (2<<8);  /* Trp RAS Precharg */
 393                 }
 394
 395                 /* Trcd RAS to CAS delay */
 396                 if((index2&0x0ff)<=0x03c) {
 397                         drt |= (0<<10);
 398                 } else {
 399                         drt |= (1<<10);
 400                 }
 401
 402                 /* Tdal Write auto precharge recovery delay */
 403                 drt |= (1<<12);
 404
 405                 /* Trc TRS min */
 406                 if((index2&0x0ff00)<=0x03700)
 407                         drt |= (0<<14);
 408                 else if((index2&0xff00)<=0x03c00)
 409                         drt |= (1<<14);
 410                 else
 411                         drt |= (2<<14); /* spd 41 */
 412
 413                 drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
 414
 415                 /* Trrd Row Delay */
 416                 if((index&0x0ff0000)<=0x0140000) {
 417                         drt |= (0<<20);
 418                 } else if((index&0x0ff0000)<=0x0280000) {
 419                         drt |= (1<<20);
 420                 } else if((index&0x0ff0000)<=0x03c0000) {
 421                         drt |= (2<<20);
 422                 } else {
 423                         drt |= (3<<20);
 424                 }
 425
 426                 /* Trfc Auto refresh cycle time */
 427                 if((index2&0x0ff0000)<=0x04b0000) {
 428                         drt |= (0<<22);
 429                 } else if((index2&0x0ff0000)<=0x0690000) {
 430                         drt |= (1<<22);
 431                 } else {
 432                         drt |= (2<<22);
 433                 }
 434                 /* Docs say use 55 for all 200Mhz */
 435                 drt |= (0x055<<24);
 436         }
 437         else if(value <= 0x60) { /* 167 Mhz */
 438                 /* according to new documentation CAS latency is 00
 439                  * for bits 3:2 for all 167 Mhz
 440                 drt |= ((index&3)<<2); */  /* set CAS latency */
 441                 if((index&0x0ff00)<=0x03000) {
 442                         drt |= (1<<8);  /* Trp RAS Precharg */
 443                 } else {
 444                         drt |= (2<<8);  /* Trp RAS Precharg */
 445                 }
 446
 447                 /* Trcd RAS to CAS delay */
 448                 if((index2&0x0ff)<=0x030) {
 449                         drt |= (0<<10);
 450                 } else {
 451                         drt |= (1<<10);
 452                 }
 453
 454                 /* Tdal Write auto precharge recovery delay */
 455                 drt |= (2<<12);
 456
 457                 /* Trc TRS min */
 458                 drt |= (2<<14); /* spd 41, but only one choice */
 459
 460                 drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
 461
 462                 /* Trrd Row Delay */
 463                 if((index&0x0ff0000)<=0x0180000) {
 464                         drt |= (0<<20);
 465                 } else if((index&0x0ff0000)<=0x0300000) {
 466                         drt |= (1<<20);
 467                 } else {
 468                         drt |= (2<<20);
 469                 }
 470
 471                 /* Trfc Auto refresh cycle time */
 472                 if((index2&0x0ff0000)<=0x0480000) {
 473                         drt |= (0<<22);
 474                 } else if((index2&0x0ff0000)<=0x0780000) {
 475                         drt |= (2<<22);
 476                 } else {
 477                         drt |= (2<<22);
 478                 }
 479                 /* Docs state to use 99 for all 167 Mhz */
 480                 drt |= (0x099<<24);
 481         }
 482         else if(value <= 0x75) { /* 133 Mhz */
 483                 drt |= ((index&3)<<2);  /* set CAS latency */
 484                 if((index&0x0ff00)<=0x03c00) {
 485                         drt |= (1<<8);  /* Trp RAS Precharg */
 486                 } else {
 487                         drt |= (2<<8);  /* Trp RAS Precharg */
 488                 }
 489
 490                 /* Trcd RAS to CAS delay */
 491                 if((index2&0x0ff)<=0x03c) {
 492                         drt |= (0<<10);
 493                 } else {
 494                         drt |= (1<<10);
 495                 }
 496
 497                 /* Tdal Write auto precharge recovery delay */
 498                 drt |= (1<<12);
 499
 500                 /* Trc TRS min */
 501                 drt |= (2<<14); /* spd 41, but only one choice */
 502
 503                 drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
 504
 505                 /* Trrd Row Delay */
 506                 if((index&0x0ff0000)<=0x01e0000) {
 507                         drt |= (0<<20);
 508                 } else if((index&0x0ff0000)<=0x03c0000) {
 509                         drt |= (1<<20);
 510                 } else {
 511                         drt |= (2<<20);
 512                 }
 513
 514                 /* Trfc Auto refresh cycle time */
 515                 if((index2&0x0ff0000)<=0x04b0000) {
 516                         drt |= (0<<22);
 517                 } else if((index2&0x0ff0000)<=0x0780000) {
 518                         drt |= (2<<22);
 519                 } else {
 520                         drt |= (2<<22);
 521                 }
 522
 523                 /* Based on CAS latency */
 524                 if(index&7)
 525                         drt |= (0x099<<24);
 526                 else
 527                         drt |= (0x055<<24);
 528
 529         }
 530         else {
 531                 die("Invalid SPD 9 bus speed.\r\n");
 532         }
 533
 534         /* 0x78 DRT */
 535         pci_write_config32(ctrl->f0, DRT, drt);
 536
 537         return(cas_latency);
 538 }
 539
 540 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 541                 long dimm_mask)
 542 {
 543         int value;
 544         int drc;
 545         int cnt;
 546         msr_t msr;
 547         u8 rate = 62;
 548         static const u8 spd_rates[6] = {15,3,7,7,62,62};
 549         static const u8 drc_rates[5] = {0,15,7,62,3};
 550         static const u8 fsb_conversion[8] = {0,1,3,2,3,0,3,3};
 551
 552         /* 0x7c DRC */
 553         drc = pci_read_config32(ctrl->f0, DRC);
 554         for(cnt=0; cnt < 4; cnt++) {
 555                 if (!(dimm_mask & (1 << cnt))) {
 556                         continue;
 557                 }
 558                 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
 559                 if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
 560
 561                 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
 562                 value &= 0x0f;    /* clip self refresh bit */
 563                 if (value > 5) goto hw_err;
 564                 if (rate > spd_rates[value])
 565                         rate = spd_rates[value];
 566
 567                 value = spd_read_byte(ctrl->channel0[cnt], 9);  /* cycle time */
 568                 if (value > 0x75) goto hw_err;
 569         }
 570         drc |= (1 << 20); /* enable ECC */
 571         for (cnt = 1; cnt < 5; cnt++)
 572                 if (drc_rates[cnt] == rate)
 573                         break;
 574         if (cnt < 5) {
 575                 drc &= ~(7 << 8);  /* clear the rate bits */
 576                 drc |= (cnt << 8);
 577         }
 578
 579         drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
 580         drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
 581         drc |= (1 << 7);
 582         drc &= ~(1 << 5); /* enable ODT */
 583         drc |= (1 << 4); /* independent clocks */
 584
 585         /* set front side bus speed */
 586         msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
 587         value = msr.lo & 0x07;
 588         drc &= ~(3 << 2);
 589         drc |= (fsb_conversion[value] << 2);
 590
 591         /* set dram type to ddr2 */
 592         drc &= ~(3 << 0);
 593         drc |= (2 << 0);
 594
 595         goto out;
 596
 597  val_err:
 598         die("Bad SPD value\r\n");
 599         /* If an hw_error occurs report that I have no memory */
 600  hw_err:
 601         drc = 0;
 602  out:
 603         return drc;
 604 }
 605
 606 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 607 {
 608         long dimm_mask;
 609
 610         /* Test if we can read the spd and if ram is ddr or ddr2 */
 611         dimm_mask = spd_detect_dimms(ctrl);
 612         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 613                 print_err("No memory for this cpu\r\n");
 614                 return;
 615         }
 616         return;
 617 }
 618
 619 static void do_delay(void)
 620 {
 621         int i;
 622         u8 b;
 623         for(i=0;i<16;i++)
 624                 b=inb(0x80);
 625 }
 626
 627 #define TIMEOUT_LOOPS 300000
 628
 629 #define DCALCSR  0x100
 630 #define DCALADDR 0x104
 631 #define DCALDATA 0x108
 632
 633 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 634 {
 635         u8 c1,c2;
 636         u32 dimm,i;
 637         u32 data32;
 638         u32 t4;
 639
 640         /* Set up northbridge values */
 641         /* ODT enable */
 642         pci_write_config32(ctrl->f0, SDRC, 0x30000000);
 643         /* Figure out which slots are Empty, Single, or Double sided */
 644         for(i=0,t4=0,c2=0;i<8;i+=2) {
 645                 c1 = pci_read_config8(ctrl->f0, DRB+i);
 646                 if(c1 == c2) continue;
 647                 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
 648                 if(c1 == c2)
 649                         t4 |= (1 << (i*4));
 650                 else
 651                         t4 |= (2 << (i*4));
 652         }
 653         for(i=0;i<1;i++) {
 654             if((t4&0x0f) == 1) {
 655                 if( ((t4>>8)&0x0f) == 0 ) {
 656                         data32 = 0x00000010; /* EEES */
 657                         break;
 658                 }
 659                 if ( ((t4>>16)&0x0f) == 0 ) {
 660                         data32 = 0x00003132; /* EESS */
 661                         break;
 662                 }
 663                 if ( ((t4>>24)&0x0f)  == 0 ) {
 664                         data32 = 0x00335566; /* ESSS */
 665                         break;
 666                 }
 667                 data32 = 0x77bbddee; /* SSSS */
 668                 break;
 669             }
 670             if((t4&0x0f) == 2) {
 671                 if( ((t4>>8)&0x0f) == 0 ) {
 672                         data32 = 0x00003132; /* EEED */
 673                         break;
 674                 }
 675                 if ( ((t4>>8)&0x0f) == 2 ) {
 676                         data32 = 0xb373ecdc; /* EEDD */
 677                         break;
 678                 }
 679                 if ( ((t4>>16)&0x0f) == 0 ) {
 680                         data32 = 0x00b3a898; /* EESD */
 681                         break;
 682                 }
 683                 data32 = 0x777becdc; /* ESSD */
 684                 break;
 685             }
 686             die("Error - First dimm slot empty\r\n");
 687         }
 688
 689         print_debug("ODT Value = ");
 690         print_debug_hex32(data32);
 691         print_debug("\r\n");
 692
 693         pci_write_config32(ctrl->f0, DDR2ODTC, data32);
 694
 695         for(dimm=0;dimm<8;dimm+=2) {
 696
 697                 write32(MCBAR+DCALADDR, 0x0b840001);
 698                 write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
 699
 700                 for(i=0;i<1001;i++) {
 701                         data32 = read32(MCBAR+DCALCSR);
 702                         if(!(data32 & (1<<31)))
 703                                 break;
 704                 }
 705         }
 706 }
 707 static void set_receive_enable(const struct mem_controller *ctrl)
 708 {
 709         u32 i;
 710         u32 cnt;
 711         u32 recena=0;
 712         u32 recenb=0;
 713
 714         {
 715         u32 dimm;
 716         u32 edge;
 717         int32_t data32;
 718         u32 data32_dram;
 719         u32 dcal_data32_0;
 720         u32 dcal_data32_1;
 721         u32 dcal_data32_2;
 722         u32 dcal_data32_3;
 723         u32 work32l;
 724         u32 work32h;
 725         u32 data32r;
 726         int32_t recen;
 727         for(dimm=0;dimm<8;dimm+=1) {
 728
 729                 if(!(dimm&1)) {
 730                         write32(MCBAR+DCALDATA+(17*4), 0x04020000);
 731                         write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
 732
 733                         for(i=0;i<1001;i++) {
 734                                 data32 = read32(MCBAR+DCALCSR);
 735                                 if(!(data32 & (1<<31)))
 736                                         break;
 737                         }
 738                         if(i>=1000)
 739                                 continue;
 740
 741                         dcal_data32_0 = read32(MCBAR+DCALDATA + 0);
 742                         dcal_data32_1 = read32(MCBAR+DCALDATA + 4);
 743                         dcal_data32_2 = read32(MCBAR+DCALDATA + 8);
 744                         dcal_data32_3 = read32(MCBAR+DCALDATA + 12);
 745                 }
 746                 else {
 747                         dcal_data32_0 = read32(MCBAR+DCALDATA + 16);
 748                         dcal_data32_1 = read32(MCBAR+DCALDATA + 20);
 749                         dcal_data32_2 = read32(MCBAR+DCALDATA + 24);
 750                         dcal_data32_3 = read32(MCBAR+DCALDATA + 28);
 751                 }
 752
 753                 /* check if bank is installed */
 754                 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
 755                         continue;
 756                 /* Calculate the timing value */
 757                 {
 758                 u32 bit;
 759                 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
 760                         work32l=dcal_data32_1,work32h=dcal_data32_3;
 761                                 (i<4) && bit; i++) {
 762                         for(;;bit--,cnt--) {
 763                                 if(work32l & (1<<cnt))
 764                                         break;
 765                                 if(!cnt) {
 766                                         work32l = dcal_data32_0;
 767                                         work32h = dcal_data32_2;
 768                                         cnt = 32;
 769                                 }
 770                                 if(!bit) break;
 771                         }
 772                         for(;;bit--,cnt--) {
 773                                 if(!(work32l & (1<<cnt)))
 774                                         break;
 775                                 if(!cnt) {
 776                                         work32l = dcal_data32_0;
 777                                         work32h = dcal_data32_2;
 778                                         cnt = 32;
 779                                 }
 780                                 if(!bit) break;
 781                         }
 782                         if(!bit) {
 783                                 break;
 784                         }
 785                         data32 = ((bit%8) << 1);
 786                         if(work32h & (1<<cnt))
 787                                 data32 += 1;
 788                         if(data32 < 4) {
 789                                 if(!edge) {
 790                                         edge = 1;
 791                                 }
 792                                 else {
 793                                         if(edge != 1) {
 794                                                 data32 = 0x0f;
 795                                         }
 796                                 }
 797                         }
 798                         if(data32 > 12) {
 799                                 if(!edge) {
 800                                         edge = 2;
 801                                 }
 802                                 else {
 803                                         if(edge != 2) {
 804                                                 data32 = 0x00;
 805                                         }
 806                                 }
 807                         }
 808                         data32r += data32;
 809                 }
 810                 }
 811                 work32l = dcal_data32_0;
 812                 work32h = dcal_data32_2;
 813                 recen = data32r;
 814                 recen += 3;
 815                 recen = recen>>2;
 816                 for(cnt=5;cnt<24;) {
 817                         for(;;cnt++)
 818                                 if(!(work32l & (1<<cnt)))
 819                                         break;
 820                         for(;;cnt++) {
 821                                 if(work32l & (1<<cnt))
 822                                         break;
 823                         }
 824                         data32 = (((cnt-1)%8)<<1);
 825                         if(work32h & (1<<(cnt-1))) {
 826                                 data32++;
 827                         }
 828                         /* test for frame edge cross overs */
 829                         if((edge == 1) && (data32 > 12) &&
 830                             (((recen+16)-data32) < 3)) {
 831                                 data32 = 0;
 832                                 cnt += 2;
 833                         }
 834                         if((edge == 2) && (data32 < 4) &&
 835                             ((recen - data32) > 12))  {
 836                                 data32 = 0x0f;
 837                                 cnt -= 2;
 838                         }
 839                         if(((recen+3) >= data32) && ((recen-3) <= data32))
 840                                 break;
 841                 }
 842                 cnt--;
 843                 cnt /= 8;
 844                 cnt--;
 845                 if(recen&1)
 846                         recen+=2;
 847                 recen >>= 1;
 848                 recen += (cnt*8);
 849                 recen+=2;      /* this is not in the spec, but matches
 850                                  the factory output, and has less failure */
 851                 recen <<= (dimm/2) * 8;
 852                 if(!(dimm&1)) {
 853                         recena |= recen;
 854                 }
 855                 else {
 856                         recenb |= recen;
 857                 }
 858         }
 859         }
 860         /* Check for Eratta problem */
 861         for(i=cnt=0;i<32;i+=8) {
 862                 if (((recena>>i)&0x0f)>7) {
 863                         cnt+= 0x101;
 864                 }
 865                 else {
 866                         if((recena>>i)&0x0f) {
 867                                 cnt++;
 868                         }
 869                 }
 870         }
 871         if(cnt&0x0f00) {
 872                 cnt = (cnt&0x0f) - (cnt>>16);
 873                 if(cnt>1) {
 874                         for(i=0;i<32;i+=8) {
 875                                 if(((recena>>i)&0x0f)>7) {
 876                                         recena &= ~(0x0f<<i);
 877                                         recena |= (7<<i);
 878                                 }
 879                         }
 880                 }
 881                 else {
 882                         for(i=0;i<32;i+=8) {
 883                                 if(((recena>>i)&0x0f)<8) {
 884                                         recena &= ~(0x0f<<i);
 885                                         recena |= (8<<i);
 886                                 }
 887                         }
 888                 }
 889         }
 890         for(i=cnt=0;i<32;i+=8) {
 891                 if (((recenb>>i)&0x0f)>7) {
 892                         cnt+= 0x101;
 893                 }
 894                 else {
 895                         if((recenb>>i)&0x0f) {
 896                                 cnt++;
 897                         }
 898                 }
 899         }
 900         if(cnt & 0x0f00) {
 901                 cnt = (cnt&0x0f) - (cnt>>16);
 902                 if(cnt>1) {
 903                         for(i=0;i<32;i+=8) {
 904                                 if(((recenb>>i)&0x0f)>7) {
 905                                         recenb &= ~(0x0f<<i);
 906                                         recenb |= (7<<i);
 907                                 }
 908                         }
 909                 }
 910                 else {
 911                         for(i=0;i<32;i+=8) {
 912                                 if(((recenb>>8)&0x0f)<8) {
 913                                         recenb &= ~(0x0f<<i);
 914                                         recenb |= (8<<i);
 915                                 }
 916                         }
 917                 }
 918         }
 919
 920         print_debug("Receive enable A = ");
 921         print_debug_hex32(recena);
 922         print_debug(",  Receive enable B = ");
 923         print_debug_hex32(recenb);
 924         print_debug("\r\n");
 925
 926         /* clear out the calibration area */
 927         write32(MCBAR+DCALDATA+(16*4), 0x00000000);
 928         write32(MCBAR+DCALDATA+(17*4), 0x00000000);
 929         write32(MCBAR+DCALDATA+(18*4), 0x00000000);
 930         write32(MCBAR+DCALDATA+(19*4), 0x00000000);
 931
 932         /* No command */
 933         write32(MCBAR+DCALCSR, 0x0000000f);
 934
 935         write32(MCBAR+0x150, recena);
 936         write32(MCBAR+0x154, recenb);
 937 }
 938
 939
 940 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 941 {
 942         int i;
 943         int cs;
 944         int cnt;
 945         int cas_latency;
 946         long mask;
 947         u32 drc;
 948         u32 data32;
 949         u32 mode_reg;
 950         u32 *iptr;
 951         volatile u32 *iptrv;
 952         msr_t msr;
 953         u32 scratch;
 954         u8 byte;
 955         u16 data16;
 956         static const struct {
 957                 u32 clkgr[4];
 958         } gearing [] = {
 959                 /* FSB 100 */
 960         {{ 0x00000010, 0x00000000, 0x00000002, 0x00000001}},
 961                 /* FSB 133 */
 962         {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
 963                 /* FSB 167 */
 964         {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
 965                 /* FSB 200 DIMM 400 */
 966         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
 967         };
 968
 969         static const u32 dqs_data[] = {
 970                 0xffffffff, 0xffffffff, 0x000000ff,
 971                 0xffffffff, 0xffffffff, 0x000000ff,
 972                 0xffffffff, 0xffffffff, 0x000000ff,
 973                 0xffffffff, 0xffffffff, 0x000000ff,
 974                 0xffffffff, 0xffffffff, 0x000000ff,
 975                 0xffffffff, 0xffffffff, 0x000000ff,
 976                 0xffffffff, 0xffffffff, 0x000000ff,
 977                 0xffffffff, 0xffffffff, 0x000000ff};
 978
 979         mask = spd_detect_dimms(ctrl);
 980         print_debug("Starting SDRAM Enable\r\n");
 981
 982         /* 0x80 */
 983 #ifdef DIMM_MAP_LOGICAL
 984         pci_write_config32(ctrl->f0, DRM,
 985                 0x00410000 | DIMM_MAP_LOGICAL);
 986 #else
 987         pci_write_config32(ctrl->f0, DRM, 0x00411248);
 988 #endif
 989         /* set dram type and Front Side Bus freq. */
 990         drc = spd_set_dram_controller_mode(ctrl, mask);
 991         if( drc == 0) {
 992                 die("Error calculating DRC\r\n");
 993         }
 994         data32 = drc & ~(3 << 20);  /* clear ECC mode */
 995         data32 = data32 & ~(7 << 8);  /* clear refresh rates */
 996         data32 = data32 | (1 << 5);  /* temp turn off ODT */
 997         /* Set gearing, then dram controller mode */
 998         /* drc bits 3:2 = FSB speed */
 999         for(iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
1000                 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
1001         }
1002         /* 0x7c DRC */
1003         pci_write_config32(ctrl->f0, DRC, data32);
1004
1005                 /* turn the clocks on */
1006         /* 0x8c CKDIS */
1007         pci_write_config16(ctrl->f0, CKDIS, 0x0000);
1008
1009                 /* 0x9a DDRCSR Take subsystem out of idle */
1010         data16 = pci_read_config16(ctrl->f0, DDRCSR);
1011         data16 &= ~(7 << 12);
1012         data16 |= (1 << 12);
1013         pci_write_config16(ctrl->f0, DDRCSR, data16);
1014
1015                 /* program row size DRB */
1016         spd_set_ram_size(ctrl, mask);
1017
1018                 /* program page size DRA */
1019         spd_set_row_attributes(ctrl, mask);
1020
1021                 /* program DRT timing values */
1022         cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1023
1024         for(i=0;i<8;i+=2) { /* loop through each dimm to test */
1025                 print_debug("DIMM ");
1026                 print_debug_hex8(i);
1027                 print_debug("\r\n");
1028                 /* Apply NOP */
1029                 do_delay();
1030
1031                 write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
1032                 write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
1033
1034                 data32 = read32(MCBAR+DCALCSR);
1035                 while(data32 & 0x80000000)
1036                         data32 = read32(MCBAR+DCALCSR);
1037         }
1038
1039         /* Apply NOP */
1040         do_delay();
1041
1042         for(cs=0;cs<8;cs+=2) {
1043                 write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
1044                 data32 = read32(MCBAR+DCALCSR);
1045                 while(data32 & 0x80000000)
1046                         data32 = read32(MCBAR+DCALCSR);
1047         }
1048
1049         /* Precharg all banks */
1050         do_delay();
1051         for(cs=0;cs<8;cs+=2) {
1052                 write32(MCBAR+DCALADDR, 0x04000000);
1053                 write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
1054                 data32 = read32(MCBAR+DCALCSR);
1055                 while(data32 & 0x80000000)
1056                         data32 = read32(MCBAR+DCALCSR);
1057         }
1058
1059         /* EMRS dll's enabled */
1060         do_delay();
1061         for(cs=0;cs<8;cs+=2) {
1062                 /* fixme hard code AL additive latency */
1063                 write32(MCBAR+DCALADDR, 0x0b940001);
1064                 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1065                 data32 = read32(MCBAR+DCALCSR);
1066                 while(data32 & 0x80000000)
1067                         data32 = read32(MCBAR+DCALCSR);
1068         }
1069         /* MRS reset dll's */
1070         do_delay();
1071         if(cas_latency == 30)
1072                 mode_reg = 0x053a0000;
1073         else
1074                 mode_reg = 0x054a0000;
1075         for(cs=0;cs<8;cs+=2) {
1076                 write32(MCBAR+DCALADDR, mode_reg);
1077                 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1078                 data32 = read32(MCBAR+DCALCSR);
1079                 while(data32 & 0x80000000)
1080                         data32 = read32(MCBAR+DCALCSR);
1081         }
1082
1083         /* Precharg all banks */
1084         do_delay();
1085         do_delay();
1086         do_delay();
1087         for(cs=0;cs<8;cs+=2) {
1088                 write32(MCBAR+DCALADDR, 0x04000000);
1089                 write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
1090                 data32 = read32(MCBAR+DCALCSR);
1091                 while(data32 & 0x80000000)
1092                         data32 = read32(MCBAR+DCALCSR);
1093         }
1094
1095         /* Do 2 refreshes */
1096         do_delay();
1097         for(cs=0;cs<8;cs+=2) {
1098                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1099                 data32 = read32(MCBAR+DCALCSR);
1100                 while(data32 & 0x80000000)
1101                         data32 = read32(MCBAR+DCALCSR);
1102         }
1103         do_delay();
1104         for(cs=0;cs<8;cs+=2) {
1105                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1106                 data32 = read32(MCBAR+DCALCSR);
1107                 while(data32 & 0x80000000)
1108                         data32 = read32(MCBAR+DCALCSR);
1109         }
1110         do_delay();
1111         /* for good luck do 6 more */
1112         for(cs=0;cs<8;cs+=2) {
1113                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1114         }
1115         do_delay();
1116         for(cs=0;cs<8;cs+=2) {
1117                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1118         }
1119         do_delay();
1120         for(cs=0;cs<8;cs+=2) {
1121                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1122         }
1123         do_delay();
1124         for(cs=0;cs<8;cs+=2) {
1125                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1126         }
1127         do_delay();
1128         for(cs=0;cs<8;cs+=2) {
1129                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1130         }
1131         do_delay();
1132         for(cs=0;cs<8;cs+=2) {
1133                 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1134         }
1135         do_delay();
1136         /* MRS reset dll's normal */
1137         do_delay();
1138         for(cs=0;cs<8;cs+=2) {
1139                 write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
1140                 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1141                 data32 = read32(MCBAR+DCALCSR);
1142                 while(data32 & 0x80000000)
1143                         data32 = read32(MCBAR+DCALCSR);
1144         }
1145
1146         /* Do only if DDR2  EMRS dll's enabled */
1147         do_delay();
1148         for(cs=0;cs<8;cs+=2) {
1149                 write32(MCBAR+DCALADDR, (0x0b940001));
1150                 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1151                 data32 = read32(MCBAR+DCALCSR);
1152                 while(data32 & 0x80000000)
1153                         data32 = read32(MCBAR+DCALCSR);
1154         }
1155
1156         do_delay();
1157         /* No command */
1158         write32(MCBAR+DCALCSR, 0x0000000f);
1159
1160         /* enable on dimm termination */
1161         set_on_dimm_termination_enable(ctrl);
1162
1163         /* receive enable calibration */
1164         set_receive_enable(ctrl);
1165
1166         /* DQS */
1167         pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
1168         for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
1169                 write32(cnt, dqs_data[i]);
1170         }
1171         pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
1172
1173         /* Enable refresh */
1174         /* 0x7c DRC */
1175         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1176         pci_write_config32(ctrl->f0, DRC, data32);
1177         write32(MCBAR+DCALCSR, 0x0008000f);
1178
1179         /* clear memory and init ECC */
1180         print_debug("Clearing memory\r\n");
1181         for(i=0;i<64;i+=4) {
1182                 write32(MCBAR+DCALDATA+i, 0x00000000);
1183         }
1184
1185         for(cs=0;cs<8;cs+=2) {
1186                 write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
1187                 data32 = read32(MCBAR+DCALCSR);
1188                 while(data32 & 0x80000000)
1189                         data32 = read32(MCBAR+DCALCSR);
1190         }
1191
1192         /* Bring memory subsystem on line */
1193         data32 = pci_read_config32(ctrl->f0, 0x98);
1194         data32 |= (1 << 31);
1195         pci_write_config32(ctrl->f0, 0x98, data32);
1196         /* wait for completion */
1197         print_debug("Waiting for mem complete\r\n");
1198         while(1) {
1199                 data32 = pci_read_config32(ctrl->f0, 0x98);
1200                 if( (data32 & (1<<31)) == 0)
1201                         break;
1202         }
1203         print_debug("Done\r\n");
1204
1205         /* Set initialization complete */
1206         /* 0x7c DRC */
1207         drc |= (1 << 29);
1208         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1209         pci_write_config32(ctrl->f0, DRC, data32);
1210
1211         /* Set the ecc mode */
1212         pci_write_config32(ctrl->f0, DRC, drc);
1213
1214         /* Enable memory scrubbing */
1215         /* 0x52 MCHSCRB */
1216         data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1217         data16 &= ~0x0f;
1218         data16 |= ((2 << 2) | (2 << 0));
1219         pci_write_config16(ctrl->f0, MCHSCRB, data16);
1220
1221         /* The memory is now setup, use it */
1222 #if CONFIG_USE_DCACHE_RAM == 0
1223         cache_lbmem(MTRR_TYPE_WRBACK);
1224 #endif
1225 }