2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 4DSP Inc
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* This code is based on src/northbridge/intel/i3100/pciexp_porta.c */
23 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
27 #include <device/pci_ops.h>
28 #include <device/pciexp.h>
33 typedef struct northbridge_intel_i3100_config config_t;
35 static void pcie_init(struct device *dev)
40 /* Get the chip configuration */
41 config = dev->chip_info;
43 if(config->intrline) {
44 pci_write_config32(dev, 0x3c, config->intrline);
47 printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n");
48 val = pci_read_config16(dev, 0x66);
51 pci_write_config16(dev, 0x66, val);
53 /* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */
57 static void pcie_bus_enable_resources(struct device *dev)
59 if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
60 printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n");
61 pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8);
63 dev->command |= PCI_COMMAND_IO;
64 dev->command |= PCI_COMMAND_MEMORY;
66 pci_dev_enable_resources(dev);
70 static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
76 val = pci_read_config16(dev, 0x76);
77 printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
78 if ((val & (1<<11)) && (!flag)) { /* training error */
79 ctl = pci_read_config16(dev, 0x74);
80 pci_write_config16(dev, 0x74, (ctl | (1<<5)));
81 val = pci_read_config16(dev, 0x76);
82 printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
86 } while (val & (3<<10));
87 return pciexp_scan_bridge(dev, max);
90 static struct device_operations pcie_ops = {
91 .read_resources = pci_bus_read_resources,
92 .set_resources = pci_dev_set_resources,
93 .enable_resources = pcie_bus_enable_resources,
95 .scan_bus = pcie_scan_bridge,
96 .reset_bus = pci_bus_reset,
100 static const struct pci_driver pci_driver_0 __pci_driver = {
102 .vendor = PCI_VENDOR_ID_INTEL,
103 .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0,
106 static const struct pci_driver pci_driver_1 __pci_driver = {
108 .vendor = PCI_VENDOR_ID_INTEL,
109 .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1,