src/northbridge/intel/i3100/northbridge.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Arastra, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  *
  19  */
  20
  21 /* This code is based on src/northbridge/intel/e7520/northbridge.c */
  22
  23 #include <console/console.h>
  24 #include <arch/io.h>
  25 #include <stdint.h>
  26 #include <device/device.h>
  27 #include <device/pci.h>
  28 #include <device/pci_ids.h>
  29 #include <device/hypertransport.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <bitops.h>
  33 #include <cpu/cpu.h>
  34 #include "chip.h"
  35 #include "i3100.h"
  36
  37
  38 static u32 max_bus;
  39
  40 #if CONFIG_WRITE_HIGH_TABLES==1
  41 #include <cbmem.h>
  42 #endif
  43
  44 static void pci_domain_set_resources(device_t dev)
  45 {
  46         device_t mc_dev;
  47         u32 pci_tolm;
  48
  49         pci_tolm = find_pci_tolm(dev->link_list);
  50
  51 #if 1
  52         printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
  53 #endif
  54         /* FIXME Me temporary hack */
  55         if(pci_tolm > 0xe0000000)
  56                 pci_tolm = 0xe0000000;
  57         /* Ensure pci_tolm is 128M aligned */
  58         pci_tolm &= 0xf8000000;
  59         mc_dev = dev->link_list->children;
  60         if (mc_dev) {
  61                 /* Figure out which areas are/should be occupied by RAM.
  62                  * This is all computed in kilobytes and converted to/from
  63                  * the memory controller right at the edges.
  64                  * Having different variables in different units is
  65                  * too confusing to get right.  Kilobytes are good up to
  66                  * 4 Terabytes of RAM...
  67                  */
  68                 u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
  69                 u32 tomk, tolmk;
  70                 u32 remapbasek, remaplimitk, remapoffsetk;
  71
  72                 /* Get the Top of Memory address, units are 128M */
  73                 tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17;
  74                 /* Compute the Top of Low Memory */
  75                 tolmk = (pci_tolm  & 0xf8000000) >> 10;
  76
  77                 if (tolmk >= tomk) {
  78                         /* The PCI hole does not overlap memory
  79                          * we won't use the remap window.
  80                          */
  81                         tolmk = tomk;
  82                         remapbasek   = 0x3ff << 16;
  83                         remaplimitk  = 0 << 16;
  84                         remapoffsetk = 0 << 16;
  85                 }
  86                 else {
  87                         /* The PCI memory hole overlaps memory
  88                          * setup the remap window.
  89                          */
  90                         /* Find the bottom of the remap window
  91                          * is it above 4G?
  92                          */
  93                         remapbasek = 4*1024*1024;
  94                         if (tomk > remapbasek) {
  95                                 remapbasek = tomk;
  96                         }
  97                         /* Find the limit of the remap window */
  98                         remaplimitk  = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
  99                         /* Find the offset of the remap window from tolm */
 100                         remapoffsetk = remapbasek - tolmk;
 101                 }
 102                 /* Write the ram configruation registers,
 103                  * preserving the reserved bits.
 104                  */
 105                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 106                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 107                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 108
 109                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 110                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 111                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 112
 113                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 114                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 115                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 116
 117                 remapoffset_r = pci_read_config16(mc_dev, 0xca);
 118                 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
 119                 pci_write_config16(mc_dev, 0xca, remapoffset_r);
 120
 121                 /* Report the memory regions */
 122                 ram_resource(dev, 3,   0, 640);
 123                 ram_resource(dev, 4, 768, (tolmk - 768));
 124                 if (tomk > 4*1024*1024) {
 125                         ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
 126                 }
 127                 if (remaplimitk >= remapbasek) {
 128                         ram_resource(dev, 6, remapbasek,
 129                                 (remaplimitk + 64*1024) - remapbasek);
 130                 }
 131
 132 #if CONFIG_WRITE_HIGH_TABLES==1
 133                 /* Leave some space for ACPI, PIRQ and MP tables */
 134                 high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
 135                 high_tables_size = HIGH_MEMORY_SIZE;
 136 #endif
 137         }
 138         assign_resources(dev->link_list);
 139 }
 140
 141 static u32 i3100_domain_scan_bus(device_t dev, u32 max)
 142 {
 143         max_bus = pci_domain_scan_bus(dev, max);
 144         return max_bus;
 145 }
 146
 147 static struct device_operations pci_domain_ops = {
 148         .read_resources   = pci_domain_read_resources,
 149         .set_resources    = pci_domain_set_resources,
 150         .enable_resources = NULL,
 151         .init             = NULL,
 152         .scan_bus         = i3100_domain_scan_bus,
 153         .ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 154 };
 155
 156 static void mc_read_resources(device_t dev)
 157 {
 158         struct resource *resource;
 159
 160         pci_dev_read_resources(dev);
 161
 162         resource = new_resource(dev, 0xcf);
 163         resource->base = 0xe0000000;
 164         resource->size = max_bus * 4096*256;
 165         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
 166 }
 167
 168 static void mc_set_resources(device_t dev)
 169 {
 170         struct resource *resource;
 171
 172         resource = find_resource(dev, 0xcf);
 173         if (resource) {
 174                 report_resource_stored(dev, resource, "<mmconfig>");
 175         }
 176         pci_dev_set_resources(dev);
 177 }
 178
 179 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 180 {
 181         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 182                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 183 }
 184
 185 static struct pci_operations intel_pci_ops = {
 186         .set_subsystem = intel_set_subsystem,
 187 };
 188
 189 static struct device_operations mc_ops = {
 190         .read_resources   = mc_read_resources,
 191         .set_resources    = mc_set_resources,
 192         .enable_resources = pci_dev_enable_resources,
 193         .init             = 0,
 194         .scan_bus         = 0,
 195         .ops_pci          = &intel_pci_ops,
 196 };
 197
 198 static const struct pci_driver mc_driver __pci_driver = {
 199         .ops = &mc_ops,
 200         .vendor = PCI_VENDOR_ID_INTEL,
 201         .device = PCI_DEVICE_ID_INTEL_3100_MC,
 202 };
 203
 204 static void cpu_bus_init(device_t dev)
 205 {
 206         initialize_cpus(dev->link_list);
 207 }
 208
 209 static void cpu_bus_noop(device_t dev)
 210 {
 211 }
 212
 213 static struct device_operations cpu_bus_ops = {
 214         .read_resources   = cpu_bus_noop,
 215         .set_resources    = cpu_bus_noop,
 216         .enable_resources = cpu_bus_noop,
 217         .init             = cpu_bus_init,
 218         .scan_bus         = 0,
 219 };
 220
 221
 222 static void enable_dev(device_t dev)
 223 {
 224         /* Set the operations if it is a special bus type */
 225         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 226                 dev->ops = &pci_domain_ops;
 227         }
 228         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 229                 dev->ops = &cpu_bus_ops;
 230         }
 231 }
 232
 233 struct chip_operations northbridge_intel_i3100_ops = {
 234         CHIP_NAME("Intel 3100 Northbridge")
 235         .enable_dev = enable_dev,
 236 };