2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* This code is based on src/northbridge/intel/e7520/northbridge.c */
23 #include <console/console.h>
26 #include <device/device.h>
27 #include <device/pci.h>
28 #include <device/pci_ids.h>
29 #include <device/hypertransport.h>
40 static void ram_resource(device_t dev, u32 index,
43 struct resource *resource;
45 resource = new_resource(dev, index);
46 resource->base = ((resource_t)basek) << 10;
47 resource->size = ((resource_t)sizek) << 10;
48 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
49 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
53 static void pci_domain_read_resources(device_t dev)
55 struct resource *resource;
57 /* Initialize the system wide io space constraints */
58 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
63 resource->limit = 0xffffUL;
64 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
66 /* Initialize the system wide memory resources constraints */
67 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
72 resource->limit = 0xffffffffUL;
73 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
76 static void tolm_test(void *gp, struct device *dev, struct resource *new)
78 struct resource **best_p = gp;
79 struct resource *best;
81 if (!best || (best->base > new->base)) {
87 static u32 find_pci_tolm(struct bus *bus)
92 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
94 if (min && tolm > min->base) {
100 #if HAVE_HIGH_TABLES==1
101 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
102 extern uint64_t high_tables_base, high_tables_size;
105 static void pci_domain_set_resources(device_t dev)
110 pci_tolm = find_pci_tolm(&dev->link[0]);
113 printk_debug("PCI mem marker = %x\n", pci_tolm);
115 /* FIXME Me temporary hack */
116 if(pci_tolm > 0xe0000000)
117 pci_tolm = 0xe0000000;
118 /* Ensure pci_tolm is 128M aligned */
119 pci_tolm &= 0xf8000000;
120 mc_dev = dev->link[0].children;
122 /* Figure out which areas are/should be occupied by RAM.
123 * This is all computed in kilobytes and converted to/from
124 * the memory controller right at the edges.
125 * Having different variables in different units is
126 * too confusing to get right. Kilobytes are good up to
127 * 4 Terabytes of RAM...
129 u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
131 u32 remapbasek, remaplimitk, remapoffsetk;
133 /* Get the Top of Memory address, units are 128M */
134 tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17;
135 /* Compute the Top of Low Memory */
136 tolmk = (pci_tolm & 0xf8000000) >> 10;
139 /* The PCI hole does not overlap memory
140 * we won't use the remap window.
143 remapbasek = 0x3ff << 16;
144 remaplimitk = 0 << 16;
145 remapoffsetk = 0 << 16;
148 /* The PCI memory hole overlaps memory
149 * setup the remap window.
151 /* Find the bottom of the remap window
154 remapbasek = 4*1024*1024;
155 if (tomk > remapbasek) {
158 /* Find the limit of the remap window */
159 remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
160 /* Find the offset of the remap window from tolm */
161 remapoffsetk = remapbasek - tolmk;
163 /* Write the ram configruation registers,
164 * preserving the reserved bits.
166 tolm_r = pci_read_config16(mc_dev, 0xc4);
167 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
168 pci_write_config16(mc_dev, 0xc4, tolm_r);
170 remapbase_r = pci_read_config16(mc_dev, 0xc6);
171 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
172 pci_write_config16(mc_dev, 0xc6, remapbase_r);
174 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
175 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
176 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
178 remapoffset_r = pci_read_config16(mc_dev, 0xca);
179 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
180 pci_write_config16(mc_dev, 0xca, remapoffset_r);
182 /* Report the memory regions */
183 ram_resource(dev, 3, 0, 640);
184 ram_resource(dev, 4, 768, (tolmk - 768));
185 if (tomk > 4*1024*1024) {
186 ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
188 if (remaplimitk >= remapbasek) {
189 ram_resource(dev, 6, remapbasek,
190 (remaplimitk + 64*1024) - remapbasek);
193 #if HAVE_HIGH_TABLES==1
194 /* Leave some space for ACPI, PIRQ and MP tables */
195 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
196 high_tables_size = HIGH_TABLES_SIZE * 1024;
199 assign_resources(&dev->link[0]);
202 static u32 pci_domain_scan_bus(device_t dev, u32 max)
204 max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
211 static struct device_operations pci_domain_ops = {
212 .read_resources = pci_domain_read_resources,
213 .set_resources = pci_domain_set_resources,
214 .enable_resources = enable_childrens_resources,
216 .scan_bus = pci_domain_scan_bus,
217 .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
220 static void mc_read_resources(device_t dev)
222 struct resource *resource;
224 pci_dev_read_resources(dev);
226 resource = new_resource(dev, 0xcf);
227 resource->base = 0xe0000000;
228 resource->size = max_bus * 4096*256;
229 resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
232 static void mc_set_resources(device_t dev)
234 struct resource *resource, *last;
236 last = &dev->resource[dev->resources];
237 resource = find_resource(dev, 0xcf);
239 report_resource_stored(dev, resource, "<mmconfig>");
241 pci_dev_set_resources(dev);
244 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
246 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
247 ((device & 0xffff) << 16) | (vendor & 0xffff));
250 static struct pci_operations intel_pci_ops = {
251 .set_subsystem = intel_set_subsystem,
254 static struct device_operations mc_ops = {
255 .read_resources = mc_read_resources,
256 .set_resources = mc_set_resources,
257 .enable_resources = pci_dev_enable_resources,
260 .ops_pci = &intel_pci_ops,
263 static struct pci_driver mc_driver __pci_driver = {
265 .vendor = PCI_VENDOR_ID_INTEL,
266 .device = PCI_DEVICE_ID_INTEL_3100_MC,
269 static void cpu_bus_init(device_t dev)
271 initialize_cpus(&dev->link[0]);
274 static void cpu_bus_noop(device_t dev)
278 static struct device_operations cpu_bus_ops = {
279 .read_resources = cpu_bus_noop,
280 .set_resources = cpu_bus_noop,
281 .enable_resources = cpu_bus_noop,
282 .init = cpu_bus_init,
287 static void enable_dev(device_t dev)
289 /* Set the operations if it is a special bus type */
290 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
291 dev->ops = &pci_domain_ops;
293 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
294 dev->ops = &cpu_bus_ops;
298 struct chip_operations northbridge_intel_i3100_ops = {
299 CHIP_NAME("Intel 3100 Northbridge")
300 .enable_dev = enable_dev,