src/northbridge/intel/e7525/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  *
  19  */
  20
  21 #include <cpu/x86/mtrr.h>
  22 #include <cpu/x86/cache.h>
  23 #include <stdlib.h>
  24 #include "raminit.h"
  25 #include "e7525.h"
  26 #if CONFIG_HAVE_OPTION_TABLE
  27 #include "option_table.h"
  28 #endif
  29
  30 #define BAR 0x40000000
  31
  32 static void sdram_set_registers(const struct mem_controller *ctrl)
  33 {
  34         static const unsigned int register_values[] = {
  35
  36                 /* CKDIS 0x8c disable clocks */
  37         PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
  38
  39                 /* 0x9c Device present and extended RAM control
  40                  * DEVPRES is very touchy, hard code the initialization
  41                  * of PCI-E ports here.
  42                  */
  43         PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
  44
  45                 /* 0xc8 Remap RAM base and limit off */
  46         PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
  47
  48                 /* ??? */
  49         PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
  50         PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
  51
  52                 /* 0x50 scrub */
  53         PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
  54
  55                 /* 0x58 0x5c PAM */
  56         PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
  57         PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
  58
  59                 /* 0xf4 */
  60         PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
  61
  62                 /* 0x14 */
  63         PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,
  64         };
  65         int i;
  66         int max;
  67
  68         max = ARRAY_SIZE(register_values);
  69         for(i = 0; i < max; i += 3) {
  70                 device_t dev;
  71                 unsigned where;
  72                 unsigned long reg;
  73                 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
  74                 where = register_values[i] & 0xff;
  75                 reg = pci_read_config32(dev, where);
  76                 reg &= register_values[i+1];
  77                 reg |= register_values[i+2];
  78                 pci_write_config32(dev, where, reg);
  79         }
  80         print_spew("done.\n");
  81 }
  82
  83
  84
  85 struct dimm_size {
  86         unsigned long side1;
  87         unsigned long side2;
  88 };
  89
  90 static struct dimm_size spd_get_dimm_size(unsigned device)
  91 {
  92         /* Calculate the log base 2 size of a DIMM in bits */
  93         struct dimm_size sz;
  94         int value, low, ddr2;
  95         sz.side1 = 0;
  96         sz.side2 = 0;
  97
  98         /* test for ddr2 */
  99         ddr2=0;
 100         value = spd_read_byte(device, 2);       /* type */
 101         if (value < 0) goto hw_err;
 102         if (value == 8) ddr2 = 1;
 103
 104         /* Note it might be easier to use byte 31 here, it has the DIMM size as
 105          * a multiple of 4MB.  The way we do it now we can size both
 106          * sides of an assymetric dimm.
 107          */
 108         value = spd_read_byte(device, 3);       /* rows */
 109         if (value < 0) goto hw_err;
 110         if ((value & 0xf) == 0) goto val_err;
 111         sz.side1 += value & 0xf;
 112
 113         value = spd_read_byte(device, 4);       /* columns */
 114         if (value < 0) goto hw_err;
 115         if ((value & 0xf) == 0) goto val_err;
 116         sz.side1 += value & 0xf;
 117
 118         value = spd_read_byte(device, 17);      /* banks */
 119         if (value < 0) goto hw_err;
 120         if ((value & 0xff) == 0) goto val_err;
 121         sz.side1 += log2(value & 0xff);
 122
 123         /* Get the module data width and convert it to a power of two */
 124         value = spd_read_byte(device, 7);       /* (high byte) */
 125         if (value < 0) goto hw_err;
 126         value &= 0xff;
 127         value <<= 8;
 128
 129         low = spd_read_byte(device, 6); /* (low byte) */
 130         if (low < 0) goto hw_err;
 131         value = value | (low & 0xff);
 132         if ((value != 72) && (value != 64)) goto val_err;
 133         sz.side1 += log2(value);
 134
 135         /* side 2 */
 136         value = spd_read_byte(device, 5);       /* number of physical banks */
 137
 138         if (value < 0) goto hw_err;
 139         value &= 7;
 140         if(ddr2) value++;
 141         if (value == 1) goto out;
 142         if (value != 2) goto val_err;
 143
 144         /* Start with the symmetrical case */
 145         sz.side2 = sz.side1;
 146
 147         value = spd_read_byte(device, 3);       /* rows */
 148         if (value < 0) goto hw_err;
 149         if ((value & 0xf0) == 0) goto out;      /* If symmetrical we are done */
 150         sz.side2 -= (value & 0x0f);             /* Subtract out rows on side 1 */
 151         sz.side2 += ((value >> 4) & 0x0f);      /* Add in rows on side 2 */
 152
 153         value = spd_read_byte(device, 4);       /* columns */
 154         if (value < 0) goto hw_err;
 155         if ((value & 0xff) == 0) goto val_err;
 156         sz.side2 -= (value & 0x0f);             /* Subtract out columns on side 1 */
 157         sz.side2 += ((value >> 4) & 0x0f);      /* Add in columsn on side 2 */
 158         goto out;
 159
 160  val_err:
 161         die("Bad SPD value\n");
 162         /* If an hw_error occurs report that I have no memory */
 163 hw_err:
 164         sz.side1 = 0;
 165         sz.side2 = 0;
 166  out:
 167         return sz;
 168
 169 }
 170
 171 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 172 {
 173         int i;
 174         int cum;
 175
 176         for(i = cum = 0; i < DIMM_SOCKETS; i++) {
 177                 struct dimm_size sz;
 178                 if (dimm_mask & (1 << i)) {
 179                         sz = spd_get_dimm_size(ctrl->channel0[i]);
 180                         if (sz.side1 < 29) {
 181                                 return -1; /* Report SPD error */
 182                         }
 183                         /* convert bits to multiples of 64MB */
 184                         sz.side1 -= 29;
 185                         cum += (1 << sz.side1);
 186                         /* DRB = 0x60 */
 187                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 188                         if( sz.side2 > 28) {
 189                                 sz.side2 -= 29;
 190                                 cum += (1 << sz.side2);
 191                         }
 192                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 193                 }
 194                 else {
 195                         pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 196                         pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 197                 }
 198         }
 199         /* set TOM top of memory 0xcc */
 200         pci_write_config16(ctrl->f0, TOM, cum);
 201         /* set TOLM top of low memory */
 202         if(cum > 0x18) {
 203                 cum = 0x18;
 204         }
 205         cum <<= 11;
 206         /* 0xc4 TOLM */
 207         pci_write_config16(ctrl->f0, TOLM, cum);
 208         return 0;
 209 }
 210
 211
 212 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 213 {
 214         unsigned dimm_mask;
 215         int i;
 216         dimm_mask = 0;
 217         for(i = 0; i < DIMM_SOCKETS; i++) {
 218                 int byte;
 219                 unsigned device;
 220                 device = ctrl->channel0[i];
 221                 if (device) {
 222                         byte = spd_read_byte(device, 2);  /* Type */
 223                         if ((byte == 7) || (byte == 8)) {
 224                                 dimm_mask |= (1 << i);
 225                         }
 226                 }
 227                 device = ctrl->channel1[i];
 228                 if (device) {
 229                         byte = spd_read_byte(device, 2);
 230                         if ((byte == 7) || (byte == 8)) {
 231                                 dimm_mask |= (1 << (i + DIMM_SOCKETS));
 232                         }
 233                 }
 234         }
 235         return dimm_mask;
 236 }
 237
 238
 239 static int spd_set_row_attributes(const struct mem_controller *ctrl,
 240                 long dimm_mask)
 241 {
 242
 243         int value;
 244         int reg;
 245         int dra;
 246         int cnt;
 247
 248         dra = 0;
 249         for(cnt=0; cnt < 4; cnt++) {
 250                 if (!(dimm_mask & (1 << cnt))) {
 251                         continue;
 252                 }
 253                 reg =0;
 254                 value = spd_read_byte(ctrl->channel0[cnt], 3);  /* rows */
 255                 if (value < 0) goto hw_err;
 256                 if ((value & 0xf) == 0) goto val_err;
 257                 reg += value & 0xf;
 258
 259                 value = spd_read_byte(ctrl->channel0[cnt], 4);  /* columns */
 260                 if (value < 0) goto hw_err;
 261                 if ((value & 0xf) == 0) goto val_err;
 262                 reg += value & 0xf;
 263
 264                 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
 265                 if (value < 0) goto hw_err;
 266                 if ((value & 0xff) == 0) goto val_err;
 267                 reg += log2(value & 0xff);
 268
 269                 /* Get the device width and convert it to a power of two */
 270                 value = spd_read_byte(ctrl->channel0[cnt], 13);
 271                 if (value < 0) goto hw_err;
 272                 value = log2(value & 0xff);
 273                 reg += value;
 274                 if(reg < 27) goto hw_err;
 275                 reg -= 27;
 276                 reg += (value << 2);
 277
 278                 dra += reg << (cnt*8);
 279                 value = spd_read_byte(ctrl->channel0[cnt], 5);
 280                 if (value & 2)
 281                         dra += reg << ((cnt*8)+4);
 282         }
 283
 284         /* 0x70 DRA */
 285         pci_write_config32(ctrl->f0, DRA, dra);
 286         goto out;
 287
 288  val_err:
 289         die("Bad SPD value\n");
 290         /* If an hw_error occurs report that I have no memory */
 291 hw_err:
 292         dra = 0;
 293  out:
 294         return dra;
 295
 296 }
 297
 298
 299 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 300                 long dimm_mask, uint32_t drc)
 301 {
 302         int value;
 303         int reg;
 304         uint32_t drt;
 305         int cnt;
 306         int first_dimm;
 307         int cas_latency=0;
 308         int latency;
 309         uint32_t index = 0;
 310         uint32_t index2 = 0;
 311         static const unsigned char cycle_time[3] = {0x75,0x60,0x50};
 312         static const int latency_indicies[] = { 26, 23, 9 };
 313
 314         /* 0x78 DRT */
 315         drt = pci_read_config32(ctrl->f0, DRT);
 316         drt &= 3;  /* save bits 1:0 */
 317
 318         for(first_dimm = 0; first_dimm < 4; first_dimm++) {
 319                 if (dimm_mask & (1 << first_dimm))
 320                         break;
 321         }
 322
 323         /* get dimm type */
 324         value = spd_read_byte(ctrl->channel0[first_dimm], 2);
 325         if(value == 8) {
 326                 drt |= (3<<5); /* back to bark write turn around & cycle add */
 327         }
 328
 329         drt |= (3<<18);  /* Trasmax */
 330
 331         for(cnt=0; cnt < 4; cnt++) {
 332                 if (!(dimm_mask & (1 << cnt))) {
 333                         continue;
 334                 }
 335                 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
 336                 /* Compute the lowest cas latency supported */
 337                 latency = log2(reg) -2;
 338
 339                 /* Loop through and find a fast clock with a low latency */
 340                 for(index = 0; index < 3; index++, latency++) {
 341                         if ((latency < 2) || (latency > 4) ||
 342                                 (!(reg & (1 << latency)))) {
 343                                 continue;
 344                         }
 345                         value = spd_read_byte(ctrl->channel0[cnt],
 346                                         latency_indicies[index]);
 347
 348                         if(value <= cycle_time[drc&3]) {
 349                                 if( latency > cas_latency) {
 350                                         cas_latency = latency;
 351                                 }
 352                                 break;
 353                         }
 354                 }
 355         }
 356         index = (cas_latency-2);
 357         if((index)==0) cas_latency = 20;
 358         else if((index)==1) cas_latency = 25;
 359         else cas_latency = 30;
 360
 361         for(cnt=0;cnt<4;cnt++) {
 362                 if (!(dimm_mask & (1 << cnt))) {
 363                         continue;
 364                 }
 365                 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
 366                 if(((index>>8)&0x0ff)<reg) {
 367                         index &= ~(0x0ff << 8);
 368                         index |= (reg << 8);
 369                 }
 370                 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
 371                 if(((index>>16)&0x0ff)<reg) {
 372                         index &= ~(0x0ff << 16);
 373                         index |= (reg<<16);
 374                 }
 375                 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
 376                 if(((index2>>0)&0x0ff)<reg) {
 377                         index2 &= ~(0x0ff << 0);
 378                         index2 |= (reg<<0);
 379                 }
 380                 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
 381                 if(((index2>>8)&0x0ff)<reg) {
 382                         index2 &= ~(0x0ff << 8);
 383                         index2 |= (reg<<8);
 384                 }
 385                 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
 386                 if(((index2>>16)&0x0ff)<reg) {
 387                         index2 &= ~(0x0ff << 16);
 388                         index2 |= (reg<<16);
 389                 }
 390         }
 391
 392         /* get dimm speed */
 393         value = cycle_time[drc&3];
 394         if(value <= 0x50) {  /* 200 MHz */
 395                 if((index&7) > 2) {
 396                         drt |= (2<<2);  /* CAS latency 4 */
 397                         cas_latency = 40;
 398                 } else {
 399                         drt |= (1<<2);  /* CAS latency 3 */
 400                         cas_latency = 30;
 401                 }
 402                 if((index&0x0ff00)<=0x03c00) {
 403                         drt |= (1<<8);  /* Trp RAS Precharg */
 404                 } else {
 405                         drt |= (2<<8);  /* Trp RAS Precharg */
 406                 }
 407
 408                 /* Trcd RAS to CAS delay */
 409                 if((index2&0x0ff)<=0x03c) {
 410                         drt |= (0<<10);
 411                 } else {
 412                         drt |= (1<<10);
 413                 }
 414
 415                 /* Tdal Write auto precharge recovery delay */
 416                 drt |= (1<<12);
 417
 418                 /* Trc TRS min */
 419                 if((index2&0x0ff00)<=0x03700)
 420                         drt |= (0<<14);
 421                 else if((index2&0xff00)<=0x03c00)
 422                         drt |= (1<<14);
 423                 else
 424                         drt |= (2<<14); /* spd 41 */
 425
 426                 drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
 427
 428                 /* Trrd Row Delay */
 429                 if((index&0x0ff0000)<=0x0140000) {
 430                         drt |= (0<<20);
 431                 } else if((index&0x0ff0000)<=0x0280000) {
 432                         drt |= (1<<20);
 433                 } else if((index&0x0ff0000)<=0x03c0000) {
 434                         drt |= (2<<20);
 435                 } else {
 436                         drt |= (3<<20);
 437                 }
 438
 439                 /* Trfc Auto refresh cycle time */
 440                 if((index2&0x0ff0000)<=0x04b0000) {
 441                         drt |= (0<<22);
 442                 } else if((index2&0x0ff0000)<=0x0690000) {
 443                         drt |= (1<<22);
 444                 } else {
 445                         drt |= (2<<22);
 446                 }
 447                 /* Docs say use 55 for all 200Mhz */
 448                 drt |= (0x055<<24);
 449         }
 450         else if(value <= 0x60) { /* 167 Mhz */
 451                 /* according to new documentation CAS latency is 00
 452                  * for bits 3:2 for all 167 Mhz
 453                 drt |= ((index&3)<<2); */  /* set CAS latency */
 454                 if((index&0x0ff00)<=0x03000) {
 455                         drt |= (1<<8);  /* Trp RAS Precharg */
 456                 } else {
 457                         drt |= (2<<8);  /* Trp RAS Precharg */
 458                 }
 459
 460                 /* Trcd RAS to CAS delay */
 461                 if((index2&0x0ff)<=0x030) {
 462                         drt |= (0<<10);
 463                 } else {
 464                         drt |= (1<<10);
 465                 }
 466
 467                 /* Tdal Write auto precharge recovery delay */
 468                 drt |= (2<<12);
 469
 470                 /* Trc TRS min */
 471                 drt |= (2<<14); /* spd 41, but only one choice */
 472
 473                 drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
 474
 475                 /* Trrd Row Delay */
 476                 if((index&0x0ff0000)<=0x0180000) {
 477                         drt |= (0<<20);
 478                 } else if((index&0x0ff0000)<=0x0300000) {
 479                         drt |= (1<<20);
 480                 } else {
 481                         drt |= (2<<20);
 482                 }
 483
 484                 /* Trfc Auto refresh cycle time */
 485                 if((index2&0x0ff0000)<=0x0480000) {
 486                         drt |= (0<<22);
 487                 } else if((index2&0x0ff0000)<=0x0780000) {
 488                         drt |= (2<<22);
 489                 } else {
 490                         drt |= (2<<22);
 491                 }
 492                 /* Docs state to use 99 for all 167 Mhz */
 493                 drt |= (0x099<<24);
 494         }
 495         else if(value <= 0x75) { /* 133 Mhz */
 496                 drt |= ((index&3)<<2);  /* set CAS latency */
 497                 if((index&0x0ff00)<=0x03c00) {
 498                         drt |= (1<<8);  /* Trp RAS Precharg */
 499                 } else {
 500                         drt |= (2<<8);  /* Trp RAS Precharg */
 501                 }
 502
 503                 /* Trcd RAS to CAS delay */
 504                 if((index2&0x0ff)<=0x03c) {
 505                         drt |= (0<<10);
 506                 } else {
 507                         drt |= (1<<10);
 508                 }
 509
 510                 /* Tdal Write auto precharge recovery delay */
 511                 drt |= (1<<12);
 512
 513                 /* Trc TRS min */
 514                 drt |= (2<<14); /* spd 41, but only one choice */
 515
 516                 drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
 517
 518                 /* Trrd Row Delay */
 519                 if((index&0x0ff0000)<=0x01e0000) {
 520                         drt |= (0<<20);
 521                 } else if((index&0x0ff0000)<=0x03c0000) {
 522                         drt |= (1<<20);
 523                 } else {
 524                         drt |= (2<<20);
 525                 }
 526
 527                 /* Trfc Auto refresh cycle time */
 528                 if((index2&0x0ff0000)<=0x04b0000) {
 529                         drt |= (0<<22);
 530                 } else if((index2&0x0ff0000)<=0x0780000) {
 531                         drt |= (2<<22);
 532                 } else {
 533                         drt |= (2<<22);
 534                 }
 535
 536                 /* Based on CAS latency */
 537                 if(index&7)
 538                         drt |= (0x099<<24);
 539                 else
 540                         drt |= (0x055<<24);
 541
 542         }
 543         else {
 544                 die("Invalid SPD 9 bus speed.\n");
 545         }
 546
 547         /* 0x78 DRT */
 548         pci_write_config32(ctrl->f0, DRT, drt);
 549
 550         return(cas_latency);
 551 }
 552
 553 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 554                 long dimm_mask)
 555 {
 556         int value;
 557         int reg;
 558         int drc;
 559         int cnt;
 560         msr_t msr;
 561         unsigned char dram_type = 0xff;
 562         unsigned char ecc = 0xff;
 563         unsigned char rate = 62;
 564         static const unsigned char spd_rates[6] = {15,3,7,7,62,62};
 565         static const unsigned char drc_rates[5] = {0,15,7,62,3};
 566         static const unsigned char fsb_conversion[4] = {3,1,3,2};
 567
 568         /* 0x7c DRC */
 569         drc = pci_read_config32(ctrl->f0, DRC);
 570         for(cnt=0; cnt < 4; cnt++) {
 571                 if (!(dimm_mask & (1 << cnt))) {
 572                         continue;
 573                 }
 574                 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
 575                 reg = spd_read_byte(ctrl->channel0[cnt], 2); /* Type */
 576                 if (value == 2) {    /* RAM is ECC capable */
 577                         if (reg == 8) {
 578                                 if ( ecc == 0xff ) {
 579                                         ecc = 2;
 580                                 }
 581                                 else if (ecc == 1) {
 582                                         die("ERROR - Mixed DDR & DDR2 RAM\n");
 583                                 }
 584                         }
 585                         else if ( reg == 7 ) {
 586                                 if ( ecc == 0xff) {
 587                                         ecc = 1;
 588                                 }
 589                                 else if ( ecc > 1 ) {
 590                                         die("ERROR - Mixed DDR & DDR2 RAM\n");
 591                                 }
 592                         }
 593                         else {
 594                                 die("ERROR - RAM not DDR\n");
 595                         }
 596                 }
 597                 else {
 598                         die("ERROR - Non ECC memory dimm\n");
 599                 }
 600
 601                 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
 602                 value &= 0x0f;    /* clip self refresh bit */
 603                 if (value > 5) goto hw_err;
 604                 if (rate > spd_rates[value])
 605                         rate = spd_rates[value];
 606
 607                 value = spd_read_byte(ctrl->channel0[cnt], 9);  /* cycle time */
 608                 if (value > 0x75) goto hw_err;
 609                 if (value <= 0x50) {
 610                         if (dram_type >= 2) {
 611                                 if (reg == 8) { /*speed is good, is this ddr2?*/
 612                                         dram_type = 2;
 613                                 } else { /* not ddr2 so use ddr333 */
 614                                         dram_type = 1;
 615                                 }
 616                         }
 617                 }
 618                 else if (value <= 0x60) {
 619                         if (dram_type >= 1)  dram_type = 1;
 620                 }
 621                 else dram_type = 0; /* ddr266 */
 622
 623         }
 624         ecc = 2;
 625 #if CONFIG_HAVE_OPTION_TABLE
 626         if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
 627                 ecc = 0;  /* ECC off in CMOS so disable it */
 628                 print_debug("ECC off\n");
 629         } else
 630 #endif
 631         {
 632                 print_debug("ECC on\n");
 633         }
 634         drc &= ~(3 << 20); /* clear the ecc bits */
 635         drc |= (ecc << 20);  /* or in the calculated ecc bits */
 636         for ( cnt = 1; cnt < 5; cnt++)
 637                 if (drc_rates[cnt] == rate)
 638                         break;
 639         if (cnt < 5) {
 640                 drc &= ~(7 << 8);  /* clear the rate bits */
 641                 drc |= (cnt << 8);
 642         }
 643
 644         if (reg == 8) { /* independant clocks */
 645                 drc |= (1 << 4);
 646         }
 647
 648         drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
 649         drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
 650         /* front side bus */
 651         msr = rdmsr(0x2c);
 652         value = msr.lo >> 16;
 653         value &= 0x03;
 654         drc &= ~(3 << 2); /* set the front side bus */
 655         drc |= (fsb_conversion[value] << 2);
 656         drc &= ~(3 << 0); /* set the dram type */
 657         drc |= (dram_type << 0);
 658
 659         goto out;
 660
 661  val_err:
 662         die("Bad SPD value\n");
 663         /* If an hw_error occurs report that I have no memory */
 664 hw_err:
 665         drc = 0;
 666  out:
 667         return drc;
 668 }
 669
 670 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 671 {
 672         long dimm_mask;
 673
 674         /* Test if we can read the spd and if ram is ddr or ddr2 */
 675         dimm_mask = spd_detect_dimms(ctrl);
 676         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 677                 print_err("No memory for this cpu\n");
 678                 return;
 679         }
 680         return;
 681 }
 682
 683 static void do_delay(void)
 684 {
 685         int i;
 686         unsigned char b;
 687         for(i=0;i<16;i++)
 688                 b=inb(0x80);
 689 }
 690
 691 #define TIMEOUT_LOOPS 300000
 692
 693 #define DCALCSR  0x100
 694 #define DCALADDR 0x104
 695 #define DCALDATA 0x108
 696
 697 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 698 {
 699         unsigned char c1,c2;
 700         unsigned int dimm,i;
 701         unsigned int data32;
 702         unsigned int t4;
 703
 704         /* Set up northbridge values */
 705         /* ODT enable */
 706         pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
 707         /* Figure out which slots are Empty, Single, or Double sided */
 708         for(i=0,t4=0,c2=0;i<8;i+=2) {
 709                 c1 = pci_read_config8(ctrl->f0, DRB+i);
 710                 if(c1 == c2) continue;
 711                 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
 712                 if(c1 == c2)
 713                         t4 |= (1 << (i*4));
 714                 else
 715                         t4 |= (2 << (i*4));
 716         }
 717         for(i=0;i<1;i++) {
 718             if((t4&0x0f) == 1) {
 719                 if( ((t4>>8)&0x0f) == 0 ) {
 720                         data32 = 0x00000010; /* EEES */
 721                         break;
 722                 }
 723                 if ( ((t4>>16)&0x0f) == 0 ) {
 724                         data32 = 0x00003132; /* EESS */
 725                         break;
 726                 }
 727                 if ( ((t4>>24)&0x0f)  == 0 ) {
 728                         data32 = 0x00335566; /* ESSS */
 729                         break;
 730                 }
 731                 data32 = 0x77bbddee; /* SSSS */
 732                 break;
 733             }
 734             if((t4&0x0f) == 2) {
 735                 if( ((t4>>8)&0x0f) == 0 ) {
 736                         data32 = 0x00003132; /* EEED */
 737                         break;
 738                 }
 739                 if ( ((t4>>8)&0x0f) == 2 ) {
 740                         data32 = 0xb373ecdc; /* EEDD */
 741                         break;
 742                 }
 743                 if ( ((t4>>16)&0x0f) == 0 ) {
 744                         data32 = 0x00b3a898; /* EESD */
 745                         break;
 746                 }
 747                 data32 = 0x777becdc; /* ESSD */
 748                 break;
 749             }
 750             die("Error - First dimm slot empty\n");
 751         }
 752
 753         print_debug("ODT Value = ");
 754         print_debug_hex32(data32);
 755         print_debug("\n");
 756
 757         pci_write_config32(ctrl->f0, 0xb0, data32);
 758
 759         for(dimm=0;dimm<8;dimm+=1) {
 760
 761                 write32(BAR+DCALADDR, 0x0b840001);
 762                 write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
 763
 764                 for(i=0;i<1001;i++) {
 765                         data32 = read32(BAR+DCALCSR);
 766                         if(!(data32 & (1<<31)))
 767                                 break;
 768                 }
 769         }
 770 }
 771 static void set_receive_enable(const struct mem_controller *ctrl)
 772 {
 773         unsigned int i;
 774         unsigned int cnt,bit;
 775         uint32_t recena=0;
 776         uint32_t recenb=0;
 777
 778         {
 779         unsigned int dimm;
 780         unsigned int edge;
 781         int32_t data32;
 782         uint32_t data32_dram;
 783         uint32_t dcal_data32_0;
 784         uint32_t dcal_data32_1;
 785         uint32_t dcal_data32_2;
 786         uint32_t dcal_data32_3;
 787         uint32_t work32l;
 788         uint32_t work32h;
 789         uint32_t data32r;
 790         int32_t recen;
 791         for(dimm=0;dimm<8;dimm+=1) {
 792
 793                 if(!(dimm&1)) {
 794                         write32(BAR+DCALDATA+(17*4), 0x04020000);
 795                         write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
 796
 797                         for(i=0;i<1001;i++) {
 798                                 data32 = read32(BAR+DCALCSR);
 799                                 if(!(data32 & (1<<31)))
 800                                         break;
 801                         }
 802                         if(i>=1000)
 803                                 continue;
 804
 805                         dcal_data32_0 = read32(BAR+DCALDATA + 0);
 806                         dcal_data32_1 = read32(BAR+DCALDATA + 4);
 807                         dcal_data32_2 = read32(BAR+DCALDATA + 8);
 808                         dcal_data32_3 = read32(BAR+DCALDATA + 12);
 809                 }
 810                 else {
 811                         dcal_data32_0 = read32(BAR+DCALDATA + 16);
 812                         dcal_data32_1 = read32(BAR+DCALDATA + 20);
 813                         dcal_data32_2 = read32(BAR+DCALDATA + 24);
 814                         dcal_data32_3 = read32(BAR+DCALDATA + 28);
 815                 }
 816
 817                 /* check if bank is installed */
 818                 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
 819                         continue;
 820                 /* Calculate the timing value */
 821                 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
 822                         work32l=dcal_data32_1,work32h=dcal_data32_3;
 823                                 (i<4) && bit; i++) {
 824                         for(;;bit--,cnt--) {
 825                                 if(work32l & (1<<cnt))
 826                                         break;
 827                                 if(!cnt) {
 828                                         work32l = dcal_data32_0;
 829                                         work32h = dcal_data32_2;
 830                                         cnt = 32;
 831                                 }
 832                                 if(!bit) break;
 833                         }
 834                         for(;;bit--,cnt--) {
 835                                 if(!(work32l & (1<<cnt)))
 836                                         break;
 837                                 if(!cnt) {
 838                                         work32l = dcal_data32_0;
 839                                         work32h = dcal_data32_2;
 840                                         cnt = 32;
 841                                 }
 842                                 if(!bit) break;
 843                         }
 844                         if(!bit) {
 845                                 break;
 846                         }
 847                         data32 = ((bit%8) << 1);
 848                         if(work32h & (1<<cnt))
 849                                 data32 += 1;
 850                         if(data32 < 4) {
 851                                 if(!edge) {
 852                                         edge = 1;
 853                                 }
 854                                 else {
 855                                         if(edge != 1) {
 856                                                 data32 = 0x0f;
 857                                         }
 858                                 }
 859                         }
 860                         if(data32 > 12) {
 861                                 if(!edge) {
 862                                         edge = 2;
 863                                 }
 864                                 else {
 865                                         if(edge != 2) {
 866                                                 data32 = 0x00;
 867                                         }
 868                                 }
 869                         }
 870                         data32r += data32;
 871                 }
 872
 873                 work32l = dcal_data32_0;
 874                 work32h = dcal_data32_2;
 875                 recen = data32r;
 876                 recen += 3;
 877                 recen = recen>>2;
 878                 for(cnt=5;cnt<24;) {
 879                         for(;;cnt++)
 880                                 if(!(work32l & (1<<cnt)))
 881                                         break;
 882                         for(;;cnt++) {
 883                                 if(work32l & (1<<cnt))
 884                                         break;
 885                         }
 886                         data32 = (((cnt-1)%8)<<1);
 887                         if(work32h & (1<<(cnt-1))) {
 888                                 data32++;
 889                         }
 890                         /* test for frame edge cross overs */
 891                         if((edge == 1) && (data32 > 12) &&
 892                             (((recen+16)-data32) < 3)) {
 893                                 data32 = 0;
 894                                 cnt += 2;
 895                         }
 896                         if((edge == 2) && (data32 < 4) &&
 897                             ((recen - data32) > 12))  {
 898                                 data32 = 0x0f;
 899                                 cnt -= 2;
 900                         }
 901                         if(((recen+3) >= data32) && ((recen-3) <= data32))
 902                                 break;
 903                 }
 904                 cnt--;
 905                 cnt /= 8;
 906                 cnt--;
 907                 if(recen&1)
 908                         recen+=2;
 909                 recen >>= 1;
 910                 recen += (cnt*8);
 911         recen+=2;
 912                 recen <<= (dimm/2) * 8;
 913                 if(!(dimm&1)) {
 914                         recena |= recen;
 915                 }
 916                 else {
 917                         recenb |= recen;
 918                 }
 919         }
 920         }
 921         /* Check for Eratta problem */
 922         for(i=cnt=bit=0;i<4;i++) {
 923                 if (((recena>>(i*8))&0x0f)>7) {
 924                         cnt++; bit++;
 925                 }
 926                 else {
 927                         if((recena>>(i*8))&0x0f) {
 928                                 cnt++;
 929                         }
 930                 }
 931         }
 932         if(bit) {
 933                 cnt-=bit;
 934                 if(cnt>1) {
 935                         for(i=0;i<4;i++) {
 936                                 if(((recena>>(i*8))&0x0f)>7) {
 937                                         recena &= ~(0x0f<<(i*8));
 938                                         recena |= (7<<(i*8));
 939                                 }
 940                         }
 941                 }
 942                 else {
 943                         for(i=0;i<4;i++) {
 944                                 if(((recena>>(i*8))&0x0f)<8) {
 945                                         recena &= ~(0x0f<<(i*8));
 946                                         recena |= (8<<(i*8));
 947                                 }
 948                         }
 949                 }
 950         }
 951         for(i=cnt=bit=0;i<4;i++) {
 952                 if (((recenb>>(i*8))&0x0f)>7) {
 953                         cnt++; bit++;
 954                 }
 955                 else {
 956                         if((recenb>>(i*8))&0x0f) {
 957                                 cnt++;
 958                         }
 959                 }
 960         }
 961         if(bit) {
 962                 cnt-=bit;
 963                 if(cnt>1) {
 964                         for(i=0;i<4;i++) {
 965                                 if(((recenb>>(i*8))&0x0f)>7) {
 966                                         recenb &= ~(0x0f<<(i*8));
 967                                         recenb |= (7<<(i*8));
 968                                 }
 969                         }
 970                 }
 971                 else {
 972                         for(i=0;i<4;i++) {
 973                                 if(((recenb>>(i*8))&0x0f)<8) {
 974                                         recenb &= ~(0x0f<<(i*8));
 975                                         recenb |= (8<<(i*8));
 976                                 }
 977                         }
 978                 }
 979         }
 980
 981 //  recena = 0x0000090a;
 982 //  recenb = 0x0000090a;
 983
 984         print_debug("Receive enable A = ");
 985         print_debug_hex32(recena);
 986         print_debug(",  Receive enable B = ");
 987         print_debug_hex32(recenb);
 988         print_debug("\n");
 989
 990         /* clear out the calibration area */
 991         write32(BAR+DCALDATA+(16*4), 0x00000000);
 992         write32(BAR+DCALDATA+(17*4), 0x00000000);
 993         write32(BAR+DCALDATA+(18*4), 0x00000000);
 994         write32(BAR+DCALDATA+(19*4), 0x00000000);
 995
 996         /* No command */
 997         write32(BAR+DCALCSR, 0x0000000f);
 998
 999         write32(BAR+0x150, recena);
1000         write32(BAR+0x154, recenb);
1001 }
1002
1003
1004 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1005 {
1006         int i;
1007         int cs;
1008         int cnt;
1009         int cas_latency;
1010         long mask;
1011         uint32_t drc;
1012         uint32_t data32;
1013         uint32_t mode_reg;
1014         uint32_t *iptr;
1015         volatile unsigned long *iptrv;
1016         msr_t msr;
1017         uint32_t scratch;
1018         uint8_t byte;
1019         uint16_t data16;
1020         static const struct {
1021                 uint32_t clkgr[4];
1022         } gearing [] = {
1023                 /* FSB 133 DIMM 266 */
1024         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1025                 /* FSB 133 DIMM 333 */
1026         {{ 0x00000000, 0x00000000, 0x00000000, 0x00000000}},
1027                 /* FSB 133 DIMM 400 */
1028         {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
1029                 /* FSB 167 DIMM 266 */
1030         {{ 0x00005432, 0x00001000, 0x00004325, 0x00000000}},
1031                 /* FSB 167 DIMM 333 */
1032         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1033                 /* FSB 167 DIMM 400 */
1034         {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
1035                 /* FSB 200 DIMM 266 */
1036         {{ 0x00000032, 0x00000010, 0x00000120, 0x00000000}},
1037                 /* FSB 200 DIMM 333 */
1038         {{ 0x00065432, 0x00010000, 0x00054326, 0x00000000}},
1039                 /* FSB 200 DIMM 400 */
1040         {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1041         };
1042
1043         static const uint32_t dqs_data[] = {
1044                 0xffffffff, 0xffffffff, 0x000000ff,
1045                 0xffffffff, 0xffffffff, 0x000000ff,
1046                 0xffffffff, 0xffffffff, 0x000000ff,
1047                 0xffffffff, 0xffffffff, 0x000000ff,
1048                 0xffffffff, 0xffffffff, 0x000000ff,
1049                 0xffffffff, 0xffffffff, 0x000000ff,
1050                 0xffffffff, 0xffffffff, 0x000000ff,
1051                 0xffffffff, 0xffffffff, 0x000000ff};
1052
1053         mask = spd_detect_dimms(ctrl);
1054         print_debug("Starting SDRAM Enable\n");
1055
1056         /* 0x80 */
1057 #ifdef DIMM_MAP_LOGICAL
1058         pci_write_config32(ctrl->f0, DRM,
1059                 0x00210000 | DIMM_MAP_LOGICAL);
1060 #else
1061         pci_write_config32(ctrl->f0, DRM, 0x00211248);
1062 #endif
1063         /* set dram type and Front Side Bus freq. */
1064         drc = spd_set_dram_controller_mode(ctrl, mask);
1065         if( drc == 0) {
1066                 die("Error calculating DRC\n");
1067         }
1068         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1069         data32 = data32 & ~(7 << 8);  /* clear refresh rates */
1070         data32 = data32 | (1 << 5);  /* temp turn off of ODT */
1071         /* Set gearing, then dram controller mode */
1072         /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
1073         for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
1074                         cnt<4;cnt++) {
1075                 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
1076         }
1077         /* 0x7c DRC */
1078         pci_write_config32(ctrl->f0, DRC, data32);
1079
1080                 /* turn the clocks on */
1081         /* 0x8c CKDIS */
1082         pci_write_config16(ctrl->f0, CKDIS, 0x0000);
1083
1084                 /* 0x9a DDRCSR Take subsystem out of idle */
1085         data16 = pci_read_config16(ctrl->f0, DDRCSR);
1086         data16 &= ~(7 << 12);
1087         data16 |= (3 << 12);   /* use dual channel lock step */
1088         pci_write_config16(ctrl->f0, DDRCSR, data16);
1089
1090                 /* program row size DRB */
1091         spd_set_ram_size(ctrl, mask);
1092
1093                 /* program page size DRA */
1094         spd_set_row_attributes(ctrl, mask);
1095
1096                 /* program DRT timing values */
1097         cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1098
1099         for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
1100                 print_debug("DIMM ");
1101                 print_debug_hex8(i);
1102                 print_debug("\n");
1103                 /* Apply NOP */
1104                 do_delay();
1105
1106                 write32(BAR + 0x100, (0x03000000 | (i<<20)));
1107
1108                 write32(BAR+0x100, (0x83000000 | (i<<20)));
1109
1110                 data32 = read32(BAR+DCALCSR);
1111                 while(data32 & 0x80000000)
1112                         data32 = read32(BAR+DCALCSR);
1113
1114         }
1115
1116         /* Apply NOP */
1117         do_delay();
1118
1119         for(cs=0;cs<8;cs++) {
1120                 write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
1121                 data32 = read32(BAR+DCALCSR);
1122                 while(data32 & 0x80000000)
1123                         data32 = read32(BAR+DCALCSR);
1124         }
1125
1126         /* Precharg all banks */
1127         do_delay();
1128         for(cs=0;cs<8;cs++) {
1129                 if ((drc & 3) == 2) /* DDR2  */
1130                         write32(BAR+DCALADDR, 0x04000000);
1131                 else   /* DDR1  */
1132                         write32(BAR+DCALADDR, 0x00000000);
1133                 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1134                 data32 = read32(BAR+DCALCSR);
1135                 while(data32 & 0x80000000)
1136                         data32 = read32(BAR+DCALCSR);
1137         }
1138
1139         /* EMRS dll's enabled */
1140         do_delay();
1141         for(cs=0;cs<8;cs++) {
1142                 if ((drc & 3) == 2) /* DDR2  */
1143                         /* fixme hard code AL additive latency */
1144                         write32(BAR+DCALADDR, 0x0b940001);
1145                 else   /* DDR1  */
1146                         write32(BAR+DCALADDR, 0x00000001);
1147                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1148                 data32 = read32(BAR+DCALCSR);
1149                 while(data32 & 0x80000000)
1150                         data32 = read32(BAR+DCALCSR);
1151         }
1152         /* MRS reset dll's */
1153         do_delay();
1154         if ((drc & 3) == 2) {  /* DDR2  */
1155                 if(cas_latency == 30)
1156                         mode_reg = 0x053a0000;
1157                 else
1158                         mode_reg = 0x054a0000;
1159         }
1160         else {  /* DDR1  */
1161                 if(cas_latency == 20)
1162                         mode_reg = 0x012a0000;
1163                 else  /*  CAS Latency 2.5 */
1164                         mode_reg = 0x016a0000;
1165         }
1166         for(cs=0;cs<8;cs++) {
1167                 write32(BAR+DCALADDR, mode_reg);
1168                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1169                 data32 = read32(BAR+DCALCSR);
1170                 while(data32 & 0x80000000)
1171                         data32 = read32(BAR+DCALCSR);
1172         }
1173
1174         /* Precharg all banks */
1175         do_delay();
1176         do_delay();
1177         do_delay();
1178         for(cs=0;cs<8;cs++) {
1179                 if ((drc & 3) == 2) /* DDR2  */
1180                         write32(BAR+DCALADDR, 0x04000000);
1181                 else   /* DDR1  */
1182                         write32(BAR+DCALADDR, 0x00000000);
1183                 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1184                 data32 = read32(BAR+DCALCSR);
1185                 while(data32 & 0x80000000)
1186                         data32 = read32(BAR+DCALCSR);
1187         }
1188
1189         /* Do 2 refreshes */
1190         do_delay();
1191         for(cs=0;cs<8;cs++) {
1192                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1193                 data32 = read32(BAR+DCALCSR);
1194                 while(data32 & 0x80000000)
1195                         data32 = read32(BAR+DCALCSR);
1196         }
1197         do_delay();
1198         for(cs=0;cs<8;cs++) {
1199                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1200                 data32 = read32(BAR+DCALCSR);
1201                 while(data32 & 0x80000000)
1202                         data32 = read32(BAR+DCALCSR);
1203         }
1204         do_delay();
1205         /* for good luck do 6 more */
1206         for(cs=0;cs<8;cs++) {
1207                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1208         }
1209         do_delay();
1210         for(cs=0;cs<8;cs++) {
1211                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1212         }
1213         do_delay();
1214         for(cs=0;cs<8;cs++) {
1215                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1216         }
1217         do_delay();
1218         for(cs=0;cs<8;cs++) {
1219                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1220         }
1221         do_delay();
1222         for(cs=0;cs<8;cs++) {
1223                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1224         }
1225         do_delay();
1226         for(cs=0;cs<8;cs++) {
1227                 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1228         }
1229         do_delay();
1230         /* MRS reset dll's normal */
1231         do_delay();
1232         for(cs=0;cs<8;cs++) {
1233                 write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
1234                 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1235                 data32 = read32(BAR+DCALCSR);
1236                 while(data32 & 0x80000000)
1237                         data32 = read32(BAR+DCALCSR);
1238         }
1239
1240         /* Do only if DDR2  EMRS dll's enabled */
1241         if ((drc & 3) == 2) { /* DDR2  */
1242                 do_delay();
1243                 for(cs=0;cs<8;cs++) {
1244                         write32(BAR+DCALADDR, (0x0b940001));
1245                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1246                         data32 = read32(BAR+DCALCSR);
1247                         while(data32 & 0x80000000)
1248                                 data32 = read32(BAR+DCALCSR);
1249                 }
1250         }
1251
1252         do_delay();
1253         /* No command */
1254         write32(BAR+DCALCSR, 0x0000000f);
1255
1256         /* DDR1 This is test code to copy some codes in the factory setup */
1257
1258         write32(BAR, 0x00100000);
1259
1260         if ((drc & 3) == 2) { /* DDR2  */
1261         /* enable on dimm termination */
1262                 set_on_dimm_termination_enable(ctrl);
1263         }
1264
1265         /* receive enable calibration */
1266         set_receive_enable(ctrl);
1267
1268         /* DQS */
1269         pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1270         for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
1271                 write32(cnt, dqs_data[i]);
1272         }
1273         pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1274
1275         /* Enable refresh */
1276         /* 0x7c DRC */
1277         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1278         pci_write_config32(ctrl->f0, DRC, data32);
1279         write32(BAR+DCALCSR, 0x0008000f);
1280
1281         /* clear memory and init ECC */
1282         print_debug("Clearing memory\n");
1283         for(i=0;i<64;i+=4) {
1284                 write32(BAR+DCALDATA+i, 0x00000000);
1285         }
1286
1287         for(cs=0;cs<8;cs++) {
1288                 write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
1289                 data32 = read32(BAR+DCALCSR);
1290                 while(data32 & 0x80000000)
1291                         data32 = read32(BAR+DCALCSR);
1292         }
1293
1294         /* Bring memory subsystem on line */
1295         data32 = pci_read_config32(ctrl->f0, 0x98);
1296         data32 |= (1 << 31);
1297         pci_write_config32(ctrl->f0, 0x98, data32);
1298         /* wait for completion */
1299         print_debug("Waiting for mem complete\n");
1300         while(1) {
1301                 data32 = pci_read_config32(ctrl->f0, 0x98);
1302                 if( (data32 & (1<<31)) == 0)
1303                         break;
1304         }
1305         print_debug("Done\n");
1306
1307         /* Set initialization complete */
1308         /* 0x7c DRC */
1309         drc |= (1 << 29);
1310         data32 = drc & ~(3 << 20);  /* clear ECC mode */
1311         pci_write_config32(ctrl->f0, DRC, data32);
1312
1313         /* Set the ecc mode */
1314         pci_write_config32(ctrl->f0, DRC, drc);
1315
1316         /* Enable memory scrubbing */
1317         /* 0x52 MCHSCRB */
1318         data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1319         data16 &= ~0x0f;
1320         data16 |= ((2 << 2) | (2 << 0));
1321         pci_write_config16(ctrl->f0, MCHSCRB, data16);
1322
1323         /* The memory is now setup, use it */
1324         cache_lbmem(MTRR_TYPE_WRBACK);
1325 }