src/northbridge/intel/e7525/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include <cpu/cpu.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14 #include "e7525.h"
  15
  16
  17 static unsigned int max_bus;
  18
  19 static void ram_resource(device_t dev, unsigned long index,
  20         unsigned long basek, unsigned long sizek)
  21 {
  22         struct resource *resource;
  23
  24         resource = new_resource(dev, index);
  25         resource->base  = ((resource_t)basek) << 10;
  26         resource->size  = ((resource_t)sizek) << 10;
  27         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  28                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  29 }
  30
  31
  32 static void pci_domain_read_resources(device_t dev)
  33 {
  34         struct resource *resource;
  35
  36         /* Initialize the system wide io space constraints */
  37         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  38         resource->base  = 0;
  39         resource->size  = 0;
  40         resource->align = 0;
  41         resource->gran  = 0;
  42         resource->limit = 0xffffUL;
  43         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  44
  45         /* Initialize the system wide memory resources constraints */
  46         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  47         resource->base  = 0;
  48         resource->size  = 0;
  49         resource->align = 0;
  50         resource->gran  = 0;
  51         resource->limit = 0xffffffffUL;
  52         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  53 }
  54
  55 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  56 {
  57         struct resource **best_p = gp;
  58         struct resource *best;
  59         best = *best_p;
  60         if (!best || (best->base > new->base)) {
  61                 best = new;
  62         }
  63         *best_p = best;
  64 }
  65
  66 static uint32_t find_pci_tolm(struct bus *bus)
  67 {
  68         struct resource *min;
  69         uint32_t tolm;
  70         min = 0;
  71         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  72         tolm = 0xffffffffUL;
  73         if (min && tolm > min->base) {
  74                 tolm = min->base;
  75         }
  76         return tolm;
  77 }
  78
  79
  80 static void pci_domain_set_resources(device_t dev)
  81 {
  82         device_t mc_dev;
  83         uint32_t pci_tolm;
  84
  85         pci_tolm = find_pci_tolm(&dev->link[0]);
  86
  87 #if 1
  88         printk_debug("PCI mem marker = %x\n", pci_tolm);
  89 #endif
  90         /* FIXME Me temporary hack */
  91         if(pci_tolm > 0xe0000000)
  92                 pci_tolm = 0xe0000000;
  93         /* Ensure pci_tolm is 128M aligned */
  94         pci_tolm &= 0xf8000000;
  95         mc_dev = dev->link[0].children;
  96         if (mc_dev) {
  97                 /* Figure out which areas are/should be occupied by RAM.
  98                  * This is all computed in kilobytes and converted to/from
  99                  * the memory controller right at the edges.
 100                  * Having different variables in different units is
 101                  * too confusing to get right.  Kilobytes are good up to
 102                  * 4 Terabytes of RAM...
 103                  */
 104                 uint16_t tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
 105                 unsigned long tomk, tolmk;
 106                 unsigned long remapbasek, remaplimitk, remapoffsetk;
 107
 108                 /* Get the Top of Memory address, units are 128M */
 109                 tomk = ((unsigned long)pci_read_config16(mc_dev, TOM)) << 17;
 110                 /* Compute the Top of Low Memory */
 111                 tolmk = (pci_tolm  & 0xf8000000) >> 10;
 112
 113                 if (tolmk >= tomk) {
 114                         /* The PCI hole does not overlap memory
 115                          * we won't use the remap window.
 116                          */
 117                         tolmk = tomk;
 118                         remapbasek   = 0x3ff << 16;
 119                         remaplimitk  = 0 << 16;
 120                         remapoffsetk = 0 << 16;
 121                 }
 122                 else {
 123                         /* The PCI memory hole overlaps memory
 124                          * setup the remap window.
 125                          */
 126                         /* Find the bottom of the remap window
 127                          * is it above 4G?
 128                          */
 129                         remapbasek = 4*1024*1024;
 130                         if (tomk > remapbasek) {
 131                                 remapbasek = tomk;
 132                         }
 133                         /* Find the limit of the remap window */
 134                         remaplimitk  = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 135                         /* Find the offset of the remap window from tolm */
 136                         remapoffsetk = remapbasek - tolmk;
 137                 }
 138                 /* Write the ram configruation registers,
 139                  * preserving the reserved bits.
 140                  */
 141                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 142                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 143                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 144
 145                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 146                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 147                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 148
 149                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 150                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 151                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 152
 153                 remapoffset_r = pci_read_config16(mc_dev, 0xca);
 154                 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
 155                 pci_write_config16(mc_dev, 0xca, remapoffset_r);
 156
 157                 /* Report the memory regions */
 158                 ram_resource(dev, 3,   0, 640);
 159                 ram_resource(dev, 4, 768, tolmk - 768);
 160                 if (tomk > 4*1024*1024) {
 161                         ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
 162                 }
 163                 if (remaplimitk >= remapbasek) {
 164                         ram_resource(dev, 6, remapbasek,
 165                                 (remaplimitk + 64*1024) - remapbasek);
 166                 }
 167         }
 168         assign_resources(&dev->link[0]);
 169 }
 170
 171 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 172 {
 173         max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
 174         if (max > max_bus) {
 175                 max_bus = max;
 176         }
 177         return max;
 178 }
 179
 180 static struct device_operations pci_domain_ops = {
 181         .read_resources   = pci_domain_read_resources,
 182         .set_resources    = pci_domain_set_resources,
 183         .enable_resources = enable_childrens_resources,
 184         .init             = 0,
 185         .scan_bus         = pci_domain_scan_bus,
 186         .ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 187 };
 188
 189 static void mc_read_resources(device_t dev)
 190 {
 191         struct resource *resource;
 192
 193         pci_dev_read_resources(dev);
 194
 195         resource = new_resource(dev, 0xcf);
 196         resource->base = 0xe0000000;
 197         resource->size = max_bus * 4096*256;
 198         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
 199 }
 200
 201 static void mc_set_resources(device_t dev)
 202 {
 203         struct resource *resource, *last;
 204
 205         last = &dev->resource[dev->resources];
 206         resource = find_resource(dev, 0xcf);
 207         if (resource) {
 208                 report_resource_stored(dev, resource, "<mmconfig>");
 209         }
 210         pci_dev_set_resources(dev);
 211 }
 212
 213 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 214 {
 215         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 216                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 217 }
 218
 219 static struct pci_operations intel_pci_ops = {
 220         .set_subsystem = intel_set_subsystem,
 221 };
 222
 223 static struct device_operations mc_ops = {
 224         .read_resources   = mc_read_resources,
 225         .set_resources    = mc_set_resources,
 226         .enable_resources = pci_dev_enable_resources,
 227         .init             = 0,
 228         .scan_bus         = 0,
 229         .ops_pci          = &intel_pci_ops,
 230 };
 231
 232 static const struct pci_driver mc_driver __pci_driver = {
 233         .ops = &mc_ops,
 234         .vendor = PCI_VENDOR_ID_INTEL,
 235         .device = 0x359e,
 236 };
 237
 238 static void cpu_bus_init(device_t dev)
 239 {
 240         initialize_cpus(&dev->link[0]);
 241 }
 242
 243 static void cpu_bus_noop(device_t dev)
 244 {
 245 }
 246
 247 static struct device_operations cpu_bus_ops = {
 248         .read_resources   = cpu_bus_noop,
 249         .set_resources    = cpu_bus_noop,
 250         .enable_resources = cpu_bus_noop,
 251         .init             = cpu_bus_init,
 252         .scan_bus         = 0,
 253 };
 254
 255
 256 static void enable_dev(device_t dev)
 257 {
 258         /* Set the operations if it is a special bus type */
 259         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 260                 dev->ops = &pci_domain_ops;
 261         }
 262         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 263                 dev->ops = &cpu_bus_ops;
 264         }
 265 }
 266
 267 struct chip_operations northbridge_intel_e7525_ops = {
 268         CHIP_NAME("Intel E7525 Northbridge")
 269         .enable_dev = enable_dev,
 270 };