1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/hypertransport.h>
13 #include "northbridge.h"
17 static unsigned int max_bus;
19 static void ram_resource(device_t dev, unsigned long index,
20 unsigned long basek, unsigned long sizek)
22 struct resource *resource;
24 resource = new_resource(dev, index);
25 resource->base = ((resource_t)basek) << 10;
26 resource->size = ((resource_t)sizek) << 10;
27 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
28 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
31 static void tolm_test(void *gp, struct device *dev, struct resource *new)
33 struct resource **best_p = gp;
34 struct resource *best;
36 if (!best || (best->base > new->base)) {
42 static uint32_t find_pci_tolm(struct bus *bus)
47 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
49 if (min && tolm > min->base) {
55 #if CONFIG_WRITE_HIGH_TABLES==1
56 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
57 extern uint64_t high_tables_base, high_tables_size;
60 static void pci_domain_set_resources(device_t dev)
65 pci_tolm = find_pci_tolm(&dev->link[0]);
68 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
70 /* FIXME Me temporary hack */
71 if(pci_tolm > 0xe0000000)
72 pci_tolm = 0xe0000000;
73 /* Ensure pci_tolm is 128M aligned */
74 pci_tolm &= 0xf8000000;
75 mc_dev = dev->link[0].children;
77 /* Figure out which areas are/should be occupied by RAM.
78 * This is all computed in kilobytes and converted to/from
79 * the memory controller right at the edges.
80 * Having different variables in different units is
81 * too confusing to get right. Kilobytes are good up to
82 * 4 Terabytes of RAM...
84 uint16_t tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
85 unsigned long tomk, tolmk;
86 unsigned long remapbasek, remaplimitk, remapoffsetk;
88 /* Get the Top of Memory address, units are 128M */
89 tomk = ((unsigned long)pci_read_config16(mc_dev, TOM)) << 17;
90 /* Compute the Top of Low Memory */
91 tolmk = (pci_tolm & 0xf8000000) >> 10;
94 /* The PCI hole does not overlap memory
95 * we won't use the remap window.
98 remapbasek = 0x3ff << 16;
99 remaplimitk = 0 << 16;
100 remapoffsetk = 0 << 16;
103 /* The PCI memory hole overlaps memory
104 * setup the remap window.
106 /* Find the bottom of the remap window
109 remapbasek = 4*1024*1024;
110 if (tomk > remapbasek) {
113 /* Find the limit of the remap window */
114 remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
115 /* Find the offset of the remap window from tolm */
116 remapoffsetk = remapbasek - tolmk;
118 /* Write the ram configruation registers,
119 * preserving the reserved bits.
121 tolm_r = pci_read_config16(mc_dev, 0xc4);
122 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
123 pci_write_config16(mc_dev, 0xc4, tolm_r);
125 remapbase_r = pci_read_config16(mc_dev, 0xc6);
126 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
127 pci_write_config16(mc_dev, 0xc6, remapbase_r);
129 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
130 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
131 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
133 remapoffset_r = pci_read_config16(mc_dev, 0xca);
134 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
135 pci_write_config16(mc_dev, 0xca, remapoffset_r);
137 /* Report the memory regions */
138 ram_resource(dev, 3, 0, 640);
139 ram_resource(dev, 4, 768, (tolmk - 768));
140 if (tomk > 4*1024*1024) {
141 ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
143 if (remaplimitk >= remapbasek) {
144 ram_resource(dev, 6, remapbasek,
145 (remaplimitk + 64*1024) - remapbasek);
148 #if CONFIG_WRITE_HIGH_TABLES==1
149 /* Leave some space for ACPI, PIRQ and MP tables */
150 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
151 high_tables_size = HIGH_TABLES_SIZE * 1024;
154 assign_resources(&dev->link[0]);
157 static u32 e7525_domain_scan_bus(device_t dev, u32 max)
159 max_bus = pci_domain_scan_bus(dev, max);
163 static struct device_operations pci_domain_ops = {
164 .read_resources = pci_domain_read_resources,
165 .set_resources = pci_domain_set_resources,
166 .enable_resources = enable_childrens_resources,
168 .scan_bus = e7525_domain_scan_bus,
169 .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
172 static void mc_read_resources(device_t dev)
174 struct resource *resource;
176 pci_dev_read_resources(dev);
178 resource = new_resource(dev, 0xcf);
179 resource->base = 0xe0000000;
180 resource->size = max_bus * 4096*256;
181 resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
184 static void mc_set_resources(device_t dev)
186 struct resource *resource, *last;
188 last = &dev->resource[dev->resources];
189 resource = find_resource(dev, 0xcf);
191 report_resource_stored(dev, resource, "<mmconfig>");
193 pci_dev_set_resources(dev);
196 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
198 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
199 ((device & 0xffff) << 16) | (vendor & 0xffff));
202 static struct pci_operations intel_pci_ops = {
203 .set_subsystem = intel_set_subsystem,
206 static struct device_operations mc_ops = {
207 .read_resources = mc_read_resources,
208 .set_resources = mc_set_resources,
209 .enable_resources = pci_dev_enable_resources,
212 .ops_pci = &intel_pci_ops,
215 static const struct pci_driver mc_driver __pci_driver = {
217 .vendor = PCI_VENDOR_ID_INTEL,
221 static void cpu_bus_init(device_t dev)
223 initialize_cpus(&dev->link[0]);
226 static void cpu_bus_noop(device_t dev)
230 static struct device_operations cpu_bus_ops = {
231 .read_resources = cpu_bus_noop,
232 .set_resources = cpu_bus_noop,
233 .enable_resources = cpu_bus_noop,
234 .init = cpu_bus_init,
239 static void enable_dev(device_t dev)
241 /* Set the operations if it is a special bus type */
242 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
243 dev->ops = &pci_domain_ops;
245 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
246 dev->ops = &cpu_bus_ops;
250 struct chip_operations northbridge_intel_e7525_ops = {
251 CHIP_NAME("Intel E7525 Northbridge")
252 .enable_dev = enable_dev,