1 #include <cpu/x86/mem.h>
2 #include <cpu/x86/mtrr.h>
3 #include <cpu/x86/cache.h>
9 static void sdram_set_registers(const struct mem_controller *ctrl)
11 static const unsigned int register_values[] = {
13 /* CKDIS 0x8c disable clocks */
14 PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
16 /* 0x9c Device present and extended RAM control
17 * DEVPRES is very touchy, hard code the initialization
18 * of PCI-E ports here.
20 PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
22 /* 0xc8 Remap RAM base and limit off */
23 PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
26 PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
27 PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
30 PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
33 PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
34 PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
37 PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
40 PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,
45 max = sizeof(register_values)/sizeof(register_values[0]);
46 for(i = 0; i < max; i += 3) {
50 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
51 where = register_values[i] & 0xff;
52 reg = pci_read_config32(dev, where);
53 reg &= register_values[i+1];
54 reg |= register_values[i+2];
55 pci_write_config32(dev, where, reg);
57 print_spew("done.\r\n");
67 static struct dimm_size spd_get_dimm_size(unsigned device)
69 /* Calculate the log base 2 size of a DIMM in bits */
77 value = spd_read_byte(device, 2); /* type */
78 if (value < 0) goto hw_err;
79 if (value == 8) ddr2 = 1;
81 /* Note it might be easier to use byte 31 here, it has the DIMM size as
82 * a multiple of 4MB. The way we do it now we can size both
83 * sides of an assymetric dimm.
85 value = spd_read_byte(device, 3); /* rows */
86 if (value < 0) goto hw_err;
87 if ((value & 0xf) == 0) goto val_err;
88 sz.side1 += value & 0xf;
90 value = spd_read_byte(device, 4); /* columns */
91 if (value < 0) goto hw_err;
92 if ((value & 0xf) == 0) goto val_err;
93 sz.side1 += value & 0xf;
95 value = spd_read_byte(device, 17); /* banks */
96 if (value < 0) goto hw_err;
97 if ((value & 0xff) == 0) goto val_err;
98 sz.side1 += log2(value & 0xff);
100 /* Get the module data width and convert it to a power of two */
101 value = spd_read_byte(device, 7); /* (high byte) */
102 if (value < 0) goto hw_err;
106 low = spd_read_byte(device, 6); /* (low byte) */
107 if (low < 0) goto hw_err;
108 value = value | (low & 0xff);
109 if ((value != 72) && (value != 64)) goto val_err;
110 sz.side1 += log2(value);
113 value = spd_read_byte(device, 5); /* number of physical banks */
115 if (value < 0) goto hw_err;
118 if (value == 1) goto out;
119 if (value != 2) goto val_err;
121 /* Start with the symmetrical case */
124 value = spd_read_byte(device, 3); /* rows */
125 if (value < 0) goto hw_err;
126 if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */
127 sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
128 sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
130 value = spd_read_byte(device, 4); /* columns */
131 if (value < 0) goto hw_err;
132 if ((value & 0xff) == 0) goto val_err;
133 sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
134 sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
138 die("Bad SPD value\r\n");
139 /* If an hw_error occurs report that I have no memory */
148 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
153 for(i = cum = 0; i < DIMM_SOCKETS; i++) {
155 if (dimm_mask & (1 << i)) {
156 sz = spd_get_dimm_size(ctrl->channel0[i]);
158 return -1; /* Report SPD error */
160 /* convert bits to multiples of 64MB */
162 cum += (1 << sz.side1);
164 pci_write_config8(ctrl->f0, DRB + (i*2), cum);
167 cum += (1 << sz.side2);
169 pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
172 pci_write_config8(ctrl->f0, DRB + (i*2), cum);
173 pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
176 /* set TOM top of memory 0xcc */
177 pci_write_config16(ctrl->f0, TOM, cum);
178 /* set TOLM top of low memory */
184 pci_write_config16(ctrl->f0, TOLM, cum);
189 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
194 for(i = 0; i < DIMM_SOCKETS; i++) {
197 device = ctrl->channel0[i];
199 byte = spd_read_byte(device, 2); /* Type */
200 if ((byte == 7) || (byte == 8)) {
201 dimm_mask |= (1 << i);
204 device = ctrl->channel1[i];
206 byte = spd_read_byte(device, 2);
207 if ((byte == 7) || (byte == 8)) {
208 dimm_mask |= (1 << (i + DIMM_SOCKETS));
216 static int spd_set_row_attributes(const struct mem_controller *ctrl,
226 for(cnt=0; cnt < 4; cnt++) {
227 if (!(dimm_mask & (1 << cnt))) {
231 value = spd_read_byte(ctrl->channel0[cnt], 3); /* rows */
232 if (value < 0) goto hw_err;
233 if ((value & 0xf) == 0) goto val_err;
236 value = spd_read_byte(ctrl->channel0[cnt], 4); /* columns */
237 if (value < 0) goto hw_err;
238 if ((value & 0xf) == 0) goto val_err;
241 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
242 if (value < 0) goto hw_err;
243 if ((value & 0xff) == 0) goto val_err;
244 reg += log2(value & 0xff);
246 /* Get the device width and convert it to a power of two */
247 value = spd_read_byte(ctrl->channel0[cnt], 13);
248 if (value < 0) goto hw_err;
249 value = log2(value & 0xff);
251 if(reg < 27) goto hw_err;
255 dra += reg << (cnt*8);
256 value = spd_read_byte(ctrl->channel0[cnt], 5);
258 dra += reg << ((cnt*8)+4);
262 pci_write_config32(ctrl->f0, DRA, dra);
266 die("Bad SPD value\r\n");
267 /* If an hw_error occurs report that I have no memory */
276 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
277 long dimm_mask, uint32_t drc)
288 static const unsigned char cycle_time[3] = {0x75,0x60,0x50};
289 static const int latency_indicies[] = { 26, 23, 9 };
292 drt = pci_read_config32(ctrl->f0, DRT);
293 drt &= 3; /* save bits 1:0 */
295 for(first_dimm = 0; first_dimm < 4; first_dimm++) {
296 if (dimm_mask & (1 << first_dimm))
301 value = spd_read_byte(ctrl->channel0[first_dimm], 2);
303 drt |= (3<<5); /* back to bark write turn around & cycle add */
306 drt |= (3<<18); /* Trasmax */
308 for(cnt=0; cnt < 4; cnt++) {
309 if (!(dimm_mask & (1 << cnt))) {
312 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
313 /* Compute the lowest cas latency supported */
314 latency = log2(reg) -2;
316 /* Loop through and find a fast clock with a low latency */
317 for(index = 0; index < 3; index++, latency++) {
318 if ((latency < 2) || (latency > 4) ||
319 (!(reg & (1 << latency)))) {
322 value = spd_read_byte(ctrl->channel0[cnt],
323 latency_indicies[index]);
325 if(value <= cycle_time[drc&3]) {
326 if( latency > cas_latency) {
327 cas_latency = latency;
333 index = (cas_latency-2);
334 if((index)==0) cas_latency = 20;
335 else if((index)==1) cas_latency = 25;
336 else cas_latency = 30;
338 for(cnt=0;cnt<4;cnt++) {
339 if (!(dimm_mask & (1 << cnt))) {
342 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
343 if(((index>>8)&0x0ff)<reg) {
344 index &= ~(0x0ff << 8);
347 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
348 if(((index>>16)&0x0ff)<reg) {
349 index &= ~(0x0ff << 16);
352 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
353 if(((index2>>0)&0x0ff)<reg) {
354 index2 &= ~(0x0ff << 0);
357 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
358 if(((index2>>8)&0x0ff)<reg) {
359 index2 &= ~(0x0ff << 8);
362 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
363 if(((index2>>16)&0x0ff)<reg) {
364 index2 &= ~(0x0ff << 16);
370 value = cycle_time[drc&3];
371 if(value <= 0x50) { /* 200 MHz */
373 drt |= (2<<2); /* CAS latency 4 */
376 drt |= (1<<2); /* CAS latency 3 */
379 if((index&0x0ff00)<=0x03c00) {
380 drt |= (1<<8); /* Trp RAS Precharg */
382 drt |= (2<<8); /* Trp RAS Precharg */
385 /* Trcd RAS to CAS delay */
386 if((index2&0x0ff)<=0x03c) {
392 /* Tdal Write auto precharge recovery delay */
396 if((index2&0x0ff00)<=0x03700)
398 else if((index2&0xff00)<=0x03c00)
401 drt |= (2<<14); /* spd 41 */
403 drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */
406 if((index&0x0ff0000)<=0x0140000) {
408 } else if((index&0x0ff0000)<=0x0280000) {
410 } else if((index&0x0ff0000)<=0x03c0000) {
416 /* Trfc Auto refresh cycle time */
417 if((index2&0x0ff0000)<=0x04b0000) {
419 } else if((index2&0x0ff0000)<=0x0690000) {
424 /* Docs say use 55 for all 200Mhz */
427 else if(value <= 0x60) { /* 167 Mhz */
428 /* according to new documentation CAS latency is 00
429 * for bits 3:2 for all 167 Mhz
430 drt |= ((index&3)<<2); */ /* set CAS latency */
431 if((index&0x0ff00)<=0x03000) {
432 drt |= (1<<8); /* Trp RAS Precharg */
434 drt |= (2<<8); /* Trp RAS Precharg */
437 /* Trcd RAS to CAS delay */
438 if((index2&0x0ff)<=0x030) {
444 /* Tdal Write auto precharge recovery delay */
448 drt |= (2<<14); /* spd 41, but only one choice */
450 drt |= (2<<16); /* Twr not defined for DDR docs say 2 */
453 if((index&0x0ff0000)<=0x0180000) {
455 } else if((index&0x0ff0000)<=0x0300000) {
461 /* Trfc Auto refresh cycle time */
462 if((index2&0x0ff0000)<=0x0480000) {
464 } else if((index2&0x0ff0000)<=0x0780000) {
469 /* Docs state to use 99 for all 167 Mhz */
472 else if(value <= 0x75) { /* 133 Mhz */
473 drt |= ((index&3)<<2); /* set CAS latency */
474 if((index&0x0ff00)<=0x03c00) {
475 drt |= (1<<8); /* Trp RAS Precharg */
477 drt |= (2<<8); /* Trp RAS Precharg */
480 /* Trcd RAS to CAS delay */
481 if((index2&0x0ff)<=0x03c) {
487 /* Tdal Write auto precharge recovery delay */
491 drt |= (2<<14); /* spd 41, but only one choice */
493 drt |= (1<<16); /* Twr not defined for DDR docs say 1 */
496 if((index&0x0ff0000)<=0x01e0000) {
498 } else if((index&0x0ff0000)<=0x03c0000) {
504 /* Trfc Auto refresh cycle time */
505 if((index2&0x0ff0000)<=0x04b0000) {
507 } else if((index2&0x0ff0000)<=0x0780000) {
513 /* Based on CAS latency */
521 die("Invalid SPD 9 bus speed.\r\n");
525 pci_write_config32(ctrl->f0, DRT, drt);
530 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
538 unsigned char dram_type = 0xff;
539 unsigned char ecc = 0xff;
540 unsigned char rate = 62;
541 static const unsigned char spd_rates[6] = {15,3,7,7,62,62};
542 static const unsigned char drc_rates[5] = {0,15,7,62,3};
543 static const unsigned char fsb_conversion[4] = {3,1,3,2};
546 drc = pci_read_config32(ctrl->f0, DRC);
547 for(cnt=0; cnt < 4; cnt++) {
548 if (!(dimm_mask & (1 << cnt))) {
551 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
552 reg = spd_read_byte(ctrl->channel0[cnt], 2); /* Type */
553 if (value == 2) { /* RAM is ECC capable */
559 die("ERROR - Mixed DDR & DDR2 RAM\r\n");
562 else if ( reg == 7 ) {
566 else if ( ecc > 1 ) {
567 die("ERROR - Mixed DDR & DDR2 RAM\r\n");
571 die("ERROR - RAM not DDR\r\n");
575 die("ERROR - Non ECC memory dimm\r\n");
578 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
579 value &= 0x0f; /* clip self refresh bit */
580 if (value > 5) goto hw_err;
581 if (rate > spd_rates[value])
582 rate = spd_rates[value];
584 value = spd_read_byte(ctrl->channel0[cnt], 9); /* cycle time */
585 if (value > 0x75) goto hw_err;
587 if (dram_type >= 2) {
588 if (reg == 8) { /*speed is good, is this ddr2?*/
590 } else { /* not ddr2 so use ddr333 */
595 else if (value <= 0x60) {
596 if (dram_type >= 1) dram_type = 1;
598 else dram_type = 0; /* ddr266 */
602 if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
603 ecc = 0; /* ECC off in CMOS so disable it */
604 print_debug("ECC off\r\n");
607 print_debug("ECC on\r\n");
609 drc &= ~(3 << 20); /* clear the ecc bits */
610 drc |= (ecc << 20); /* or in the calculated ecc bits */
611 for ( cnt = 1; cnt < 5; cnt++)
612 if (drc_rates[cnt] == rate)
615 drc &= ~(7 << 8); /* clear the rate bits */
619 if (reg == 8) { /* independant clocks */
623 drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
624 drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
627 value = msr.lo >> 16;
629 drc &= ~(3 << 2); /* set the front side bus */
630 drc |= (fsb_conversion[value] << 2);
631 drc &= ~(3 << 0); /* set the dram type */
632 drc |= (dram_type << 0);
637 die("Bad SPD value\r\n");
638 /* If an hw_error occurs report that I have no memory */
645 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
649 /* Test if we can read the spd and if ram is ddr or ddr2 */
650 dimm_mask = spd_detect_dimms(ctrl);
651 if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
652 print_err("No memory for this cpu\r\n");
658 static void do_delay(void)
666 static void pll_setup(uint32_t drc)
669 if(drc&3) { /* DDR 333 or DDR 400 */
670 if((drc&0x0c) == 0x0c) { /* FSB 200 */
673 else if((drc&0x0c) == 0x08) { /* FSB 167 */
676 else if(drc&1){ /* FSB 133 DDR 333 */
679 else { /* FSB 133 DDR 400 */
684 if((drc&0x08) == 0x08) { /* FSB 200 or 167 */
691 mainboard_set_e7520_pll(pins);
695 #define TIMEOUT_LOOPS 300000
697 #define DCALCSR 0x100
698 #define DCALADDR 0x104
699 #define DCALDATA 0x108
701 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
708 /* Set up northbridge values */
710 pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
711 /* Figure out which slots are Empty, Single, or Double sided */
712 for(i=0,t4=0,c2=0;i<8;i+=2) {
713 c1 = pci_read_config8(ctrl->f0, DRB+i);
714 if(c1 == c2) continue;
715 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
723 if( ((t4>>8)&0x0f) == 0 ) {
724 data32 = 0x00000010; /* EEES */
727 if ( ((t4>>16)&0x0f) == 0 ) {
728 data32 = 0x00003132; /* EESS */
731 if ( ((t4>>24)&0x0f) == 0 ) {
732 data32 = 0x00335566; /* ESSS */
735 data32 = 0x77bbddee; /* SSSS */
739 if( ((t4>>8)&0x0f) == 0 ) {
740 data32 = 0x00003132; /* EEED */
743 if ( ((t4>>8)&0x0f) == 2 ) {
744 data32 = 0xb373ecdc; /* EEDD */
747 if ( ((t4>>16)&0x0f) == 0 ) {
748 data32 = 0x00b3a898; /* EESD */
751 data32 = 0x777becdc; /* ESSD */
754 die("Error - First dimm slot empty\r\n");
757 print_debug("ODT Value = ");
758 print_debug_hex32(data32);
761 pci_write_config32(ctrl->f0, 0xb0, data32);
763 for(dimm=0;dimm<8;dimm+=1) {
765 write32(BAR+DCALADDR, 0x0b840001);
766 write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
768 for(i=0;i<1001;i++) {
769 data32 = read32(BAR+DCALCSR);
770 if(!(data32 & (1<<31)))
775 static void set_receive_enable(const struct mem_controller *ctrl)
786 uint32_t data32_dram;
787 uint32_t dcal_data32_0;
788 uint32_t dcal_data32_1;
789 uint32_t dcal_data32_2;
790 uint32_t dcal_data32_3;
795 for(dimm=0;dimm<8;dimm+=1) {
798 write32(BAR+DCALDATA+(17*4), 0x04020000);
799 write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
801 for(i=0;i<1001;i++) {
802 data32 = read32(BAR+DCALCSR);
803 if(!(data32 & (1<<31)))
809 dcal_data32_0 = read32(BAR+DCALDATA + 0);
810 dcal_data32_1 = read32(BAR+DCALDATA + 4);
811 dcal_data32_2 = read32(BAR+DCALDATA + 8);
812 dcal_data32_3 = read32(BAR+DCALDATA + 12);
815 dcal_data32_0 = read32(BAR+DCALDATA + 16);
816 dcal_data32_1 = read32(BAR+DCALDATA + 20);
817 dcal_data32_2 = read32(BAR+DCALDATA + 24);
818 dcal_data32_3 = read32(BAR+DCALDATA + 28);
821 /* check if bank is installed */
822 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
824 /* Calculate the timing value */
827 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
828 work32l=dcal_data32_1,work32h=dcal_data32_3;
831 if(work32l & (1<<cnt))
834 work32l = dcal_data32_0;
835 work32h = dcal_data32_2;
841 if(!(work32l & (1<<cnt)))
844 work32l = dcal_data32_0;
845 work32h = dcal_data32_2;
853 data32 = ((bit%8) << 1);
854 if(work32h & (1<<cnt))
879 work32l = dcal_data32_0;
880 work32h = dcal_data32_2;
886 if(!(work32l & (1<<cnt)))
889 if(work32l & (1<<cnt))
892 data32 = (((cnt-1)%8)<<1);
893 if(work32h & (1<<(cnt-1))) {
896 /* test for frame edge cross overs */
897 if((edge == 1) && (data32 > 12) &&
898 (((recen+16)-data32) < 3)) {
902 if((edge == 2) && (data32 < 4) &&
903 ((recen - data32) > 12)) {
907 if(((recen+3) >= data32) && ((recen-3) <= data32))
917 recen+=2; /* this is not in the spec, but matches
918 the factory output, and has less failure */
919 recen <<= (dimm/2) * 8;
928 /* Check for Eratta problem */
929 for(i=cnt=0;i<32;i+=8) {
930 if (((recena>>i)&0x0f)>7) {
934 if((recena>>i)&0x0f) {
940 cnt = (cnt&0x0f) - (cnt>>16);
943 if(((recena>>i)&0x0f)>7) {
944 recena &= ~(0x0f<<i);
951 if(((recena>>i)&0x0f)<8) {
952 recena &= ~(0x0f<<i);
958 for(i=cnt=0;i<32;i+=8) {
959 if (((recenb>>i)&0x0f)>7) {
963 if((recenb>>i)&0x0f) {
969 cnt = (cnt&0x0f) - (cnt>>16);
972 if(((recenb>>i)&0x0f)>7) {
973 recenb &= ~(0x0f<<i);
980 if(((recenb>>8)&0x0f)<8) {
981 recenb &= ~(0x0f<<i);
988 print_debug("Receive enable A = ");
989 print_debug_hex32(recena);
990 print_debug(", Receive enable B = ");
991 print_debug_hex32(recenb);
994 /* clear out the calibration area */
995 write32(BAR+DCALDATA+(16*4), 0x00000000);
996 write32(BAR+DCALDATA+(17*4), 0x00000000);
997 write32(BAR+DCALDATA+(18*4), 0x00000000);
998 write32(BAR+DCALDATA+(19*4), 0x00000000);
1001 write32(BAR+DCALCSR, 0x0000000f);
1003 write32(BAR+0x150, recena);
1004 write32(BAR+0x154, recenb);
1008 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1019 volatile unsigned long *iptrv;
1024 static const struct {
1027 /* FSB 133 DIMM 266 */
1028 {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1029 /* FSB 133 DIMM 333 */
1030 {{ 0x00000000, 0x00000000, 0x00000000, 0x00000000}},
1031 /* FSB 133 DIMM 400 */
1032 {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
1033 /* FSB 167 DIMM 266 */
1034 {{ 0x00005432, 0x00001000, 0x00004325, 0x00000000}},
1035 /* FSB 167 DIMM 333 */
1036 {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1037 /* FSB 167 DIMM 400 */
1038 {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
1039 /* FSB 200 DIMM 266 */
1040 {{ 0x00000032, 0x00000010, 0x00000120, 0x00000000}},
1041 /* FSB 200 DIMM 333 */
1042 {{ 0x00065432, 0x00010000, 0x00154320, 0x00000000}},
1043 /* FSB 200 DIMM 400 */
1044 {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
1047 static const uint32_t dqs_data[] = {
1048 0xffffffff, 0xffffffff, 0x000000ff,
1049 0xffffffff, 0xffffffff, 0x000000ff,
1050 0xffffffff, 0xffffffff, 0x000000ff,
1051 0xffffffff, 0xffffffff, 0x000000ff,
1052 0xffffffff, 0xffffffff, 0x000000ff,
1053 0xffffffff, 0xffffffff, 0x000000ff,
1054 0xffffffff, 0xffffffff, 0x000000ff,
1055 0xffffffff, 0xffffffff, 0x000000ff};
1057 mask = spd_detect_dimms(ctrl);
1058 print_debug("Starting SDRAM Enable\r\n");
1061 #ifdef DIMM_MAP_LOGICAL
1062 pci_write_config32(ctrl->f0, DRM,
1063 0x00210000 | DIMM_MAP_LOGICAL);
1065 pci_write_config32(ctrl->f0, DRM, 0x00211248);
1067 /* set dram type and Front Side Bus freq. */
1068 drc = spd_set_dram_controller_mode(ctrl, mask);
1070 die("Error calculating DRC\r\n");
1073 data32 = drc & ~(3 << 20); /* clear ECC mode */
1074 data32 = data32 & ~(7 << 8); /* clear refresh rates */
1075 data32 = data32 | (1 << 5); /* temp turn off of ODT */
1076 /* Set gearing, then dram controller mode */
1077 /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
1078 for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
1080 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
1083 pci_write_config32(ctrl->f0, DRC, data32);
1085 /* turn the clocks on */
1087 pci_write_config16(ctrl->f0, CKDIS, 0x0000);
1089 /* 0x9a DDRCSR Take subsystem out of idle */
1090 data16 = pci_read_config16(ctrl->f0, DDRCSR);
1091 data16 &= ~(7 << 12);
1092 data16 |= (3 << 12); /* use dual channel lock step */
1093 pci_write_config16(ctrl->f0, DDRCSR, data16);
1095 /* program row size DRB */
1096 spd_set_ram_size(ctrl, mask);
1098 /* program page size DRA */
1099 spd_set_row_attributes(ctrl, mask);
1101 /* program DRT timing values */
1102 cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1104 for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
1105 print_debug("DIMM ");
1106 print_debug_hex8(i);
1107 print_debug("\r\n");
1111 write32(BAR + 0x100, (0x03000000 | (i<<20)));
1113 write32(BAR+0x100, (0x83000000 | (i<<20)));
1115 data32 = read32(BAR+DCALCSR);
1116 while(data32 & 0x80000000)
1117 data32 = read32(BAR+DCALCSR);
1124 for(cs=0;cs<8;cs++) {
1125 write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
1126 data32 = read32(BAR+DCALCSR);
1127 while(data32 & 0x80000000)
1128 data32 = read32(BAR+DCALCSR);
1131 /* Precharg all banks */
1133 for(cs=0;cs<8;cs++) {
1134 if ((drc & 3) == 2) /* DDR2 */
1135 write32(BAR+DCALADDR, 0x04000000);
1137 write32(BAR+DCALADDR, 0x00000000);
1138 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1139 data32 = read32(BAR+DCALCSR);
1140 while(data32 & 0x80000000)
1141 data32 = read32(BAR+DCALCSR);
1144 /* EMRS dll's enabled */
1146 for(cs=0;cs<8;cs++) {
1147 if ((drc & 3) == 2) /* DDR2 */
1148 /* fixme hard code AL additive latency */
1149 write32(BAR+DCALADDR, 0x0b940001);
1151 write32(BAR+DCALADDR, 0x00000001);
1152 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1153 data32 = read32(BAR+DCALCSR);
1154 while(data32 & 0x80000000)
1155 data32 = read32(BAR+DCALCSR);
1157 /* MRS reset dll's */
1159 if ((drc & 3) == 2) { /* DDR2 */
1160 if(cas_latency == 30)
1161 mode_reg = 0x053a0000;
1163 mode_reg = 0x054a0000;
1166 if(cas_latency == 20)
1167 mode_reg = 0x012a0000;
1168 else /* CAS Latency 2.5 */
1169 mode_reg = 0x016a0000;
1171 for(cs=0;cs<8;cs++) {
1172 write32(BAR+DCALADDR, mode_reg);
1173 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1174 data32 = read32(BAR+DCALCSR);
1175 while(data32 & 0x80000000)
1176 data32 = read32(BAR+DCALCSR);
1179 /* Precharg all banks */
1183 for(cs=0;cs<8;cs++) {
1184 if ((drc & 3) == 2) /* DDR2 */
1185 write32(BAR+DCALADDR, 0x04000000);
1187 write32(BAR+DCALADDR, 0x00000000);
1188 write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
1189 data32 = read32(BAR+DCALCSR);
1190 while(data32 & 0x80000000)
1191 data32 = read32(BAR+DCALCSR);
1194 /* Do 2 refreshes */
1196 for(cs=0;cs<8;cs++) {
1197 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1198 data32 = read32(BAR+DCALCSR);
1199 while(data32 & 0x80000000)
1200 data32 = read32(BAR+DCALCSR);
1203 for(cs=0;cs<8;cs++) {
1204 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1205 data32 = read32(BAR+DCALCSR);
1206 while(data32 & 0x80000000)
1207 data32 = read32(BAR+DCALCSR);
1210 /* for good luck do 6 more */
1211 for(cs=0;cs<8;cs++) {
1212 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1215 for(cs=0;cs<8;cs++) {
1216 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1219 for(cs=0;cs<8;cs++) {
1220 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1223 for(cs=0;cs<8;cs++) {
1224 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1227 for(cs=0;cs<8;cs++) {
1228 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1231 for(cs=0;cs<8;cs++) {
1232 write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
1235 /* MRS reset dll's normal */
1237 for(cs=0;cs<8;cs++) {
1238 write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
1239 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1240 data32 = read32(BAR+DCALCSR);
1241 while(data32 & 0x80000000)
1242 data32 = read32(BAR+DCALCSR);
1245 /* Do only if DDR2 EMRS dll's enabled */
1246 if ((drc & 3) == 2) { /* DDR2 */
1248 for(cs=0;cs<8;cs++) {
1249 write32(BAR+DCALADDR, (0x0b940001));
1250 write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
1251 data32 = read32(BAR+DCALCSR);
1252 while(data32 & 0x80000000)
1253 data32 = read32(BAR+DCALCSR);
1259 write32(BAR+DCALCSR, 0x0000000f);
1261 /* DDR1 This is test code to copy some codes in the factory setup */
1263 write32(BAR, 0x00100000);
1265 if ((drc & 3) == 2) { /* DDR2 */
1266 /* enable on dimm termination */
1267 set_on_dimm_termination_enable(ctrl);
1270 pci_write_config32(ctrl->f0, 0x88, 0xa0000000 );
1273 /* receive enable calibration */
1274 set_receive_enable(ctrl);
1277 pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1278 for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
1279 write32(cnt, dqs_data[i]);
1281 pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
1283 /* Enable refresh */
1285 data32 = drc & ~(3 << 20); /* clear ECC mode */
1286 pci_write_config32(ctrl->f0, DRC, data32);
1287 write32(BAR+DCALCSR, 0x0008000f);
1289 /* clear memory and init ECC */
1290 print_debug("Clearing memory\r\n");
1291 for(i=0;i<64;i+=4) {
1292 write32(BAR+DCALDATA+i, 0x00000000);
1295 for(cs=0;cs<8;cs++) {
1296 write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
1297 data32 = read32(BAR+DCALCSR);
1298 while(data32 & 0x80000000)
1299 data32 = read32(BAR+DCALCSR);
1302 /* Bring memory subsystem on line */
1303 data32 = pci_read_config32(ctrl->f0, 0x98);
1304 data32 |= (1 << 31);
1305 pci_write_config32(ctrl->f0, 0x98, data32);
1306 /* wait for completion */
1307 print_debug("Waiting for mem complete\r\n");
1309 data32 = pci_read_config32(ctrl->f0, 0x98);
1310 if( (data32 & (1<<31)) == 0)
1313 print_debug("Done\r\n");
1315 /* Set initialization complete */
1318 data32 = drc & ~(3 << 20); /* clear ECC mode */
1319 pci_write_config32(ctrl->f0, DRC, data32);
1321 /* Set the ecc mode */
1322 pci_write_config32(ctrl->f0, DRC, drc);
1324 /* Enable memory scrubbing */
1326 data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1328 data16 |= ((2 << 2) | (2 << 0));
1329 pci_write_config16(ctrl->f0, MCHSCRB, data16);
1331 /* The memory is now setup, use it */
1332 cache_lbmem(MTRR_TYPE_WRBACK);