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Configure CIMx to use 33 MHz fast mode for SPD read.
[coreboot.git]
/
src
/
northbridge
/
intel
/
e7520
/
northbridge.h
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#ifndef NORTHBRIDGE_INTEL_E7520_H
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#define NORTHBRIDGE_INTEL_E7520_H
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extern unsigned int e7520_scan_root_bus(device_t root, unsigned int max);
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#endif /* NORTHBRIDGE_INTEL_E7520_H */
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