1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/hypertransport.h>
13 #include "northbridge.h"
17 static unsigned int max_bus;
19 static void ram_resource(device_t dev, unsigned long index,
20 unsigned long basek, unsigned long sizek)
22 struct resource *resource;
24 resource = new_resource(dev, index);
25 resource->base = ((resource_t)basek) << 10;
26 resource->size = ((resource_t)sizek) << 10;
27 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
28 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
32 static void pci_domain_read_resources(device_t dev)
34 struct resource *resource;
36 /* Initialize the system wide io space constraints */
37 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
42 resource->limit = 0xffffUL;
43 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
45 /* Initialize the system wide memory resources constraints */
46 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
51 resource->limit = 0xffffffffUL;
52 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
55 static void tolm_test(void *gp, struct device *dev, struct resource *new)
57 struct resource **best_p = gp;
58 struct resource *best;
60 if (!best || (best->base > new->base)) {
66 static uint32_t find_pci_tolm(struct bus *bus)
71 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
73 if (min && tolm > min->base) {
80 static void pci_domain_set_resources(device_t dev)
85 pci_tolm = find_pci_tolm(&dev->link[0]);
88 printk_debug("PCI mem marker = %x\n", pci_tolm);
90 /* FIXME Me temporary hack */
91 if(pci_tolm > 0xe0000000)
92 pci_tolm = 0xe0000000;
93 /* Ensure pci_tolm is 128M aligned */
94 pci_tolm &= 0xf8000000;
95 mc_dev = dev->link[0].children;
97 /* Figure out which areas are/should be occupied by RAM.
98 * This is all computed in kilobytes and converted to/from
99 * the memory controller right at the edges.
100 * Having different variables in different units is
101 * too confusing to get right. Kilobytes are good up to
102 * 4 Terabytes of RAM...
104 uint16_t tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
105 unsigned long tomk, tolmk;
106 unsigned long remapbasek, remaplimitk, remapoffsetk;
108 /* Get the Top of Memory address, units are 128M */
109 tomk = ((unsigned long)pci_read_config16(mc_dev, TOM)) << 17;
110 /* Compute the Top of Low Memory */
111 tolmk = (pci_tolm & 0xf8000000) >> 10;
114 /* The PCI hole does not overlap memory
115 * we won't use the remap window.
118 remapbasek = 0x3ff << 16;
119 remaplimitk = 0 << 16;
120 remapoffsetk = 0 << 16;
123 /* The PCI memory hole overlaps memory
124 * setup the remap window.
126 /* Find the bottom of the remap window
129 remapbasek = 4*1024*1024;
130 if (tomk > remapbasek) {
133 /* Find the limit of the remap window */
134 remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
135 /* Find the offset of the remap window from tolm */
136 remapoffsetk = remapbasek - tolmk;
138 /* Write the ram configruation registers,
139 * preserving the reserved bits.
141 tolm_r = pci_read_config16(mc_dev, 0xc4);
142 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
143 pci_write_config16(mc_dev, 0xc4, tolm_r);
145 remapbase_r = pci_read_config16(mc_dev, 0xc6);
146 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
147 pci_write_config16(mc_dev, 0xc6, remapbase_r);
149 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
150 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
151 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
153 remapoffset_r = pci_read_config16(mc_dev, 0xca);
154 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
155 pci_write_config16(mc_dev, 0xca, remapoffset_r);
157 /* Report the memory regions */
158 ram_resource(dev, 3, 0, 640);
159 ram_resource(dev, 4, 768, (tolmk - 768));
160 if (tomk > 4*1024*1024) {
161 ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
163 if (remaplimitk >= remapbasek) {
164 ram_resource(dev, 6, remapbasek,
165 (remaplimitk + 64*1024) - remapbasek);
168 assign_resources(&dev->link[0]);
171 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
173 max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
180 static struct device_operations pci_domain_ops = {
181 .read_resources = pci_domain_read_resources,
182 .set_resources = pci_domain_set_resources,
183 .enable_resources = enable_childrens_resources,
185 .scan_bus = pci_domain_scan_bus,
186 .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
189 static void mc_read_resources(device_t dev)
191 struct resource *resource;
193 pci_dev_read_resources(dev);
195 resource = new_resource(dev, 0xcf);
196 resource->base = 0xe0000000;
197 resource->size = max_bus * 4096*256;
198 resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
201 static void mc_set_resources(device_t dev)
203 struct resource *resource, *last;
205 last = &dev->resource[dev->resources];
206 resource = find_resource(dev, 0xcf);
208 report_resource_stored(dev, resource, "<mmconfig>");
210 pci_dev_set_resources(dev);
213 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
215 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
216 ((device & 0xffff) << 16) | (vendor & 0xffff));
219 static struct pci_operations intel_pci_ops = {
220 .set_subsystem = intel_set_subsystem,
223 static struct device_operations mc_ops = {
224 .read_resources = mc_read_resources,
225 .set_resources = mc_set_resources,
226 .enable_resources = pci_dev_enable_resources,
229 .ops_pci = &intel_pci_ops,
232 static const struct pci_driver mc_driver __pci_driver = {
234 .vendor = PCI_VENDOR_ID_INTEL,
238 static void cpu_bus_init(device_t dev)
240 initialize_cpus(&dev->link[0]);
243 static void cpu_bus_noop(device_t dev)
247 static struct device_operations cpu_bus_ops = {
248 .read_resources = cpu_bus_noop,
249 .set_resources = cpu_bus_noop,
250 .enable_resources = cpu_bus_noop,
251 .init = cpu_bus_init,
256 static void enable_dev(device_t dev)
258 /* Set the operations if it is a special bus type */
259 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
260 dev->ops = &pci_domain_ops;
262 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
263 dev->ops = &cpu_bus_ops;
267 struct chip_operations northbridge_intel_e7520_ops = {
268 CHIP_NAME("Intel E7520 Northbridge")
269 .enable_dev = enable_dev,