1 /* This was originally for the e7500, modified for e7501
2 * The primary differences are that 7501 apparently can
3 * support single channel RAM (i haven't tested),
4 * CAS1.5 is no longer supported, The ECC scrubber
5 * now supports a mode to zero RAM and init ECC in one step
6 * and the undocumented registers at 0x80 require new
7 * (undocumented) values determined by guesswork and
8 * comparison w/ OEM BIOS values.
9 * Steven James 02/06/2003
12 /* converted to C 6/2004 yhlu */
16 #include <sdram_mode.h>
20 // Uncomment this to enable run-time checking of DIMM parameters
21 // for dual-channel operation
22 // Unfortunately the code seems to chew up several K of space.
23 //#define VALIDATE_DIMM_COMPATIBILITY
25 // Uncomment this to enable local debugging messages
26 //#define DEBUG_RAM_CONFIG
28 #if defined(DEBUG_RAM_CONFIG)
29 #define RAM_DEBUG_MESSAGE(x) print_debug(x)
30 #define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
31 #define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
32 #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
34 #define RAM_DEBUG_MESSAGE(x)
35 #define RAM_DEBUG_HEX32(x)
36 #define RAM_DEBUG_HEX8(x)
40 #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
41 #define SPD_ERROR "Error reading SPD info\r\n"
43 // NOTE: This used to be 0x100000.
44 // That doesn't work on systems where A20M# is asserted, because
45 // attempts to access 0x1000NN end up accessing 0x0000NN.
46 #define RCOMP_MMIO 0x200000
53 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
55 /**********************************************************************************/
57 static const uint32_t refresh_frequency[]= {
58 /* Relative frequency (array value) of each E7501 Refresh Mode Select
59 * (RMS) value (array index)
60 * 0 == least frequent refresh (longest interval between refreshes)
70 0, 2, 3, 1, 0, 0, 0, 4 };
72 static const uint32_t refresh_rate_map[] = {
73 /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
74 * Select values (array value)
75 * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
76 * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
77 * 64 clock (481 ns) (7) refresh.
78 * [0] == 15.625 us -> 15.6 us
79 * [1] == 3.9 us -> 481 ns
80 * [2] == 7.8 us -> 7.8 us
81 * [3] == 31.3 us -> 15.6 us
82 * [4] == 62.5 us -> 15.6 us
83 * [5] == 125 us -> 64 us
87 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
90 // SPD parameters that must match for dual-channel operation
91 static const uint8_t dual_channel_parameters[] = {
97 SPD_PRIMARY_SDRAM_WIDTH,
98 SPD_NUM_BANKS_PER_SDRAM
102 * Table: constant_register_values
104 static const long constant_register_values[] = {
105 /* SVID - Subsystem Vendor Identification Register
107 * [15:00] Subsytem Vendor ID (Indicates system board vendor)
109 /* SID - Subsystem Identification Register
111 * [15:00] Subsystem ID
113 // Not everyone wants to be Super Micro Computer, Inc.
114 // The mainboard should set this if desired.
115 // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
118 * (DRAM Read Timing Control, if similar to 855PM?)
120 * This register has something to do with CAS latencies,
121 * possibily this is the real chipset control.
122 * At 0x00 CAS latency 1.5 works.
123 * At 0x06 CAS latency 2.5 works.
124 * At 0x01 CAS latency 2.0 works.
126 /* This is still undocumented in e7501, but with different values
127 * CAS 2.0 values taken from Intel BIOS settings, others are a guess
128 * and may be terribly wrong. Old values preserved as comments until I
129 * figure this out for sure.
130 * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
132 * Steven James 02/06/2003
134 /* NOTE: values now configured in configure_e7501_cas_latency() based
135 * on SPD info and total number of DIMMs (per Intel)
138 /* FDHC - Fixed DRAM Hole Control
141 * 0 == No memory Hole
142 * 1 == Memory Hole from 15MB to 16MB
145 * PAM - Programmable Attribute Map
146 * 0x59 [1:0] Reserved
147 * 0x59 [5:4] 0xF0000 - 0xFFFFF
148 * 0x5A [1:0] 0xC0000 - 0xC3FFF
149 * 0x5A [5:4] 0xC4000 - 0xC7FFF
150 * 0x5B [1:0] 0xC8000 - 0xCBFFF
151 * 0x5B [5:4] 0xCC000 - 0xCFFFF
152 * 0x5C [1:0] 0xD0000 - 0xD3FFF
153 * 0x5C [5:4] 0xD4000 - 0xD7FFF
154 * 0x5D [1:0] 0xD8000 - 0xDBFFF
155 * 0x5D [5:4] 0xDC000 - 0xDFFFF
156 * 0x5E [1:0] 0xE0000 - 0xE3FFF
157 * 0x5E [5:4] 0xE4000 - 0xE7FFF
158 * 0x5F [1:0] 0xE8000 - 0xEBFFF
159 * 0x5F [5:4] 0xEC000 - 0xEFFFF
160 * 00 == DRAM Disabled (All Access go to memory mapped I/O space)
161 * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
162 * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
163 * 11 == Normal (All Access go to DRAM)
166 // Map all legacy ranges to DRAM
167 0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
168 0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
170 /* DRB - DRAM Row Boundary Registers
172 * An array of 8 byte registers, which hold the ending
173 * memory address assigned to each pair of DIMMS, in 64MB
176 // Conservatively say each row has 64MB of ram, we will fix this up later
177 // NOTE: These defaults allow us to prime all of the DIMMs on the board
178 // without jumping through 36-bit adddressing hoops, even if the
179 // total memory is > 4 GB. Changing these values may break do_ram_command()!
180 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
181 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
183 /* DRA - DRAM Row Attribute Register
188 * [7:7] Device width for Odd numbered rows
189 * 0 == 8 bits wide x8
190 * 1 == 4 bits wide x4
191 * [6:4] Row Attributes for Odd numbered rows
192 * 010 == 8KB (for dual-channel)
193 * 011 == 16KB (for dual-channel)
194 * 100 == 32KB (for dual-channel)
195 * 101 == 64KB (for dual-channel)
197 * [3:3] Device width for Even numbered rows
198 * 0 == 8 bits wide x8
199 * 1 == 4 bits wide x4
200 * [2:0] Row Attributes for Even numbered rows
201 * 010 == 8KB (for dual-channel)
202 * 011 == 16KB (for dual-channel)
203 * 100 == 32KB (for dual-channel)
204 * 101 == 64KB (This page size appears broken)
207 // NOTE: overridden by configure_e7501_row_attributes(), later
210 /* DRT - DRAM Timing Register
213 * [29:29] Back to Back Write-Read Turn Around
214 * 0 == 3 clocks between WR-RD commands
215 * 1 == 2 clocks between WR-RD commands
216 * [28:28] Back to Back Read-Write Turn Around
217 * 0 == 5 clocks between RD-WR commands
218 * 1 == 4 clocks between RD-WR commands
219 * [27:27] Back to Back Read Turn Around
220 * 0 == 4 clocks between RD commands
221 * 1 == 3 clocks between RD commands
222 * [26:24] Read Delay (tRD)
228 * [18:16] DRAM idle timer
230 * 011 == 16 dram clocks
233 * [10:09] Active to Precharge (tRAS)
239 * [05:04] Cas Latency (tCL)
242 * 10 == Reserved (was 1.5 Clocks for E7500)
244 * [03:03] Write Ras# to Cas# Delay (tRCD)
247 * [02:01] Read RAS# to CAS# Delay (tRCD)
250 * 10 == 3 DRAM Clocks
251 * 11 == 2 DRAM Clocks
252 * [00:00] DRAM RAS# to Precharge (tRP)
257 // Some earlier settings:
258 /* Most aggressive settings possible */
259 // 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0),
260 // 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
261 // 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
263 // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
264 // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
265 0x78, 0xD7F8FFFF, (1<<29)|(1<<27)|(1<<16),
267 /* FIXME why was I attempting to set a reserved bit? */
270 /* DRC - DRAM Contoller Mode Register
273 * [29:29] Initialization Complete
278 * 0 == Single channel
280 * [21:20] DRAM Data Integrity Mode
281 * 00 == Disabled, no ECC
283 * 10 == Error checking, using chip-kill, with correction
285 * [19:18] DRB Granularity (Read-Only)
286 * 00 == 32 MB quantities (single channel mode)
287 * 01 == 64 MB quantities (dual-channel mode)
290 * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below)
291 * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
295 * [10:08] Refresh mode select
296 * 000 == Refresh disabled
297 * 001 == Refresh interval 15.6 usec
298 * 010 == Refresh interval 7.8 usec
299 * 011 == Refresh interval 64 usec
300 * 111 == Refresh every 64 clocks (fast refresh)
302 * [06:04] Mode Select (SMS)
303 * 000 == Reserved (was Self Refresh Mode in E7500)
305 * 010 == All Banks Precharge
306 * 011 == Mode Register Set
307 * 100 == Extended Mode Register Set
310 * 111 == Normal Operation
313 // .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
314 // .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
315 // .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
317 // Default to dual-channel mode, ECC, 1-clock address/cmd hold
318 // NOTE: configure_e7501_dram_controller_mode() configures further
319 0x7c, 0xff8ef8ff, (1<<22)|(2<<20)|(1<<16)|(0<<8),
321 /* Another Intel undocumented register
323 * [31:31] Purpose unknown
324 * [26:26] Master DLL Reset?
325 * 0 == Normal operation?
327 * [07:07] Periodic memory recalibration?
330 * [04:04] Receive FIFO RE-Sync?
331 * 0 == Normal operation?
334 // NOTE: Some factory BIOSs don't do this.
335 // Doesn't seem to matter either way.
336 0x88, 0xffffff00, 0x80,
338 /* CLOCK_DIS - CK/CK# Disable Register
340 * [7:7] DDR Frequency
341 * 0 == 100 MHz (200 MHz data rate)
342 * 1 == 133 MHz (266 MHz data rate)
357 // NOTE: Disable all clocks initially; turn ones we need back on
358 // in enable_e7501_clocks()
359 0x8C, 0xfffffff0, 0xf,
361 /* TOLM - Top of Low Memory Register
363 * [15:11] Top of low memory (TOLM)
364 * The address below 4GB that should be treated as RAM,
365 * on a 128MB granularity.
368 /* REMAPBASE - Remap Base Address Regsiter
371 * [09:00] Remap Base Address [35:26] 64M aligned
372 * Bits [25:0] are assumed to be 0.
375 // NOTE: TOLM overridden by configure_e7501_ram_addresses()
376 0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
378 /* REMAPLIMIT - Remap Limit Address Register
381 * [09:00] Remap Limit Address [35:26] 64M aligned
382 * When remaplimit < remapbase the remap window is disabled.
386 /* DVNP - Device Not Present Register
389 * [04:04] Device 4 Function 1 Present
392 * [03:03] Device 3 Function 1 Present
395 * [02:02] Device 2 Function 1 Present
399 * [00:00] Device 0 Function 1 Present
404 // Enable D0:D1, disable D2:F1, D3:F1, D4:F1
405 0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
408 0xd8, 0xffff9fff, 0x00000000,
410 // Undocumented - this is pure conjecture based on similarity to 855PM
411 /* MCHTST - MCH Test Register
413 * [31:31] Purpose unknown
414 * [30:30] Purpose unknown
415 * [29:23] Unknown - not used?
416 * [22:22] System Memory MMR Enable
417 * 0 == Disable: mem space and BAR at 0x14 are not accessible
418 * 1 == Enable: mem space and BAR at 0x14 are accessible
419 * [21:20] Purpose unknown
420 * [19:02] Unknown - not used?
421 * [01:01] D6EN (Device #6 enable)
424 * [00:00] Unknown - not used?
427 0xf4, 0x3f8ffffd, 0x40300002,
429 #ifdef SUSPICIOUS_LOOKING_CODE
430 // SJM: Undocumented.
431 // This will access D2:F0:0x50, is this correct??
432 0x1050, 0xffffffcf, 0x00000030,
436 /* DDR RECOMP tables */
438 // Slew table for 1x drive?
439 static const uint32_t maybe_1x_slew_table[] = {
440 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
441 0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
444 // Slew table for 2x drive?
445 static const uint32_t maybe_2x_slew_table[] = {
446 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
447 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
450 // Pull Up / Pull Down offset table, if analogous to IXP2800?
451 static const uint32_t maybe_pull_updown_offset_table[] = {
452 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
453 0x88888888, 0x88888888, 0x88888888, 0x88888888,
456 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
458 /**********************************************************************************/
459 #define SLOW_DOWN_IO inb(0x80);
460 //#define SLOW_DOWN_IO udelay(40);
462 /* Estimate that SLOW_DOWN_IO takes about 50&76us*/
463 /* delay for 200us */
466 static void do_delay(void)
469 for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
471 #define DO_DELAY do_delay();
477 #define EXTRA_DELAY DO_DELAY
480 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
481 /* DELAY FUNCTIONS */
482 /**********************************************************************************/
484 static void die_on_spd_error(int spd_return_value)
486 if (spd_return_value < 0)
487 die("Error reading SPD info\r\n");
490 //----------------------------------------------------------------------------------
491 // Function: sdram_spd_get_page_size
492 // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
493 // Return Value: struct dimm_size - log2(page size) for each side of the DIMM.
494 // Description: Calculate the page size for each physical bank of the DIMM:
495 // log2(page size) = (# columns) + log2(data width)
497 // NOTE: page size is the total number of data bits in a row.
499 static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
501 uint16_t module_data_width;
503 struct dimm_size pgsz;
509 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
510 if (value < 0) goto hw_err;
511 pgsz.side1 = value & 0xf; // # columns in bank 1
513 /* Get the module data width and convert it to a power of two */
514 value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
515 if (value < 0) goto hw_err;
516 module_data_width = (value & 0xff) << 8;
518 value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
519 if (value < 0) goto hw_err;
520 module_data_width |= (value & 0xff);
522 pgsz.side1 += log2(module_data_width);
525 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
526 if (value < 0) goto hw_err;
528 die("Bad SPD value\r\n");
531 pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
532 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
533 if (value < 0) goto hw_err;
534 if ((value & 0xf0) != 0) {
536 pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */
537 pgsz.side2 += (value>>4) & 0xf; /* Add in columns on side 2 */
545 return pgsz; // Never reached
549 //----------------------------------------------------------------------------------
550 // Function: sdram_spd_get_width
551 // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
552 // Return Value: dimm_size - width in bits of each DIMM side's DRAMs.
553 // Description: Read the width in bits of each DIMM side's DRAMs via SPD.
556 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
559 struct dimm_size width;
564 value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
565 die_on_spd_error(value);
567 width.side1 = value & 0x7f; // Mask off bank 2 flag
570 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
572 // If bank 2 exists, it's the same width as bank 1
573 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
574 die_on_spd_error(value);
576 #ifdef ROMCC_IF_BUG_FIXED
578 width.side2 = width.side1;
582 width.side2 = width.side1;
594 //----------------------------------------------------------------------------------
595 // Function: spd_get_dimm_size
596 // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
597 // Return Value: dimm_size - log2(number of bits) for each side of the DIMM
598 // Description: Calculate the log base 2 size in bits of both DIMM sides.
599 // log2(# bits) = (# columns) + log2(data width) +
600 // (# rows) + log2(banks per SDRAM)
602 // Note that it might be easier to use SPD byte 31 here, it has the
603 // DIMM size as a multiple of 4MB. The way we do it now we can size
604 // both sides of an asymmetric dimm.
606 static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
610 // Start with log2(page size)
611 struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
615 value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);
616 die_on_spd_error(value);
618 sz.side1 += value & 0xf;
624 sz.side2 += value >> 4; // Asymmetric
626 sz.side2 += value; // Symmetric
629 value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM);
630 die_on_spd_error(value);
641 //----------------------------------------------------------------------------------
642 // Function: are_spd_values_equal
643 // Parameters: spd_byte_number -
644 // dimmN_address - SMBus addresses of DIMM sockets to interrogate
645 // Return Value: 1 if both DIMM sockets report the same value for the specified
646 // SPD parameter; 0 if the values differed or an error occurred.
647 // Description: Determine whether two DIMMs have the same value for a SPD parameter.
649 static uint8_t are_spd_values_equal(uint8_t spd_byte_number, uint16_t dimm0_address,
650 uint16_t dimm1_address)
654 int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
655 int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
657 if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value))
663 //----------------------------------------------------------------------------------
664 // Function: spd_get_supported_dimms
665 // Parameters: ctrl - PCI addresses of memory controller functions, and
666 // SMBus addresses of DIMM slots on the mainboard
667 // Return Value: uint8_t - a bitmask indicating which of the possible sockets
668 // for each channel was found to contain a compatible DIMM.
669 // Bit 0 corresponds to the closest socket for channel 0,
670 // Bit 1 to the next socket for channel 0,
672 // Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0,
673 // Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1,
675 // Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
676 // Description: Scan for compatible DIMMs.
677 // The code in this module only supports dual-channel operation,
678 // so we test that compatible DIMMs are paired.
680 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
683 uint8_t dimm_mask = 0;
685 // Have to increase size of dimm_mask if this assertion is violated
686 ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
688 // Find DIMMs we can support on channel 0.
689 // Then see if the corresponding channel 1 DIMM has the same parameters,
690 // since we only support dual-channel.
692 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
694 uint16_t channel0_dimm = ctrl->channel0[i];
695 uint16_t channel1_dimm = ctrl->channel1[i];
696 uint8_t bDualChannel = 1;
697 struct dimm_size page_size;
698 struct dimm_size sdram_width;
702 if (channel0_dimm == 0)
703 continue; // No such socket on this mainboard
705 if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
708 #ifdef VALIDATE_DIMM_COMPATIBILITY
709 if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2)
710 continue; // Unsupported voltage
712 // E7501 does not support unregistered DIMMs
713 spd_value = spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
714 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
717 // Must support burst = 4 for dual-channel operation on E7501
718 // NOTE: for single-channel, burst = 8 is required
719 spd_value = spd_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS);
720 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
723 page_size = sdram_spd_get_page_size(channel0_dimm);
724 sdram_width = sdram_spd_get_width(channel0_dimm);
726 // Validate DIMM page size
727 // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
728 // NOTE: 4 KB = 32 Kb = 2^15
729 // 32 KB = 262 Kb = 2^18
731 if ((page_size.side1 < 15) || (page_size.side1 > 18))
734 // If DIMM is double-sided, verify side2 page size
735 if (page_size.side2 != 0) {
736 if ((page_size.side2 < 15) || (page_size.side2 > 18))
740 // Validate SDRAM width
741 // The E7501 only supports x4 and x8 devices
743 if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
746 // If DIMM is double-sided, verify side2 width
747 if (sdram_width.side2 != 0) {
748 if ((sdram_width.side2 != 4) && (sdram_width.side2 != 8))
752 // Channel 0 DIMM looks compatible.
753 // Now see if it is paired with the proper DIMM on channel 1.
755 ASSERT(channel1_dimm != 0); // No such socket on this mainboard??
757 // NOTE: unpopulated DIMMs cause read to fail
758 spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
759 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
761 print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
765 #ifdef VALIDATE_DIMM_COMPATIBILITY
766 spd_value = spd_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS);
767 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
770 for (j=0; j<sizeof(dual_channel_parameters); ++j) {
771 if (!are_spd_values_equal(dual_channel_parameters[j], channel0_dimm, channel1_dimm)) {
779 // Code around ROMCC bug in optimization of "if" statements
780 #ifdef ROMCC_IF_BUG_FIXED
782 // Made it through all the checks, this DIMM pair is usable
783 dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
786 print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
788 switch (bDualChannel) {
790 print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
794 // Made it through all the checks, this DIMM pair is usable
795 dimm_mask |= (1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i));
804 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
805 /* SPD (SERIAL PRESENCE DETECT) FUNCTIONS */
806 /**********************************************************************************/
808 //----------------------------------------------------------------------------------
809 // Function: do_ram_command
811 // command - specifies the command to be sent to the DIMMs:
812 // RAM_COMMAND_NOP - No Operation
813 // RAM_COMMAND_PRECHARGE - Precharge all banks
814 // RAM_COMMAND_MRS - Load Mode Register
815 // RAM_COMMAND_EMRS - Load Extended Mode Register
816 // RAM_COMMAND_CBR - Auto Refresh ("CAS-before-RAS")
817 // RAM_COMMAND_NORMAL - Normal operation
818 // jedec_mode_bits - for mode register set & extended mode register set
819 // commands, bits 0-12 contain the register value in JEDEC format.
820 // Return Value: None
821 // Description: Send the specified command to all DIMMs.
823 static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
826 uint32_t dram_controller_mode;
827 uint8_t dimm_start_64M_multiple = 0;
828 uint16_t e7501_mode_bits = jedec_mode_bits;
830 // Configure the RAM command
831 dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
832 dram_controller_mode &= 0xFFFFFF8F;
833 dram_controller_mode |= command;
834 pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
836 // RAM_COMMAND_NORMAL is an exception.
837 // It affects only the memory controller and does not need to be "sent" to the DIMMs.
839 if (command != RAM_COMMAND_NORMAL) {
841 // Send the command to all DIMMs by accessing a memory location within each
842 // NOTE: for mode select commands, some of the location address bits
843 // are part of the command
845 // Map JEDEC mode bits to E7501
846 if (command == RAM_COMMAND_MRS) {
847 // Host address lines [15:5] map to DIMM address lines [12:11, 9:1]
848 // The E7501 hard-sets DIMM address lines 10 & 0 to zero
850 ASSERT(!(jedec_mode_bits & 0x0401));
852 e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15-12)) | // JEDEC bits 11-12 move to bits 14-15
853 ((jedec_mode_bits & 0x03FE) << (13-9)); // JEDEC bits 1-9 move to bits 5-13
855 } else if (command == RAM_COMMAND_EMRS) {
856 // Host address lines [15:3] map to DIMM address lines [12:0]
857 e7501_mode_bits = jedec_mode_bits <<= 3;
859 ASSERT(jedec_mode_bits == 0);
862 dimm_start_64M_multiple = 0;
864 for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
866 uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
867 if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
869 // This code assumes DRAM row boundaries are all set below 4 GB
870 // NOTE: 0x40 * 64 MB == 4 GB
871 ASSERT(dimm_start_64M_multiple < 0x40);
873 // NOTE: 2^26 == 64 MB
875 uint32_t dimm_start_address = dimm_start_64M_multiple << 26;
877 RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
878 RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
879 RAM_DEBUG_MESSAGE("\r\n");
880 read32(dimm_start_address + e7501_mode_bits);
882 // Set the start of the next DIMM
883 dimm_start_64M_multiple = dimm_end_64M_multiple;
889 //----------------------------------------------------------------------------------
890 // Function: set_ram_mode
891 // Parameters: jedec_mode_bits - for mode register set & extended mode register set
892 // commands, bits 0-12 contain the register value in JEDEC format.
893 // Return Value: None
894 // Description: Set the mode register of all DIMMs. The proper CAS# latency
895 // setting is added to the mode bits specified by the caller.
897 static void set_ram_mode(uint16_t jedec_mode_bits)
899 ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
901 uint32_t dram_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
903 switch (dram_cas_latency) {
905 jedec_mode_bits |= SDRAM_CAS_2_5;
909 jedec_mode_bits |= SDRAM_CAS_2_0;
917 do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
920 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
921 /* SDRAM CONFIGURATION FUNCTIONS */
922 /**********************************************************************************/
924 //----------------------------------------------------------------------------------
925 // Function: configure_dimm_row_boundaries
927 // dimm_log2_num_bits - log2(number of bits) for each side of the DIMM
928 // total_dram_64M_multiple - total DRAM in the system (as a
929 // multiple of 64 MB) for DIMMs < dimm_index
930 // dimm_index - which DIMM pair is being processed
931 // (0..MAX_DIMM_SOCKETS_PER_CHANNEL)
932 // Return Value: New multiple of 64 MB total DRAM in the system
933 // Description: Configure the E7501's DRAM Row Boundary registers for the memory
934 // present in the specified DIMM.
936 static uint8_t configure_dimm_row_boundaries(
937 struct dimm_size dimm_log2_num_bits,
938 uint8_t total_dram_64M_multiple,
943 ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
945 // DIMM sides must be at least 32 MB
946 ASSERT(dimm_log2_num_bits.side1 >= 28);
947 ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28));
949 // In dual-channel mode, we are called only once for each pair of DIMMs.
950 // Each time we process twice the capacity of a single DIMM.
952 // Convert single DIMM capacity to paired DIMM capacity
953 // (multiply by two ==> add 1 to log2)
954 dimm_log2_num_bits.side1++;
955 if (dimm_log2_num_bits.side2 > 0)
956 dimm_log2_num_bits.side2++;
958 // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
959 // to the total capacity of the system
960 // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
962 total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
964 // Configure the boundary address for the row on side 1
965 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple);
967 // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
968 // (as a multiple of 64 MB) to the total capacity of the system
969 if (dimm_log2_num_bits.side2 >= 29)
970 total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side2 - 29));
972 // Configure the boundary address for the row (if any) on side 2
973 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple);
975 // Update boundaries for rows subsequent to these.
976 // These settings will be overridden by a subsequent call if a populated physical slot exists
978 for(i=dimm_index+1; i<MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
979 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(i<<1), total_dram_64M_multiple);
980 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(i<<1), total_dram_64M_multiple);
983 return total_dram_64M_multiple;
986 //----------------------------------------------------------------------------------
987 // Function: configure_e7501_ram_addresses
988 // Parameters: ctrl - PCI addresses of memory controller functions, and
989 // SMBus addresses of DIMM slots on the mainboard
990 // dimm_mask - bitmask of populated DIMMs on the board - see
991 // spd_get_supported_dimms()
992 // Return Value: None
993 // Description: Program the E7501's DRAM row boundary addresses and its Top Of
994 // Low Memory (TOLM). If necessary, set up a remap window so we
995 // don't waste DRAM that ordinarily would lie behind addresses
996 // reserved for memory-mapped I/O.
998 static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
1002 uint8_t total_dram_64M_multiple = 0;
1004 // Configure the E7501's DRAM row boundaries
1005 // Start by zeroing out the temporary initial configuration
1006 pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0);
1007 pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0);
1009 for(i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1011 uint16_t dimm_socket_address = ctrl->channel0[i];
1012 struct dimm_size sz;
1014 if (!(dimm_mask & (1 << i)))
1015 continue; // This DIMM not present
1017 sz = spd_get_dimm_size(dimm_socket_address);
1019 RAM_DEBUG_MESSAGE("dimm size =");
1020 RAM_DEBUG_HEX32(sz.side1);
1021 RAM_DEBUG_MESSAGE(" ");
1022 RAM_DEBUG_HEX32(sz.side2);
1023 RAM_DEBUG_MESSAGE("\r\n");
1026 die("Bad SPD value\r\n");
1028 total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
1031 // Configure the Top Of Low Memory (TOLM) in the E7501
1032 // This address must be a multiple of 128 MB that is less than 4 GB.
1033 // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
1034 // in the highest 5 bits.
1036 // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
1037 // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
1038 // such as flash and memory-mapped I/O.
1040 // If there is more than 3 GB of DRAM, we define a remap window which
1041 // makes the DRAM "behind" the reserved region available above the top of physical
1044 // NOTE: 0xC0000000 / (64 MB) == 0x30
1046 if (total_dram_64M_multiple <= 0x30) {
1048 // <= 3 GB total RAM
1050 /* I should really adjust all of this in C after I have resources
1051 * to all of the pci devices.
1054 // Round up to 128MB granularity
1055 // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
1057 uint8_t total_dram_128M_multiple = (total_dram_64M_multiple + 1) >> 1;
1059 // Convert to high 16 bits of address
1060 uint16_t top_of_low_memory = total_dram_128M_multiple << 11;
1062 pci_write_config16(PCI_DEV(0, 0, 0), TOLM, top_of_low_memory);
1068 // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
1069 uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0
1070 uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF
1074 pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000);
1076 // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
1077 // visible just beyond 4 GB or the end of physical memory, whichever is larger
1078 // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
1079 // (i.e. a multiple of 64 MB) in the lowest 10 bits.
1080 // NOTE: 0x100000000 / (64 MB) == 0x40
1082 if (total_dram_64M_multiple < 0x40) {
1083 remap_base = 0x40; // 0x100000000
1084 remap_limit = 0x40 + (total_dram_64M_multiple - 0x30) - 1;
1087 pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, remap_base);
1088 pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, remap_limit);
1092 //----------------------------------------------------------------------------------
1093 // Function: initialize_ecc
1095 // Return Value: None
1096 // Description: If we're configured to use ECC, initialize the SDRAM and
1097 // clear the E7501's ECC error flags.
1099 static void initialize_ecc(void)
1101 uint32_t dram_controller_mode;
1103 /* Test to see if ECC support is enabled */
1104 dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1105 dram_controller_mode >>= 20;
1106 dram_controller_mode &= 3;
1107 if (dram_controller_mode == 2) {
1111 RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n");
1112 /* Initialize ECC bits , use ECC zero mode (new to 7501)*/
1113 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
1114 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
1116 // Wait for scrub cycle to complete
1118 byte = pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
1120 } while ( (byte & 0x08 ) == 0);
1122 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
1123 RAM_DEBUG_MESSAGE("ECC state initialized.\r\n");
1125 /* Clear the ECC error bits */
1126 pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
1127 pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03);
1129 // Clear DRAM Interface error bits (write-one-clear)
1130 pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1<<18);
1131 pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1<<18);
1133 // Start normal ECC scrub
1134 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5);
1139 //----------------------------------------------------------------------------------
1140 // Function: configure_e7501_dram_timing
1141 // Parameters: ctrl - PCI addresses of memory controller functions, and
1142 // SMBus addresses of DIMM slots on the mainboard
1143 // dimm_mask - bitmask of populated DIMMs on the board - see
1144 // spd_get_supported_dimms()
1145 // Return Value: None
1146 // Description: Program the DRAM Timing register of the E7501 (except for CAS#
1147 // latency, which is assumed to have been programmed already), based
1148 // on the parameters of the various installed DIMMs.
1150 static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask)
1153 uint32_t dram_timing;
1155 uint8_t slowest_row_precharge = 0;
1156 uint8_t slowest_ras_cas_delay = 0;
1157 uint8_t slowest_active_to_precharge_delay = 0;
1158 uint32_t current_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
1160 // CAS# latency must be programmed beforehand
1161 ASSERT((current_cas_latency == DRT_CAS_2_0) || (current_cas_latency == DRT_CAS_2_5));
1163 // Each timing parameter is determined by the slowest DIMM
1165 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1167 uint16_t dimm_socket_address;
1169 if (!(dimm_mask & (1 << i)))
1170 continue; // This DIMM not present
1172 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1173 dimm_socket_address = ctrl->channel0[i];
1175 dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1177 value = spd_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME);
1178 if (value < 0) goto hw_err;
1179 if (value > slowest_row_precharge)
1180 slowest_row_precharge = value;
1182 value = spd_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY);
1183 if(value < 0 ) goto hw_err;
1184 if (value > slowest_ras_cas_delay)
1185 slowest_ras_cas_delay = value;
1187 value = spd_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
1188 if(value < 0 ) goto hw_err;
1189 if (value > slowest_active_to_precharge_delay)
1190 slowest_active_to_precharge_delay = value;
1193 // NOTE for timing parameters:
1194 // At 133 MHz, 1 clock == 7.52 ns
1196 /* Read the initial state */
1197 dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
1201 // E7501 supports only 2 or 3 clocks for tRP
1202 if (slowest_row_precharge > ((22<<2) | (2<<0)))
1203 die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks
1204 else if (slowest_row_precharge > (15<<2))
1205 dram_timing &= ~(1<<0); // > 15.0 ns: 3 clocks
1207 dram_timing |= (1<<0); // <= 15.0 ns: 2 clocks
1211 // E7501 supports only 2 or 3 clocks for tRCD
1212 // Use the same value for both read & write
1213 dram_timing &= ~((1<<3)|(3<<1));
1214 if (slowest_ras_cas_delay > ((22<<2) | (2<<0)))
1215 die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks
1216 else if (slowest_ras_cas_delay > (15<<2))
1217 dram_timing |= (2<<1); // > 15.0 ns: 3 clocks
1219 dram_timing |= ((1<<3) | (3<<1)); // <= 15.0 ns: 2 clocks
1223 // E7501 supports only 5, 6, or 7 clocks for tRAS
1224 // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
1225 dram_timing &= ~(3<<9);
1227 if (slowest_active_to_precharge_delay > 52)
1228 die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks
1229 else if (slowest_active_to_precharge_delay > 45)
1230 dram_timing |= (0<<9); // 46-52 ns: 7 clocks
1231 else if (slowest_active_to_precharge_delay > 37)
1232 dram_timing |= (1<<9); // 38-45 ns: 6 clocks
1234 dram_timing |= (2<<9); // < 38 ns: 5 clocks
1239 /* Set to a 7 clock read delay. This is for 133Mhz
1240 * with a CAS latency of 2.5 if 2.0 a 6 clock
1243 dram_timing &= ~(7<<24); // 7 clocks
1244 if (current_cas_latency == DRT_CAS_2_0)
1245 dram_timing |= (1<<24); // 6 clocks
1248 * Back to Back Read-Write Turn Around
1250 /* Set to a 5 clock back to back read to write turn around.
1251 * 4 is a good delay if the CAS latency is 2.0 */
1253 dram_timing &= ~(1<<28); // 5 clocks
1254 if (current_cas_latency == DRT_CAS_2_0)
1255 dram_timing |= (1<<28); // 4 clocks
1257 pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
1265 //----------------------------------------------------------------------------------
1266 // Function: configure_e7501_cas_latency
1267 // Parameters: ctrl - PCI addresses of memory controller functions, and
1268 // SMBus addresses of DIMM slots on the mainboard
1269 // dimm_mask - bitmask of populated DIMMs on the board - see
1270 // spd_get_supported_dimms()
1271 // Return Value: None
1272 // Description: Determine the shortest CAS# latency that the E7501 and all DIMMs
1273 // have in common, and program the E7501 to use it.
1275 static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8_t dimm_mask)
1279 uint32_t dram_timing;
1280 uint16_t maybe_dram_read_timing;
1283 // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
1284 // NOTE: E7501 supports only 2.0 and 2.5
1285 uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
1286 uint32_t current_cas_latency;
1287 uint32_t dimm_compatible_cas_latencies;
1289 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1291 uint16_t dimm_socket_address;
1293 if (!(dimm_mask & (1 << i)))
1294 continue; // This DIMM not usable
1296 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1297 dimm_socket_address = ctrl->channel0[i];
1299 dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1301 value = spd_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES);
1302 if (value < 0) goto hw_err;
1304 dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM
1305 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
1307 // Can we support the highest CAS# latency?
1309 value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
1310 if (value < 0) goto hw_err;
1312 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1314 // Our bus is too fast for this CAS# latency
1315 // Remove it from the bitmask of those supported by the DIMM that are compatible
1316 dimm_compatible_cas_latencies &= ~current_cas_latency;
1319 // Can we support the next-highest CAS# latency (max - 0.5)?
1321 current_cas_latency >>= 1;
1322 if (current_cas_latency != 0) {
1323 value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND);
1324 if(value < 0 ) goto hw_err;
1326 dimm_compatible_cas_latencies &= ~current_cas_latency;
1329 // Can we support the next-highest CAS# latency (max - 1.0)?
1330 current_cas_latency >>= 1;
1331 if (current_cas_latency != 0) {
1332 value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD);
1333 if(value < 0 ) goto hw_err;
1335 dimm_compatible_cas_latencies &= ~current_cas_latency;
1338 // Restrict the system to CAS# latencies compatible with this DIMM
1339 system_compatible_cas_latencies &= dimm_compatible_cas_latencies;
1341 /* go to the next DIMM */
1344 /* After all of the arduous calculation setup with the fastest
1345 * cas latency I can use.
1348 dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
1349 dram_timing &= ~(DRT_CAS_MASK);
1351 maybe_dram_read_timing = pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
1352 maybe_dram_read_timing &= 0xF00C;
1354 if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
1355 dram_timing |= DRT_CAS_2_0;
1356 maybe_dram_read_timing |= 0xBB1;
1358 else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
1360 uint32_t dram_row_attributes = pci_read_config32(PCI_DEV(0, 0, 0), DRA);
1362 dram_timing |= DRT_CAS_2_5;
1364 // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
1365 // different value if all DIMM slots are populated
1367 if ((dram_row_attributes & 0xff) && (dram_row_attributes & 0xff00) &&
1368 (dram_row_attributes & 0xff0000) && (dram_row_attributes & 0xff000000)) {
1370 // All slots populated
1371 maybe_dram_read_timing |= 0x0882;
1374 // Some unpopulated slots
1375 maybe_dram_read_timing |= 0x0662;
1379 die("No CAS# latencies compatible with all DIMMs!!\r\n");
1381 pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
1383 /* set master DLL reset */
1384 dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
1386 pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1388 dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */
1389 dword |= 0xd2109800;
1391 pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1394 pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, maybe_dram_read_timing);
1396 dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */
1398 pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1406 //----------------------------------------------------------------------------------
1407 // Function: configure_e7501_dram_controller_mode
1408 // Parameters: ctrl - PCI addresses of memory controller functions, and
1409 // SMBus addresses of DIMM slots on the mainboard
1410 // dimm_mask - bitmask of populated DIMMs on the board - see
1411 // spd_get_supported_dimms()
1412 // Return Value: None
1413 // Description: Configure the refresh interval so that we refresh no more often
1414 // than required by the "most needy" DIMM. Also disable ECC if any
1415 // of the DIMMs don't support it.
1417 static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl,
1423 uint32_t controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1424 uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
1426 // Code below assumes that most aggressive settings are in
1427 // force when we are called, either via E7501 reset defaults
1428 // or by sdram_set_registers():
1432 ASSERT((controller_mode & (3<<20)) == (2<<20)); // ECC
1433 ASSERT(!(controller_mode & (7 << 8))); // Refresh
1435 /* Walk through _all_ dimms and find the least-common denominator for:
1440 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1442 uint32_t dimm_refresh_mode;
1444 uint16_t dimm_socket_address;
1446 if (!(dimm_mask & (1 << i))) {
1447 continue; // This DIMM not usable
1450 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1451 dimm_socket_address = ctrl->channel0[i];
1453 dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1455 // Disable ECC mode if any one of the DIMMs does not support ECC
1456 // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
1458 value = spd_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE);
1459 die_on_spd_error(value);
1460 if (value != ERROR_SCHEME_ECC) {
1461 controller_mode &= ~(3 << 20);
1464 value = spd_read_byte(dimm_socket_address, SPD_REFRESH);
1465 die_on_spd_error(value);
1466 value &= 0x7f; // Mask off self-refresh bit
1467 if(value > MAX_SPD_REFRESH_RATE) {
1468 print_err("unsupported refresh rate\r\n");
1472 // Get the appropriate E7501 refresh mode for this DIMM
1473 dimm_refresh_mode = refresh_rate_map[value];
1474 if (dimm_refresh_mode > 7) {
1475 print_err("unsupported refresh rate\r\n");
1479 // If this DIMM requires more frequent refresh than others,
1480 // update the system setting
1481 if (refresh_frequency[dimm_refresh_mode] > refresh_frequency[system_refresh_mode])
1482 system_refresh_mode = dimm_refresh_mode;
1484 #ifdef SUSPICIOUS_LOOKING_CODE
1485 // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
1486 // than the clock period of the memory controller. Also, no other northbridge
1487 // looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
1489 // Switch to 2 clocks for address/command if required by any one of the DIMMs
1490 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1491 value = spd_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
1492 die_on_spd_error(value);
1493 if(value >= 0xa0) { /* At 133MHz this constant should be 0x75 */
1494 controller_mode &= ~(1<<16); /* Use two clock cyles instead of one */
1498 /* go to the next DIMM */
1501 controller_mode |= (system_refresh_mode << 8);
1503 // Configure the E7501
1504 pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode);
1507 //----------------------------------------------------------------------------------
1508 // Function: configure_e7501_row_attributes
1509 // Parameters: ctrl - PCI addresses of memory controller functions, and
1510 // SMBus addresses of DIMM slots on the mainboard
1511 // dimm_mask - bitmask of populated DIMMs on the board - see
1512 // spd_get_supported_dimms()
1513 // Return Value: None
1514 // Description: Configure the E7501's DRAM Row Attributes (DRA) registers
1515 // based on DIMM parameters read via SPD. This tells the controller
1516 // the width of the SDRAM chips on each DIMM side (x4 or x8) and
1517 // the page size of each DIMM side (4, 8, 16, or 32 KB).
1519 static void configure_e7501_row_attributes(const struct mem_controller *ctrl,
1523 uint32_t row_attributes = 0;
1525 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1527 uint16_t dimm_socket_address = ctrl->channel0[i];
1528 struct dimm_size page_size;
1529 struct dimm_size sdram_width;
1531 if (!(dimm_mask & (1 << i)))
1532 continue; // This DIMM not usable
1534 // Get the relevant parameters via SPD
1535 page_size = sdram_spd_get_page_size(dimm_socket_address);
1536 sdram_width = sdram_spd_get_width(dimm_socket_address);
1538 // Update the DRAM Row Attributes.
1539 // Page size is encoded as log2(page size in bits) - log2(8 Kb)
1540 // NOTE: 8 Kb = 2^13
1541 row_attributes |= (page_size.side1 - 13) << (i<<3); // Side 1 of each DIMM is an EVEN row
1543 if (sdram_width.side2 > 0)
1544 row_attributes |= (page_size.side2 - 13) << ((i<<3) + 4); // Side 2 is ODD
1546 // Set x4 flags if appropriate
1547 if (sdram_width.side1 == 4) {
1548 row_attributes |= 0x08 << (i<<3);
1551 if (sdram_width.side2 == 4) {
1552 row_attributes |= 0x08 << ((i<<3) + 4);
1555 /* go to the next DIMM */
1558 /* Write the new row attributes register */
1559 pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes);
1562 //----------------------------------------------------------------------------------
1563 // Function: enable_e7501_clocks
1564 // Parameters: dimm_mask - bitmask of populated DIMMs on the board - see
1565 // spd_get_supported_dimms()
1566 // Return Value: None
1567 // Description: Enable clock signals for populated DIMM sockets and disable them
1568 // for unpopulated sockets (to reduce EMI).
1570 static void enable_e7501_clocks(uint8_t dimm_mask)
1573 uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
1575 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1577 uint8_t socket_mask = 1 << i;
1579 if (dimm_mask & socket_mask)
1580 clock_disable &= ~socket_mask; // DIMM present, enable clock
1582 clock_disable |= socket_mask; // DIMM absent, disable clock
1585 pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable);
1589 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1590 /* DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS */
1591 /**********************************************************************************/
1593 //----------------------------------------------------------------------------------
1594 // Function: RAM_RESET_DDR_PTR
1595 // Parameters: ctrl - PCI addresses of memory controller functions, and
1596 // SMBus addresses of DIMM slots on the mainboard
1597 // Return Value: None
1598 // Description: DDR Receive FIFO RE-Sync (?)
1600 static void RAM_RESET_DDR_PTR(void)
1603 byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
1605 pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
1607 byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
1609 pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
1612 //----------------------------------------------------------------------------------
1613 // Function: ram_set_d0f0_regs
1615 // Return Value: None
1616 // Description: Set E7501 registers that are either independent of DIMM specifics,
1617 // or establish default settings that will be overridden when we
1618 // learn the specifics.
1619 // This sets PCI configuration registers to known good values based
1620 // on the table 'constant_register_values', which are a triple of
1621 // configuration register offset, mask, and bits to set.
1623 static void ram_set_d0f0_regs(void)
1626 int num_values = ARRAY_SIZE(constant_register_values);
1628 ASSERT((num_values % 3) == 0); // Bad table?
1630 for(i = 0; i < num_values; i += 3) {
1632 uint32_t register_offset = constant_register_values[i];
1633 uint32_t bits_to_mask = constant_register_values[i+1];
1634 uint32_t bits_to_set = constant_register_values[i+2];
1635 uint32_t register_value;
1637 // It's theoretically possible to set values for something other than D0:F0,
1638 // but it's not typically done here
1639 ASSERT(!(register_offset & 0xFFFFFF00));
1641 // bits_to_mask and bits_to_set should not reference the same bits
1642 // Again, not strictly an error, but flagged as a potential bug
1643 ASSERT((bits_to_mask & bits_to_set) == 0);
1645 register_value = pci_read_config32(PCI_DEV(0, 0, 0), register_offset);
1646 register_value &= bits_to_mask;
1647 register_value |= bits_to_set;
1649 pci_write_config32(PCI_DEV(0, 0, 0), register_offset, register_value);
1653 //----------------------------------------------------------------------------------
1654 // Function: write_8dwords
1655 // Parameters: src_addr
1657 // Return Value: None
1658 // Description: Copy 64 bytes from one location to another.
1660 static void write_8dwords(uint32_t* src_addr, uint32_t dst_addr)
1663 for (i=0; i<8; i++) {
1664 write32(dst_addr, *src_addr);
1666 dst_addr += sizeof(uint32_t);
1670 //----------------------------------------------------------------------------------
1671 // Function: ram_set_rcomp_regs
1673 // Return Value: None
1674 // Description: Set the E7501's (undocumented) RCOMP registers.
1675 // Per the 855PM datasheet and IXP2800 HW Initialization Reference
1676 // Manual, RCOMP registers appear to affect drive strength,
1677 // pullup/pulldown offset, and slew rate of various signal groups.
1678 // Comments below are conjecture based on apparent similarity
1679 // between the E7501 and these two chips.
1681 static void ram_set_rcomp_regs(void)
1684 uint8_t maybe_strength_control;
1686 RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n");
1688 /*enable access to the rcomp bar*/
1689 dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
1691 pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
1694 // Set the RCOMP MMIO base address
1695 pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
1697 // Block RCOMP updates while we configure the registers
1698 dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1700 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1703 /* Begin to write the RCOMP registers */
1705 // Set CMD and DQ/DQS strength to 2x (?)
1706 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
1707 maybe_strength_control |= 0x44;
1708 write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
1710 write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
1711 write16(RCOMP_MMIO + 0x42, 0);
1713 write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
1715 // NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
1716 write16(RCOMP_MMIO + 0x40, 0);
1719 // Set RCVEnOut# strength to 2x (?)
1720 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
1721 maybe_strength_control |= 4;
1722 write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
1724 write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
1725 write16(RCOMP_MMIO + 0x50, 0);
1727 // Set CS# strength for x4 SDRAM to 2x (?)
1728 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
1729 maybe_strength_control |= 4;
1730 write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
1732 write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
1733 write16(RCOMP_MMIO + 0x48, 0);
1735 // Set CKE strength for x4 SDRAM to 2x (?)
1736 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
1737 maybe_strength_control |= 4;
1738 write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
1740 write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
1741 write16(RCOMP_MMIO + 0x44, 0);
1743 // Set CK strength for x4 SDRAM to 1x (?)
1744 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
1745 maybe_strength_control |= 1;
1746 write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
1748 write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
1749 write16(RCOMP_MMIO + 0x4c, 0);
1751 write8(RCOMP_MMIO + 0x2c, 0xff);
1754 // Set the digital filter length to 8 (?)
1755 dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1757 // NOTE: Some factory BIOS don't do this.
1758 // Doesn't seem to matter either way.
1762 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1767 /* unblock updates */
1768 dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1770 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1772 // Force a RCOMP measurement cycle?
1774 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1776 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1781 /*disable access to the rcomp bar */
1782 dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
1784 pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
1788 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1789 /* DIMM-INDEPENDENT CONFIGURATION FUNCTIONS */
1790 /**********************************************************************************/
1792 //----------------------------------------------------------------------------------
1793 // Function: sdram_enable
1794 // Parameters: controllers - not used
1795 // ctrl - PCI addresses of memory controller functions, and
1796 // SMBus addresses of DIMM slots on the mainboard
1797 // Return Value: None
1798 // Description: Go through the JEDEC initialization sequence for all DIMMs,
1799 // then enable refresh and initialize ECC and memory to zero.
1800 // Upon exit, SDRAM is up and running.
1802 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1804 uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD);
1805 uint32_t dram_controller_mode;
1810 /* 1 & 2 Power up and start clocks */
1811 RAM_DEBUG_MESSAGE("Ram Enable 1\r\n");
1812 RAM_DEBUG_MESSAGE("Ram Enable 2\r\n");
1814 /* A 200us delay is needed */
1820 RAM_DEBUG_MESSAGE("Ram Enable 3\r\n");
1821 do_ram_command(RAM_COMMAND_NOP, 0);
1824 /* 4 Precharge all */
1825 RAM_DEBUG_MESSAGE("Ram Enable 4\r\n");
1826 do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1829 /* wait until the all banks idle state... */
1830 /* 5. Issue EMRS to enable DLL */
1831 RAM_DEBUG_MESSAGE("Ram Enable 5\r\n");
1832 do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
1836 RAM_DEBUG_MESSAGE("Ram Enable 6\r\n");
1837 set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
1840 /* Ensure a 200us delay between the DLL reset in step 6 and the final
1841 * mode register set in step 9.
1842 * Infineon needs this before any other command is sent to the ram.
1847 /* 7 Precharge all */
1848 RAM_DEBUG_MESSAGE("Ram Enable 7\r\n");
1849 do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1852 /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1853 RAM_DEBUG_MESSAGE("Ram Enable 8\r\n");
1854 do_ram_command(RAM_COMMAND_CBR, 0);
1856 do_ram_command(RAM_COMMAND_CBR, 0);
1858 /* And for good luck 6 more CBRs */
1859 do_ram_command(RAM_COMMAND_CBR, 0);
1861 do_ram_command(RAM_COMMAND_CBR, 0);
1863 do_ram_command(RAM_COMMAND_CBR, 0);
1865 do_ram_command(RAM_COMMAND_CBR, 0);
1867 do_ram_command(RAM_COMMAND_CBR, 0);
1869 do_ram_command(RAM_COMMAND_CBR, 0);
1872 /* 9 mode register set */
1873 RAM_DEBUG_MESSAGE("Ram Enable 9\r\n");
1874 set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
1877 /* 10 DDR Receive FIFO RE-Sync */
1878 RAM_DEBUG_MESSAGE("Ram Enable 10\r\n");
1879 RAM_RESET_DDR_PTR();
1882 /* 11 normal operation */
1883 RAM_DEBUG_MESSAGE("Ram Enable 11\r\n");
1884 do_ram_command(RAM_COMMAND_NORMAL, 0);
1887 // Reconfigure the row boundaries and Top of Low Memory
1888 // to match the true size of the DIMMs
1889 configure_e7501_ram_addresses(ctrl, dimm_mask);
1891 /* Finally enable refresh */
1892 dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1893 dram_controller_mode |= (1 << 29);
1894 pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
1899 dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */
1900 dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit
1901 pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
1903 RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n");
1909 //----------------------------------------------------------------------------------
1910 // Function: sdram_set_spd_registers
1911 // Parameters: ctrl - PCI addresses of memory controller functions, and
1912 // SMBus addresses of DIMM slots on the mainboard
1913 // Return Value: None
1914 // Description: Configure SDRAM controller parameters that depend on
1915 // characteristics of the DIMMs installed in the system. These
1916 // characteristics are read from the DIMMs via the standard Serial
1917 // Presence Detect (SPD) interface.
1919 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
1923 RAM_DEBUG_MESSAGE("Reading SPD data...\r\n");
1925 //activate_spd_rom(ctrl); Not necessary for this chipset
1927 dimm_mask = spd_get_supported_dimms(ctrl);
1929 if (dimm_mask == 0) {
1930 print_debug("No usable memory for this controller\r\n");
1933 enable_e7501_clocks(dimm_mask);
1935 RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n");
1937 configure_e7501_row_attributes(ctrl, dimm_mask);
1938 configure_e7501_dram_controller_mode(ctrl, dimm_mask);
1939 configure_e7501_cas_latency(ctrl, dimm_mask);
1940 RAM_RESET_DDR_PTR();
1942 configure_e7501_dram_timing(ctrl, dimm_mask);
1944 RAM_DEBUG_MESSAGE("done\r\n");
1947 // NOTE: configure_e7501_ram_addresses() is NOT called here.
1948 // We want to keep the default 64 MB/row mapping until sdram_enable() is called,
1949 // even though the default mapping is almost certainly incorrect.
1950 // The default mapping makes it easy to initialize all of the DIMMs
1951 // even if the total system memory is > 4 GB.
1953 // Save the dimm_mask for when sdram_enable is called, so it can call
1954 // configure_e7501_ram_addresses() without having to regenerate the bitmask
1956 pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask);
1959 //----------------------------------------------------------------------------------
1960 // Function: sdram_set_registers
1961 // Parameters: ctrl - PCI addresses of memory controller functions, and
1962 // SMBus addresses of DIMM slots on the mainboard
1963 // Return Value: None
1964 // Description: Do basic ram setup that does NOT depend on serial presence detect
1965 // information (i.e. independent of DIMM specifics).
1967 static void sdram_set_registers(const struct mem_controller *ctrl)
1969 RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n");
1972 ram_set_rcomp_regs();
1973 ram_set_d0f0_regs();
1976 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1977 /* PUBLIC INTERFACE */
1978 /**********************************************************************************/