1 /* This was originally for the e7500, modified for e7501
2 * The primary differences are that 7501 apparently can
3 * support single channel RAM (i haven't tested),
4 * CAS1.5 is no longer supported, The ECC scrubber
5 * now supports a mode to zero RAM and init ECC in one step
6 * and the undocumented registers at 0x80 require new
7 * (undocumented) values determined by guesswork and
8 * comparison w/ OEM BIOS values.
9 * Steven James 02/06/2003
12 /* converted to C 6/2004 yhlu */
16 #include <sdram_mode.h>
19 // Uncomment this to enable run-time checking of DIMM parameters
20 // for dual-channel operation
21 // Unfortunately the code seems to chew up several K of space.
22 //#define VALIDATE_DIMM_COMPATIBILITY
24 // Uncomment this to enable local debugging messages
25 //#define DEBUG_RAM_CONFIG
27 #if defined(DEBUG_RAM_CONFIG)
28 #define RAM_DEBUG_MESSAGE(x) print_debug(x)
29 #define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
30 #define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
31 #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
33 #define RAM_DEBUG_MESSAGE(x)
34 #define RAM_DEBUG_HEX32(x)
35 #define RAM_DEBUG_HEX8(x)
39 #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
40 #define SPD_ERROR "Error reading SPD info\r\n"
42 // NOTE: This used to be 0x100000.
43 // That doesn't work on systems where A20M# is asserted, because
44 // attempts to access 0x1000NN end up accessing 0x0000NN.
45 #define RCOMP_MMIO 0x200000
52 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
54 /**********************************************************************************/
56 static const uint32_t refresh_frequency[]= {
57 /* Relative frequency (array value) of each E7501 Refresh Mode Select
58 * (RMS) value (array index)
59 * 0 == least frequent refresh (longest interval between refreshes)
69 0, 2, 3, 1, 0, 0, 0, 4 };
71 static const uint32_t refresh_rate_map[] = {
72 /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
73 * Select values (array value)
74 * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
75 * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
76 * 64 clock (481 ns) (7) refresh.
77 * [0] == 15.625 us -> 15.6 us
78 * [1] == 3.9 us -> 481 ns
79 * [2] == 7.8 us -> 7.8 us
80 * [3] == 31.3 us -> 15.6 us
81 * [4] == 62.5 us -> 15.6 us
82 * [5] == 125 us -> 64 us
86 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
89 // SPD parameters that must match for dual-channel operation
90 static const uint8_t dual_channel_parameters[] = {
96 SPD_PRIMARY_DRAM_WIDTH,
97 SPD_NUM_BANKS_PER_DRAM
101 * Table: constant_register_values
103 static const long constant_register_values[] = {
104 /* SVID - Subsystem Vendor Identification Register
106 * [15:00] Subsytem Vendor ID (Indicates system board vendor)
108 /* SID - Subsystem Identification Register
110 * [15:00] Subsystem ID
112 // Not everyone wants to be Super Micro Computer, Inc.
113 // The mainboard should set this if desired.
114 // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
117 * (DRAM Read Timing Control, if similar to 855PM?)
119 * This register has something to do with CAS latencies,
120 * possibily this is the real chipset control.
121 * At 0x00 CAS latency 1.5 works.
122 * At 0x06 CAS latency 2.5 works.
123 * At 0x01 CAS latency 2.0 works.
125 /* This is still undocumented in e7501, but with different values
126 * CAS 2.0 values taken from Intel BIOS settings, others are a guess
127 * and may be terribly wrong. Old values preserved as comments until I
128 * figure this out for sure.
129 * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
131 * Steven James 02/06/2003
133 /* NOTE: values now configured in configure_e7501_cas_latency() based
134 * on SPD info and total number of DIMMs (per Intel)
137 /* FDHC - Fixed DRAM Hole Control
140 * 0 == No memory Hole
141 * 1 == Memory Hole from 15MB to 16MB
144 * PAM - Programmable Attribute Map
145 * 0x59 [1:0] Reserved
146 * 0x59 [5:4] 0xF0000 - 0xFFFFF
147 * 0x5A [1:0] 0xC0000 - 0xC3FFF
148 * 0x5A [5:4] 0xC4000 - 0xC7FFF
149 * 0x5B [1:0] 0xC8000 - 0xCBFFF
150 * 0x5B [5:4] 0xCC000 - 0xCFFFF
151 * 0x5C [1:0] 0xD0000 - 0xD3FFF
152 * 0x5C [5:4] 0xD4000 - 0xD7FFF
153 * 0x5D [1:0] 0xD8000 - 0xDBFFF
154 * 0x5D [5:4] 0xDC000 - 0xDFFFF
155 * 0x5E [1:0] 0xE0000 - 0xE3FFF
156 * 0x5E [5:4] 0xE4000 - 0xE7FFF
157 * 0x5F [1:0] 0xE8000 - 0xEBFFF
158 * 0x5F [5:4] 0xEC000 - 0xEFFFF
159 * 00 == DRAM Disabled (All Access go to memory mapped I/O space)
160 * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
161 * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
162 * 11 == Normal (All Access go to DRAM)
165 // Map all legacy ranges to DRAM
166 0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
167 0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
169 /* DRB - DRAM Row Boundary Registers
171 * An array of 8 byte registers, which hold the ending
172 * memory address assigned to each pair of DIMMS, in 64MB
175 // Conservatively say each row has 64MB of ram, we will fix this up later
176 // NOTE: These defaults allow us to prime all of the DIMMs on the board
177 // without jumping through 36-bit adddressing hoops, even if the
178 // total memory is > 4 GB. Changing these values may break do_ram_command()!
179 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
180 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
182 /* DRA - DRAM Row Attribute Register
187 * [7:7] Device width for Odd numbered rows
188 * 0 == 8 bits wide x8
189 * 1 == 4 bits wide x4
190 * [6:4] Row Attributes for Odd numbered rows
191 * 010 == 8KB (for dual-channel)
192 * 011 == 16KB (for dual-channel)
193 * 100 == 32KB (for dual-channel)
194 * 101 == 64KB (for dual-channel)
196 * [3:3] Device width for Even numbered rows
197 * 0 == 8 bits wide x8
198 * 1 == 4 bits wide x4
199 * [2:0] Row Attributes for Even numbered rows
200 * 010 == 8KB (for dual-channel)
201 * 011 == 16KB (for dual-channel)
202 * 100 == 32KB (for dual-channel)
203 * 101 == 64KB (This page size appears broken)
206 // NOTE: overridden by configure_e7501_row_attributes(), later
209 /* DRT - DRAM Timing Register
212 * [29:29] Back to Back Write-Read Turn Around
213 * 0 == 3 clocks between WR-RD commands
214 * 1 == 2 clocks between WR-RD commands
215 * [28:28] Back to Back Read-Write Turn Around
216 * 0 == 5 clocks between RD-WR commands
217 * 1 == 4 clocks between RD-WR commands
218 * [27:27] Back to Back Read Turn Around
219 * 0 == 4 clocks between RD commands
220 * 1 == 3 clocks between RD commands
221 * [26:24] Read Delay (tRD)
227 * [18:16] DRAM idle timer
229 * 011 == 16 dram clocks
232 * [10:09] Active to Precharge (tRAS)
238 * [05:04] Cas Latency (tCL)
241 * 10 == Reserved (was 1.5 Clocks for E7500)
243 * [03:03] Write Ras# to Cas# Delay (tRCD)
246 * [02:01] Read RAS# to CAS# Delay (tRCD)
249 * 10 == 3 DRAM Clocks
250 * 11 == 2 DRAM Clocks
251 * [00:00] DRAM RAS# to Precharge (tRP)
256 // Some earlier settings:
257 /* Most aggressive settings possible */
258 // 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0),
259 // 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
260 // 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
262 // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
263 // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
264 0x78, 0xD7F8FFFF, (1<<29)|(1<<27)|(1<<16),
266 /* FIXME why was I attempting to set a reserved bit? */
269 /* DRC - DRAM Contoller Mode Register
272 * [29:29] Initialization Complete
277 * 0 == Single channel
279 * [21:20] DRAM Data Integrity Mode
280 * 00 == Disabled, no ECC
282 * 10 == Error checking, using chip-kill, with correction
284 * [19:18] DRB Granularity (Read-Only)
285 * 00 == 32 MB quantities (single channel mode)
286 * 01 == 64 MB quantities (dual-channel mode)
289 * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below)
290 * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
294 * [10:08] Refresh mode select
295 * 000 == Refresh disabled
296 * 001 == Refresh interval 15.6 usec
297 * 010 == Refresh interval 7.8 usec
298 * 011 == Refresh interval 64 usec
299 * 111 == Refresh every 64 clocks (fast refresh)
301 * [06:04] Mode Select (SMS)
302 * 000 == Reserved (was Self Refresh Mode in E7500)
304 * 010 == All Banks Precharge
305 * 011 == Mode Register Set
306 * 100 == Extended Mode Register Set
309 * 111 == Normal Operation
312 // .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
313 // .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
314 // .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
316 // Default to dual-channel mode, ECC, 1-clock address/cmd hold
317 // NOTE: configure_e7501_dram_controller_mode() configures further
318 0x7c, 0xff8ef8ff, (1<<22)|(2<<20)|(1<<16)|(0<<8),
320 /* Another Intel undocumented register
322 * [31:31] Purpose unknown
323 * [26:26] Master DLL Reset?
324 * 0 == Normal operation?
326 * [07:07] Periodic memory recalibration?
329 * [04:04] Receive FIFO RE-Sync?
330 * 0 == Normal operation?
333 // NOTE: Some factory BIOSs don't do this.
334 // Doesn't seem to matter either way.
335 0x88, 0xffffff00, 0x80,
337 /* CLOCK_DIS - CK/CK# Disable Register
339 * [7:7] DDR Frequency
340 * 0 == 100 MHz (200 MHz data rate)
341 * 1 == 133 MHz (266 MHz data rate)
356 // NOTE: Disable all clocks initially; turn ones we need back on
357 // in enable_e7501_clocks()
358 0x8C, 0xfffffff0, 0xf,
360 /* TOLM - Top of Low Memory Register
362 * [15:11] Top of low memory (TOLM)
363 * The address below 4GB that should be treated as RAM,
364 * on a 128MB granularity.
367 /* REMAPBASE - Remap Base Address Regsiter
370 * [09:00] Remap Base Address [35:26] 64M aligned
371 * Bits [25:0] are assumed to be 0.
374 // NOTE: TOLM overridden by configure_e7501_ram_addresses()
375 0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
377 /* REMAPLIMIT - Remap Limit Address Register
380 * [09:00] Remap Limit Address [35:26] 64M aligned
381 * When remaplimit < remapbase the remap window is disabled.
385 /* DVNP - Device Not Present Register
388 * [04:04] Device 4 Function 1 Present
391 * [03:03] Device 3 Function 1 Present
394 * [02:02] Device 2 Function 1 Present
398 * [00:00] Device 0 Function 1 Present
403 // Enable D0:D1, disable D2:F1, D3:F1, D4:F1
404 0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
407 0xd8, 0xffff9fff, 0x00000000,
409 // Undocumented - this is pure conjecture based on similarity to 855PM
410 /* MCHTST - MCH Test Register
412 * [31:31] Purpose unknown
413 * [30:30] Purpose unknown
414 * [29:23] Unknown - not used?
415 * [22:22] System Memory MMR Enable
416 * 0 == Disable: mem space and BAR at 0x14 are not accessible
417 * 1 == Enable: mem space and BAR at 0x14 are accessible
418 * [21:20] Purpose unknown
419 * [19:02] Unknown - not used?
420 * [01:01] D6EN (Device #6 enable)
423 * [00:00] Unknown - not used?
426 0xf4, 0x3f8ffffd, 0x40300002,
428 #ifdef SUSPICIOUS_LOOKING_CODE
429 // SJM: Undocumented.
430 // This will access D2:F0:0x50, is this correct??
431 0x1050, 0xffffffcf, 0x00000030,
435 /* DDR RECOMP tables */
437 // Slew table for 1x drive?
438 static const uint32_t maybe_1x_slew_table[] = {
439 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
440 0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
443 // Slew table for 2x drive?
444 static const uint32_t maybe_2x_slew_table[] = {
445 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
446 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
449 // Pull Up / Pull Down offset table, if analogous to IXP2800?
450 static const uint32_t maybe_pull_updown_offset_table[] = {
451 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
452 0x88888888, 0x88888888, 0x88888888, 0x88888888,
455 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
457 /**********************************************************************************/
458 #define SLOW_DOWN_IO inb(0x80);
459 //#define SLOW_DOWN_IO udelay(40);
461 /* Estimate that SLOW_DOWN_IO takes about 50&76us*/
462 /* delay for 200us */
465 static void do_delay(void)
468 for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
470 #define DO_DELAY do_delay();
476 #define EXTRA_DELAY DO_DELAY
479 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
480 /* DELAY FUNCTIONS */
481 /**********************************************************************************/
483 static void die_on_spd_error(int spd_return_value)
485 if (spd_return_value < 0)
486 die("Error reading SPD info\r\n");
489 //----------------------------------------------------------------------------------
490 // Function: sdram_spd_get_page_size
491 // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
492 // Return Value: struct dimm_size - log2(page size) for each side of the DIMM.
493 // Description: Calculate the page size for each physical bank of the DIMM:
494 // log2(page size) = (# columns) + log2(data width)
496 // NOTE: page size is the total number of data bits in a row.
498 static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
500 uint16_t module_data_width;
502 struct dimm_size pgsz;
508 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
509 if (value < 0) goto hw_err;
510 pgsz.side1 = value & 0xf; // # columns in bank 1
512 /* Get the module data width and convert it to a power of two */
513 value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
514 if (value < 0) goto hw_err;
515 module_data_width = (value & 0xff) << 8;
517 value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
518 if (value < 0) goto hw_err;
519 module_data_width |= (value & 0xff);
521 pgsz.side1 += log2(module_data_width);
524 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
525 if (value < 0) goto hw_err;
527 die("Bad SPD value\r\n");
530 pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
531 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
532 if (value < 0) goto hw_err;
533 if ((value & 0xf0) != 0) {
535 pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */
536 pgsz.side2 += (value>>4) & 0xf; /* Add in columns on side 2 */
544 return pgsz; // Never reached
548 //----------------------------------------------------------------------------------
549 // Function: sdram_spd_get_width
550 // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
551 // Return Value: dimm_size - width in bits of each DIMM side's DRAMs.
552 // Description: Read the width in bits of each DIMM side's DRAMs via SPD.
555 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
558 struct dimm_size width;
563 value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_DRAM_WIDTH);
564 die_on_spd_error(value);
566 width.side1 = value & 0x7f; // Mask off bank 2 flag
569 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
571 // If bank 2 exists, it's the same width as bank 1
572 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
573 die_on_spd_error(value);
575 #ifdef ROMCC_IF_BUG_FIXED
577 width.side2 = width.side1;
581 width.side2 = width.side1;
593 //----------------------------------------------------------------------------------
594 // Function: spd_get_dimm_size
595 // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
596 // Return Value: dimm_size - log2(number of bits) for each side of the DIMM
597 // Description: Calculate the log base 2 size in bits of both DIMM sides.
598 // log2(# bits) = (# columns) + log2(data width) +
599 // (# rows) + log2(banks per SDRAM)
601 // Note that it might be easier to use SPD byte 31 here, it has the
602 // DIMM size as a multiple of 4MB. The way we do it now we can size
603 // both sides of an asymmetric dimm.
605 static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
609 // Start with log2(page size)
610 struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
614 value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);
615 die_on_spd_error(value);
617 sz.side1 += value & 0xf;
623 sz.side2 += value >> 4; // Asymmetric
625 sz.side2 += value; // Symmetric
628 value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_DRAM);
629 die_on_spd_error(value);
640 //----------------------------------------------------------------------------------
641 // Function: are_spd_values_equal
642 // Parameters: spd_byte_number -
643 // dimmN_address - SMBus addresses of DIMM sockets to interrogate
644 // Return Value: 1 if both DIMM sockets report the same value for the specified
645 // SPD parameter; 0 if the values differed or an error occurred.
646 // Description: Determine whether two DIMMs have the same value for a SPD parameter.
648 static uint8_t are_spd_values_equal(uint8_t spd_byte_number, uint16_t dimm0_address,
649 uint16_t dimm1_address)
653 int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
654 int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
656 if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value))
662 //----------------------------------------------------------------------------------
663 // Function: spd_get_supported_dimms
664 // Parameters: ctrl - PCI addresses of memory controller functions, and
665 // SMBus addresses of DIMM slots on the mainboard
666 // Return Value: uint8_t - a bitmask indicating which of the possible sockets
667 // for each channel was found to contain a compatible DIMM.
668 // Bit 0 corresponds to the closest socket for channel 0,
669 // Bit 1 to the next socket for channel 0,
671 // Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0,
672 // Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1,
674 // Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
675 // Description: Scan for compatible DIMMs.
676 // The code in this module only supports dual-channel operation,
677 // so we test that compatible DIMMs are paired.
679 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
682 uint8_t dimm_mask = 0;
684 // Have to increase size of dimm_mask if this assertion is violated
685 ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
687 // Find DIMMs we can support on channel 0.
688 // Then see if the corresponding channel 1 DIMM has the same parameters,
689 // since we only support dual-channel.
691 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
693 uint16_t channel0_dimm = ctrl->channel0[i];
694 uint16_t channel1_dimm = ctrl->channel1[i];
695 uint8_t bDualChannel = 1;
696 struct dimm_size page_size;
697 struct dimm_size sdram_width;
701 if (channel0_dimm == 0)
702 continue; // No such socket on this mainboard
704 if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != MEMORY_TYPE_SDRAM_DDR)
707 #ifdef VALIDATE_DIMM_COMPATIBILITY
708 if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2)
709 continue; // Unsupported voltage
711 // E7501 does not support unregistered DIMMs
712 spd_value = spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
713 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
716 // Must support burst = 4 for dual-channel operation on E7501
717 // NOTE: for single-channel, burst = 8 is required
718 spd_value = spd_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS);
719 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
722 page_size = sdram_spd_get_page_size(channel0_dimm);
723 sdram_width = sdram_spd_get_width(channel0_dimm);
725 // Validate DIMM page size
726 // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
727 // NOTE: 4 KB = 32 Kb = 2^15
728 // 32 KB = 262 Kb = 2^18
730 if ((page_size.side1 < 15) || (page_size.side1 > 18))
733 // If DIMM is double-sided, verify side2 page size
734 if (page_size.side2 != 0) {
735 if ((page_size.side2 < 15) || (page_size.side2 > 18))
739 // Validate SDRAM width
740 // The E7501 only supports x4 and x8 devices
742 if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
745 // If DIMM is double-sided, verify side2 width
746 if (sdram_width.side2 != 0) {
747 if ((sdram_width.side2 != 4) && (sdram_width.side2 != 8))
751 // Channel 0 DIMM looks compatible.
752 // Now see if it is paired with the proper DIMM on channel 1.
754 ASSERT(channel1_dimm != 0); // No such socket on this mainboard??
756 // NOTE: unpopulated DIMMs cause read to fail
757 spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
758 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
760 print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
764 #ifdef VALIDATE_DIMM_COMPATIBILITY
765 spd_value = spd_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS);
766 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
769 for (j=0; j<sizeof(dual_channel_parameters); ++j) {
770 if (!are_spd_values_equal(dual_channel_parameters[j], channel0_dimm, channel1_dimm)) {
778 // Code around ROMCC bug in optimization of "if" statements
779 #ifdef ROMCC_IF_BUG_FIXED
781 // Made it through all the checks, this DIMM pair is usable
782 dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
785 print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
787 switch (bDualChannel) {
789 print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
793 // Made it through all the checks, this DIMM pair is usable
794 dimm_mask |= (1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i));
803 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
804 /* SPD (SERIAL PRESENCE DETECT) FUNCTIONS */
805 /**********************************************************************************/
807 //----------------------------------------------------------------------------------
808 // Function: do_ram_command
809 // Parameters: ctrl - PCI addresses of memory controller functions, and
810 // SMBus addresses of DIMM slots on the mainboard
811 // command - specifies the command to be sent to the DIMMs:
812 // RAM_COMMAND_NOP - No Operation
813 // RAM_COMMAND_PRECHARGE - Precharge all banks
814 // RAM_COMMAND_MRS - Load Mode Register
815 // RAM_COMMAND_EMRS - Load Extended Mode Register
816 // RAM_COMMAND_CBR - Auto Refresh ("CAS-before-RAS")
817 // RAM_COMMAND_NORMAL - Normal operation
818 // jedec_mode_bits - for mode register set & extended mode register set
819 // commands, bits 0-12 contain the register value in JEDEC format.
820 // Return Value: None
821 // Description: Send the specified command to all DIMMs.
823 static void do_ram_command(const struct mem_controller *ctrl, uint8_t command,
824 uint16_t jedec_mode_bits)
827 uint32_t dram_controller_mode;
828 uint8_t dimm_start_64M_multiple = 0;
829 uint16_t e7501_mode_bits = jedec_mode_bits;
831 // Configure the RAM command
832 dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
833 dram_controller_mode &= 0xFFFFFF8F;
834 dram_controller_mode |= command;
835 pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
837 // RAM_COMMAND_NORMAL is an exception.
838 // It affects only the memory controller and does not need to be "sent" to the DIMMs.
840 if (command != RAM_COMMAND_NORMAL) {
842 // Send the command to all DIMMs by accessing a memory location within each
843 // NOTE: for mode select commands, some of the location address bits
844 // are part of the command
846 // Map JEDEC mode bits to E7501
847 if (command == RAM_COMMAND_MRS) {
848 // Host address lines [15:5] map to DIMM address lines [12:11, 9:1]
849 // The E7501 hard-sets DIMM address lines 10 & 0 to zero
851 ASSERT(!(jedec_mode_bits & 0x0401));
853 e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15-12)) | // JEDEC bits 11-12 move to bits 14-15
854 ((jedec_mode_bits & 0x03FE) << (13-9)); // JEDEC bits 1-9 move to bits 5-13
856 } else if (command == RAM_COMMAND_EMRS) {
857 // Host address lines [15:3] map to DIMM address lines [12:0]
858 e7501_mode_bits = jedec_mode_bits <<= 3;
860 ASSERT(jedec_mode_bits == 0);
863 dimm_start_64M_multiple = 0;
865 for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
867 uint8_t dimm_end_64M_multiple = pci_read_config8(ctrl->d0, DRB_ROW_0 + i);
868 if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
870 // This code assumes DRAM row boundaries are all set below 4 GB
871 // NOTE: 0x40 * 64 MB == 4 GB
872 ASSERT(dimm_start_64M_multiple < 0x40);
874 // NOTE: 2^26 == 64 MB
876 uint32_t dimm_start_address = dimm_start_64M_multiple << 26;
878 RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
879 RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
880 RAM_DEBUG_MESSAGE("\r\n");
881 read32(dimm_start_address + e7501_mode_bits);
883 // Set the start of the next DIMM
884 dimm_start_64M_multiple = dimm_end_64M_multiple;
890 //----------------------------------------------------------------------------------
891 // Function: set_ram_mode
892 // Parameters: ctrl - PCI addresses of memory controller functions, and
893 // SMBus addresses of DIMM slots on the mainboard
894 // jedec_mode_bits - for mode register set & extended mode register set
895 // commands, bits 0-12 contain the register value in JEDEC format.
896 // Return Value: None
897 // Description: Set the mode register of all DIMMs. The proper CAS# latency
898 // setting is added to the mode bits specified by the caller.
900 static void set_ram_mode(const struct mem_controller *ctrl, uint16_t jedec_mode_bits)
902 ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
904 uint32_t dram_cas_latency = pci_read_config32(ctrl->d0, DRT) & DRT_CAS_MASK;
906 switch (dram_cas_latency) {
908 jedec_mode_bits |= SDRAM_CAS_2_5;
912 jedec_mode_bits |= SDRAM_CAS_2_0;
920 do_ram_command(ctrl, RAM_COMMAND_MRS, jedec_mode_bits);
923 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
924 /* SDRAM CONFIGURATION FUNCTIONS */
925 /**********************************************************************************/
927 //----------------------------------------------------------------------------------
928 // Function: configure_dimm_row_boundaries
929 // Parameters: ctrl - PCI addresses of memory controller functions, and
930 // SMBus addresses of DIMM slots on the mainboard
931 // dimm_log2_num_bits - log2(number of bits) for each side of the DIMM
932 // total_dram_64M_multiple - total DRAM in the system (as a
933 // multiple of 64 MB) for DIMMs < dimm_index
934 // dimm_index - which DIMM pair is being processed
935 // (0..MAX_DIMM_SOCKETS_PER_CHANNEL)
936 // Return Value: New multiple of 64 MB total DRAM in the system
937 // Description: Configure the E7501's DRAM Row Boundary registers for the memory
938 // present in the specified DIMM.
940 static uint8_t configure_dimm_row_boundaries(const struct mem_controller *ctrl,
941 struct dimm_size dimm_log2_num_bits,
942 uint8_t total_dram_64M_multiple,
947 ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
949 // DIMM sides must be at least 32 MB
950 ASSERT(dimm_log2_num_bits.side1 >= 28);
951 ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28));
953 // In dual-channel mode, we are called only once for each pair of DIMMs.
954 // Each time we process twice the capacity of a single DIMM.
956 // Convert single DIMM capacity to paired DIMM capacity
957 // (multiply by two ==> add 1 to log2)
958 dimm_log2_num_bits.side1++;
959 if (dimm_log2_num_bits.side2 > 0)
960 dimm_log2_num_bits.side2++;
962 // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
963 // to the total capacity of the system
964 // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
966 total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
968 // Configure the boundary address for the row on side 1
969 pci_write_config8(ctrl->d0, DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple);
971 // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
972 // (as a multiple of 64 MB) to the total capacity of the system
973 if (dimm_log2_num_bits.side2 >= 29)
974 total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side2 - 29));
976 // Configure the boundary address for the row (if any) on side 2
977 pci_write_config8(ctrl->d0, DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple);
979 // Update boundaries for rows subsequent to these.
980 // These settings will be overridden by a subsequent call if a populated physical slot exists
982 for(i=dimm_index+1; i<MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
983 pci_write_config8(ctrl->d0, DRB_ROW_0+(i<<1), total_dram_64M_multiple);
984 pci_write_config8(ctrl->d0, DRB_ROW_1+(i<<1), total_dram_64M_multiple);
987 return total_dram_64M_multiple;
990 //----------------------------------------------------------------------------------
991 // Function: configure_e7501_ram_addresses
992 // Parameters: ctrl - PCI addresses of memory controller functions, and
993 // SMBus addresses of DIMM slots on the mainboard
994 // dimm_mask - bitmask of populated DIMMs on the board - see
995 // spd_get_supported_dimms()
996 // Return Value: None
997 // Description: Program the E7501's DRAM row boundary addresses and its Top Of
998 // Low Memory (TOLM). If necessary, set up a remap window so we
999 // don't waste DRAM that ordinarily would lie behind addresses
1000 // reserved for memory-mapped I/O.
1002 static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
1006 uint8_t total_dram_64M_multiple = 0;
1008 // Configure the E7501's DRAM row boundaries
1009 // Start by zeroing out the temporary initial configuration
1010 pci_write_config32(ctrl->d0, DRB_ROW_0, 0);
1011 pci_write_config32(ctrl->d0, DRB_ROW_4, 0);
1013 for(i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1015 uint16_t dimm_socket_address = ctrl->channel0[i];
1016 struct dimm_size sz;
1018 if (!(dimm_mask & (1 << i)))
1019 continue; // This DIMM not present
1021 sz = spd_get_dimm_size(dimm_socket_address);
1023 RAM_DEBUG_MESSAGE("dimm size =");
1024 RAM_DEBUG_HEX32(sz.side1);
1025 RAM_DEBUG_MESSAGE(" ");
1026 RAM_DEBUG_HEX32(sz.side2);
1027 RAM_DEBUG_MESSAGE("\r\n");
1030 die("Bad SPD value\r\n");
1032 total_dram_64M_multiple = configure_dimm_row_boundaries(ctrl, sz, total_dram_64M_multiple, i);
1035 // Configure the Top Of Low Memory (TOLM) in the E7501
1036 // This address must be a multiple of 128 MB that is less than 4 GB.
1037 // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
1038 // in the highest 5 bits.
1040 // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
1041 // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
1042 // such as flash and memory-mapped I/O.
1044 // If there is more than 3 GB of DRAM, we define a remap window which
1045 // makes the DRAM "behind" the reserved region available above the top of physical
1048 // NOTE: 0xC0000000 / (64 MB) == 0x30
1050 if (total_dram_64M_multiple <= 0x30) {
1052 // <= 3 GB total RAM
1054 /* I should really adjust all of this in C after I have resources
1055 * to all of the pci devices.
1058 // Round up to 128MB granularity
1059 // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
1061 uint8_t total_dram_128M_multiple = (total_dram_64M_multiple + 1) >> 1;
1063 // Convert to high 16 bits of address
1064 uint16_t top_of_low_memory = total_dram_128M_multiple << 11;
1066 pci_write_config16(ctrl->d0, TOLM, top_of_low_memory);
1072 // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
1073 uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0
1074 uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF
1078 pci_write_config16(ctrl->d0, TOLM, 0xc000);
1080 // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
1081 // visible just beyond 4 GB or the end of physical memory, whichever is larger
1082 // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
1083 // (i.e. a multiple of 64 MB) in the lowest 10 bits.
1084 // NOTE: 0x100000000 / (64 MB) == 0x40
1086 if (total_dram_64M_multiple < 0x40) {
1087 remap_base = 0x40; // 0x100000000
1088 remap_limit = 0x40 + (total_dram_64M_multiple - 0x30) - 1;
1091 pci_write_config16(ctrl->d0, REMAPBASE, remap_base);
1092 pci_write_config16(ctrl->d0, REMAPLIMIT, remap_limit);
1096 //----------------------------------------------------------------------------------
1097 // Function: initialize_ecc
1098 // Parameters: ctrl - PCI addresses of memory controller functions, and
1099 // SMBus addresses of DIMM slots on the mainboard
1100 // Return Value: None
1101 // Description: If we're configured to use ECC, initialize the SDRAM and
1102 // clear the E7501's ECC error flags.
1104 static void initialize_ecc(const struct mem_controller *ctrl)
1106 uint32_t dram_controller_mode;
1108 /* Test to see if ECC support is enabled */
1109 dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
1110 dram_controller_mode >>= 20;
1111 dram_controller_mode &= 3;
1112 if (dram_controller_mode == 2) {
1116 RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n");
1117 /* Initialize ECC bits , use ECC zero mode (new to 7501)*/
1118 pci_write_config8(ctrl->d0, MCHCFGNS, 0x06);
1119 pci_write_config8(ctrl->d0, MCHCFGNS, 0x07);
1121 // Wait for scrub cycle to complete
1123 byte = pci_read_config8(ctrl->d0, MCHCFGNS);
1125 } while ( (byte & 0x08 ) == 0);
1127 pci_write_config8(ctrl->d0, MCHCFGNS, byte & 0xfc);
1128 RAM_DEBUG_MESSAGE("ECC state initialized.\r\n");
1130 /* Clear the ECC error bits */
1131 pci_write_config8(ctrl->d0f1, DRAM_FERR, 0x03);
1132 pci_write_config8(ctrl->d0f1, DRAM_NERR, 0x03);
1134 // Clear DRAM Interface error bits (write-one-clear)
1135 pci_write_config32(ctrl->d0f1, FERR_GLOBAL, 1<<18);
1136 pci_write_config32(ctrl->d0f1, NERR_GLOBAL, 1<<18);
1138 // Start normal ECC scrub
1139 pci_write_config8(ctrl->d0, MCHCFGNS, 5);
1144 //----------------------------------------------------------------------------------
1145 // Function: configure_e7501_dram_timing
1146 // Parameters: ctrl - PCI addresses of memory controller functions, and
1147 // SMBus addresses of DIMM slots on the mainboard
1148 // dimm_mask - bitmask of populated DIMMs on the board - see
1149 // spd_get_supported_dimms()
1150 // Return Value: None
1151 // Description: Program the DRAM Timing register of the E7501 (except for CAS#
1152 // latency, which is assumed to have been programmed already), based
1153 // on the parameters of the various installed DIMMs.
1155 static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask)
1158 uint32_t dram_timing;
1160 uint8_t slowest_row_precharge = 0;
1161 uint8_t slowest_ras_cas_delay = 0;
1162 uint8_t slowest_active_to_precharge_delay = 0;
1163 uint32_t current_cas_latency = pci_read_config32(ctrl->d0, DRT) & DRT_CAS_MASK;
1165 // CAS# latency must be programmed beforehand
1166 ASSERT((current_cas_latency == DRT_CAS_2_0) || (current_cas_latency == DRT_CAS_2_5));
1168 // Each timing parameter is determined by the slowest DIMM
1170 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1172 uint16_t dimm_socket_address;
1174 if (!(dimm_mask & (1 << i)))
1175 continue; // This DIMM not present
1177 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1178 dimm_socket_address = ctrl->channel0[i];
1180 dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1182 value = spd_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME);
1183 if (value < 0) goto hw_err;
1184 if (value > slowest_row_precharge)
1185 slowest_row_precharge = value;
1187 value = spd_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY);
1188 if(value < 0 ) goto hw_err;
1189 if (value > slowest_ras_cas_delay)
1190 slowest_ras_cas_delay = value;
1192 value = spd_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
1193 if(value < 0 ) goto hw_err;
1194 if (value > slowest_active_to_precharge_delay)
1195 slowest_active_to_precharge_delay = value;
1198 // NOTE for timing parameters:
1199 // At 133 MHz, 1 clock == 7.52 ns
1201 /* Read the initial state */
1202 dram_timing = pci_read_config32(ctrl->d0, DRT);
1206 // E7501 supports only 2 or 3 clocks for tRP
1207 if (slowest_row_precharge > ((22<<2) | (2<<0)))
1208 die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks
1209 else if (slowest_row_precharge > (15<<2))
1210 dram_timing &= ~(1<<0); // > 15.0 ns: 3 clocks
1212 dram_timing |= (1<<0); // <= 15.0 ns: 2 clocks
1216 // E7501 supports only 2 or 3 clocks for tRCD
1217 // Use the same value for both read & write
1218 dram_timing &= ~((1<<3)|(3<<1));
1219 if (slowest_ras_cas_delay > ((22<<2) | (2<<0)))
1220 die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks
1221 else if (slowest_ras_cas_delay > (15<<2))
1222 dram_timing |= (2<<1); // > 15.0 ns: 3 clocks
1224 dram_timing |= ((1<<3) | (3<<1)); // <= 15.0 ns: 2 clocks
1228 // E7501 supports only 5, 6, or 7 clocks for tRAS
1229 // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
1230 dram_timing &= ~(3<<9);
1232 if (slowest_active_to_precharge_delay > 52)
1233 die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks
1234 else if (slowest_active_to_precharge_delay > 45)
1235 dram_timing |= (0<<9); // 46-52 ns: 7 clocks
1236 else if (slowest_active_to_precharge_delay > 37)
1237 dram_timing |= (1<<9); // 38-45 ns: 6 clocks
1239 dram_timing |= (2<<9); // < 38 ns: 5 clocks
1244 /* Set to a 7 clock read delay. This is for 133Mhz
1245 * with a CAS latency of 2.5 if 2.0 a 6 clock
1248 dram_timing &= ~(7<<24); // 7 clocks
1249 if (current_cas_latency == DRT_CAS_2_0)
1250 dram_timing |= (1<<24); // 6 clocks
1253 * Back to Back Read-Write Turn Around
1255 /* Set to a 5 clock back to back read to write turn around.
1256 * 4 is a good delay if the CAS latency is 2.0 */
1258 dram_timing &= ~(1<<28); // 5 clocks
1259 if (current_cas_latency == DRT_CAS_2_0)
1260 dram_timing |= (1<<28); // 4 clocks
1262 pci_write_config32(ctrl->d0, DRT, dram_timing);
1270 //----------------------------------------------------------------------------------
1271 // Function: configure_e7501_cas_latency
1272 // Parameters: ctrl - PCI addresses of memory controller functions, and
1273 // SMBus addresses of DIMM slots on the mainboard
1274 // dimm_mask - bitmask of populated DIMMs on the board - see
1275 // spd_get_supported_dimms()
1276 // Return Value: None
1277 // Description: Determine the shortest CAS# latency that the E7501 and all DIMMs
1278 // have in common, and program the E7501 to use it.
1280 static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8_t dimm_mask)
1284 uint32_t dram_timing;
1285 uint16_t maybe_dram_read_timing;
1288 // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
1289 // NOTE: E7501 supports only 2.0 and 2.5
1290 uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
1291 uint32_t current_cas_latency;
1292 uint32_t dimm_compatible_cas_latencies;
1294 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1296 uint16_t dimm_socket_address;
1298 if (!(dimm_mask & (1 << i)))
1299 continue; // This DIMM not usable
1301 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1302 dimm_socket_address = ctrl->channel0[i];
1304 dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1306 value = spd_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES);
1307 if (value < 0) goto hw_err;
1309 dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM
1310 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
1312 // Can we support the highest CAS# latency?
1314 value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
1315 if (value < 0) goto hw_err;
1317 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1319 // Our bus is too fast for this CAS# latency
1320 // Remove it from the bitmask of those supported by the DIMM that are compatible
1321 dimm_compatible_cas_latencies &= ~current_cas_latency;
1324 // Can we support the next-highest CAS# latency (max - 0.5)?
1326 current_cas_latency >>= 1;
1327 if (current_cas_latency != 0) {
1328 value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05);
1329 if(value < 0 ) goto hw_err;
1331 dimm_compatible_cas_latencies &= ~current_cas_latency;
1334 // Can we support the next-highest CAS# latency (max - 1.0)?
1335 current_cas_latency >>= 1;
1336 if (current_cas_latency != 0) {
1337 value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10);
1338 if(value < 0 ) goto hw_err;
1340 dimm_compatible_cas_latencies &= ~current_cas_latency;
1343 // Restrict the system to CAS# latencies compatible with this DIMM
1344 system_compatible_cas_latencies &= dimm_compatible_cas_latencies;
1346 /* go to the next DIMM */
1349 /* After all of the arduous calculation setup with the fastest
1350 * cas latency I can use.
1353 dram_timing = pci_read_config32(ctrl->d0, DRT);
1354 dram_timing &= ~(DRT_CAS_MASK);
1356 maybe_dram_read_timing = pci_read_config16(ctrl->d0, MAYBE_DRDCTL);
1357 maybe_dram_read_timing &= 0xF00C;
1359 if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
1360 dram_timing |= DRT_CAS_2_0;
1361 maybe_dram_read_timing |= 0xBB1;
1363 else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
1365 uint32_t dram_row_attributes = pci_read_config32(ctrl->d0, DRA);
1367 dram_timing |= DRT_CAS_2_5;
1369 // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
1370 // different value if all DIMM slots are populated
1372 if ((dram_row_attributes & 0xff) && (dram_row_attributes & 0xff00) &&
1373 (dram_row_attributes & 0xff0000) && (dram_row_attributes & 0xff000000)) {
1375 // All slots populated
1376 maybe_dram_read_timing |= 0x0882;
1379 // Some unpopulated slots
1380 maybe_dram_read_timing |= 0x0662;
1384 die("No CAS# latencies compatible with all DIMMs!!\r\n");
1386 pci_write_config32(ctrl->d0, DRT, dram_timing);
1388 /* set master DLL reset */
1389 dword = pci_read_config32(ctrl->d0, 0x88);
1391 pci_write_config32(ctrl->d0, 0x88, dword);
1393 dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */
1394 dword |= 0xd2109800;
1396 pci_write_config32(ctrl->d0, 0x88, dword);
1399 pci_write_config16(ctrl->d0, MAYBE_DRDCTL, maybe_dram_read_timing);
1401 dword = pci_read_config32(ctrl->d0, 0x88); /* reset master DLL reset */
1403 pci_write_config32(ctrl->d0, 0x88, dword);
1411 //----------------------------------------------------------------------------------
1412 // Function: configure_e7501_dram_controller_mode
1413 // Parameters: ctrl - PCI addresses of memory controller functions, and
1414 // SMBus addresses of DIMM slots on the mainboard
1415 // dimm_mask - bitmask of populated DIMMs on the board - see
1416 // spd_get_supported_dimms()
1417 // Return Value: None
1418 // Description: Configure the refresh interval so that we refresh no more often
1419 // than required by the "most needy" DIMM. Also disable ECC if any
1420 // of the DIMMs don't support it.
1422 static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl,
1428 uint32_t controller_mode = pci_read_config32(ctrl->d0, DRC);
1429 uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
1431 // Code below assumes that most aggressive settings are in
1432 // force when we are called, either via E7501 reset defaults
1433 // or by sdram_set_registers():
1437 ASSERT((controller_mode & (3<<20)) == (2<<20)); // ECC
1438 ASSERT(!(controller_mode & (7 << 8))); // Refresh
1440 /* Walk through _all_ dimms and find the least-common denominator for:
1445 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1447 uint32_t dimm_refresh_mode;
1449 uint16_t dimm_socket_address;
1451 if (!(dimm_mask & (1 << i))) {
1452 continue; // This DIMM not usable
1455 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1456 dimm_socket_address = ctrl->channel0[i];
1458 dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1460 // Disable ECC mode if any one of the DIMMs does not support ECC
1461 // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
1463 value = spd_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE);
1464 die_on_spd_error(value);
1465 if (value != ERROR_SCHEME_ECC) {
1466 controller_mode &= ~(3 << 20);
1469 value = spd_read_byte(dimm_socket_address, SPD_REFRESH);
1470 die_on_spd_error(value);
1471 value &= 0x7f; // Mask off self-refresh bit
1472 if(value > MAX_SPD_REFRESH_RATE) {
1473 print_err("unsupported refresh rate\r\n");
1477 // Get the appropriate E7501 refresh mode for this DIMM
1478 dimm_refresh_mode = refresh_rate_map[value];
1479 if (dimm_refresh_mode > 7) {
1480 print_err("unsupported refresh rate\r\n");
1484 // If this DIMM requires more frequent refresh than others,
1485 // update the system setting
1486 if (refresh_frequency[dimm_refresh_mode] > refresh_frequency[system_refresh_mode])
1487 system_refresh_mode = dimm_refresh_mode;
1489 #ifdef SUSPICIOUS_LOOKING_CODE
1490 // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
1491 // than the clock period of the memory controller. Also, no other northbridge
1492 // looks at SPD_ADDRESS_CMD_HOLD.
1494 // Switch to 2 clocks for address/command if required by any one of the DIMMs
1495 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1496 value = spd_read_byte(dimm_socket_address, SPD_ADDRESS_CMD_HOLD);
1497 die_on_spd_error(value);
1498 if(value >= 0xa0) { /* At 133MHz this constant should be 0x75 */
1499 controller_mode &= ~(1<<16); /* Use two clock cyles instead of one */
1503 /* go to the next DIMM */
1506 controller_mode |= (system_refresh_mode << 8);
1508 // Configure the E7501
1509 pci_write_config32(ctrl->d0, DRC, controller_mode);
1512 //----------------------------------------------------------------------------------
1513 // Function: configure_e7501_row_attributes
1514 // Parameters: ctrl - PCI addresses of memory controller functions, and
1515 // SMBus addresses of DIMM slots on the mainboard
1516 // dimm_mask - bitmask of populated DIMMs on the board - see
1517 // spd_get_supported_dimms()
1518 // Return Value: None
1519 // Description: Configure the E7501's DRAM Row Attributes (DRA) registers
1520 // based on DIMM parameters read via SPD. This tells the controller
1521 // the width of the SDRAM chips on each DIMM side (x4 or x8) and
1522 // the page size of each DIMM side (4, 8, 16, or 32 KB).
1524 static void configure_e7501_row_attributes(const struct mem_controller *ctrl,
1528 uint32_t row_attributes = 0;
1530 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1532 uint16_t dimm_socket_address = ctrl->channel0[i];
1533 struct dimm_size page_size;
1534 struct dimm_size sdram_width;
1536 if (!(dimm_mask & (1 << i)))
1537 continue; // This DIMM not usable
1539 // Get the relevant parameters via SPD
1540 page_size = sdram_spd_get_page_size(dimm_socket_address);
1541 sdram_width = sdram_spd_get_width(dimm_socket_address);
1543 // Update the DRAM Row Attributes.
1544 // Page size is encoded as log2(page size in bits) - log2(8 Kb)
1545 // NOTE: 8 Kb = 2^13
1546 row_attributes |= (page_size.side1 - 13) << (i<<3); // Side 1 of each DIMM is an EVEN row
1548 if (sdram_width.side2 > 0)
1549 row_attributes |= (page_size.side2 - 13) << ((i<<3) + 4); // Side 2 is ODD
1551 // Set x4 flags if appropriate
1552 if (sdram_width.side1 == 4) {
1553 row_attributes |= 0x08 << (i<<3);
1556 if (sdram_width.side2 == 4) {
1557 row_attributes |= 0x08 << ((i<<3) + 4);
1560 /* go to the next DIMM */
1563 /* Write the new row attributes register */
1564 pci_write_config32(ctrl->d0, DRA, row_attributes);
1567 //----------------------------------------------------------------------------------
1568 // Function: enable_e7501_clocks
1569 // Parameters: ctrl - PCI addresses of memory controller functions, and
1570 // SMBus addresses of DIMM slots on the mainboard
1571 // dimm_mask - bitmask of populated DIMMs on the board - see
1572 // spd_get_supported_dimms()
1573 // Return Value: None
1574 // Description: Enable clock signals for populated DIMM sockets and disable them
1575 // for unpopulated sockets (to reduce EMI).
1577 static void enable_e7501_clocks(const struct mem_controller *ctrl, uint8_t dimm_mask)
1580 uint8_t clock_disable = pci_read_config8(ctrl->d0, CKDIS);
1582 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1584 uint8_t socket_mask = 1 << i;
1586 if (dimm_mask & socket_mask)
1587 clock_disable &= ~socket_mask; // DIMM present, enable clock
1589 clock_disable |= socket_mask; // DIMM absent, disable clock
1592 pci_write_config8(ctrl->d0, CKDIS, clock_disable);
1596 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1597 /* DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS */
1598 /**********************************************************************************/
1600 //----------------------------------------------------------------------------------
1601 // Function: RAM_RESET_DDR_PTR
1602 // Parameters: ctrl - PCI addresses of memory controller functions, and
1603 // SMBus addresses of DIMM slots on the mainboard
1604 // Return Value: None
1605 // Description: DDR Receive FIFO RE-Sync (?)
1607 static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl)
1610 byte = pci_read_config8(ctrl->d0, 0x88);
1612 pci_write_config8(ctrl->d0, 0x88, byte);
1614 byte = pci_read_config8(ctrl->d0, 0x88);
1616 pci_write_config8(ctrl->d0, 0x88, byte);
1619 //----------------------------------------------------------------------------------
1620 // Function: ram_set_d0f0_regs
1621 // Parameters: ctrl - PCI addresses of memory controller functions, and
1622 // SMBus addresses of DIMM slots on the mainboard
1623 // Return Value: None
1624 // Description: Set E7501 registers that are either independent of DIMM specifics,
1625 // or establish default settings that will be overridden when we
1626 // learn the specifics.
1627 // This sets PCI configuration registers to known good values based
1628 // on the table 'constant_register_values', which are a triple of
1629 // configuration register offset, mask, and bits to set.
1631 static void ram_set_d0f0_regs(const struct mem_controller *ctrl)
1634 int num_values = sizeof(constant_register_values)/sizeof(constant_register_values[0]);
1636 ASSERT((num_values % 3) == 0); // Bad table?
1638 for(i = 0; i < num_values; i += 3) {
1640 uint32_t register_offset = constant_register_values[i];
1641 uint32_t bits_to_mask = constant_register_values[i+1];
1642 uint32_t bits_to_set = constant_register_values[i+2];
1643 uint32_t register_value;
1645 // It's theoretically possible to set values for something other than D0:F0,
1646 // but it's not typically done here
1647 ASSERT(!(register_offset & 0xFFFFFF00));
1649 // bits_to_mask and bits_to_set should not reference the same bits
1650 // Again, not strictly an error, but flagged as a potential bug
1651 ASSERT((bits_to_mask & bits_to_set) == 0);
1653 register_value = pci_read_config32(ctrl->d0, register_offset);
1654 register_value &= bits_to_mask;
1655 register_value |= bits_to_set;
1657 pci_write_config32(ctrl->d0, register_offset, register_value);
1661 //----------------------------------------------------------------------------------
1662 // Function: write_8dwords
1663 // Parameters: src_addr
1665 // Return Value: None
1666 // Description: Copy 64 bytes from one location to another.
1668 static void write_8dwords(uint32_t* src_addr, uint32_t dst_addr)
1671 for (i=0; i<8; i++) {
1672 write32(dst_addr, *src_addr);
1674 dst_addr += sizeof(uint32_t);
1678 //----------------------------------------------------------------------------------
1679 // Function: ram_set_rcomp_regs
1680 // Parameters: ctrl - PCI addresses of memory controller functions, and
1681 // SMBus addresses of DIMM slots on the mainboard
1682 // Return Value: None
1683 // Description: Set the E7501's (undocumented) RCOMP registers.
1684 // Per the 855PM datasheet and IXP2800 HW Initialization Reference
1685 // Manual, RCOMP registers appear to affect drive strength,
1686 // pullup/pulldown offset, and slew rate of various signal groups.
1687 // Comments below are conjecture based on apparent similarity
1688 // between the E7501 and these two chips.
1690 static void ram_set_rcomp_regs(const struct mem_controller *ctrl)
1693 uint8_t maybe_strength_control;
1695 RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n");
1697 /*enable access to the rcomp bar*/
1698 dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST);
1700 pci_write_config32(ctrl->d0, MAYBE_MCHTST, dword);
1703 // Set the RCOMP MMIO base address
1704 pci_write_config32(ctrl->d0, MAYBE_SMRBASE, RCOMP_MMIO);
1706 // Block RCOMP updates while we configure the registers
1707 dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1709 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1712 /* Begin to write the RCOMP registers */
1714 // Set CMD and DQ/DQS strength to 2x (?)
1715 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
1716 maybe_strength_control |= 0x44;
1717 write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
1719 write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
1720 write16(RCOMP_MMIO + 0x42, 0);
1722 write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
1724 // NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
1725 write16(RCOMP_MMIO + 0x40, 0);
1728 // Set RCVEnOut# strength to 2x (?)
1729 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
1730 maybe_strength_control |= 4;
1731 write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
1733 write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
1734 write16(RCOMP_MMIO + 0x50, 0);
1736 // Set CS# strength for x4 SDRAM to 2x (?)
1737 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
1738 maybe_strength_control |= 4;
1739 write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
1741 write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
1742 write16(RCOMP_MMIO + 0x48, 0);
1744 // Set CKE strength for x4 SDRAM to 2x (?)
1745 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
1746 maybe_strength_control |= 4;
1747 write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
1749 write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
1750 write16(RCOMP_MMIO + 0x44, 0);
1752 // Set CK strength for x4 SDRAM to 1x (?)
1753 maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
1754 maybe_strength_control |= 1;
1755 write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
1757 write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
1758 write16(RCOMP_MMIO + 0x4c, 0);
1760 write8(RCOMP_MMIO + 0x2c, 0xff);
1763 // Set the digital filter length to 8 (?)
1764 dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1766 // NOTE: Some factory BIOS don't do this.
1767 // Doesn't seem to matter either way.
1771 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1776 /* unblock updates */
1777 dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1779 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1781 // Force a RCOMP measurement cycle?
1783 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1785 write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1790 /*disable access to the rcomp bar */
1791 dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST);
1793 pci_write_config32(ctrl->d0, MAYBE_MCHTST, dword);
1797 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1798 /* DIMM-INDEPENDENT CONFIGURATION FUNCTIONS */
1799 /**********************************************************************************/
1801 //----------------------------------------------------------------------------------
1802 // Function: sdram_enable
1803 // Parameters: controllers - not used
1804 // ctrl - PCI addresses of memory controller functions, and
1805 // SMBus addresses of DIMM slots on the mainboard
1806 // Return Value: None
1807 // Description: Go through the JEDEC initialization sequence for all DIMMs,
1808 // then enable refresh and initialize ECC and memory to zero.
1809 // Upon exit, SDRAM is up and running.
1811 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1813 uint8_t dimm_mask = pci_read_config16(ctrl->d0, SKPD);
1814 uint32_t dram_controller_mode;
1819 /* 1 & 2 Power up and start clocks */
1820 RAM_DEBUG_MESSAGE("Ram Enable 1\r\n");
1821 RAM_DEBUG_MESSAGE("Ram Enable 2\r\n");
1823 /* A 200us delay is needed */
1829 RAM_DEBUG_MESSAGE("Ram Enable 3\r\n");
1830 do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
1833 /* 4 Precharge all */
1834 RAM_DEBUG_MESSAGE("Ram Enable 4\r\n");
1835 do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
1838 /* wait until the all banks idle state... */
1839 /* 5. Issue EMRS to enable DLL */
1840 RAM_DEBUG_MESSAGE("Ram Enable 5\r\n");
1841 do_ram_command(ctrl, RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
1845 RAM_DEBUG_MESSAGE("Ram Enable 6\r\n");
1846 set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
1849 /* Ensure a 200us delay between the DLL reset in step 6 and the final
1850 * mode register set in step 9.
1851 * Infineon needs this before any other command is sent to the ram.
1856 /* 7 Precharge all */
1857 RAM_DEBUG_MESSAGE("Ram Enable 7\r\n");
1858 do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
1861 /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1862 RAM_DEBUG_MESSAGE("Ram Enable 8\r\n");
1863 do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1865 do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1867 /* And for good luck 6 more CBRs */
1868 do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1870 do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1872 do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1874 do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1876 do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1878 do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1881 /* 9 mode register set */
1882 RAM_DEBUG_MESSAGE("Ram Enable 9\r\n");
1883 set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
1886 /* 10 DDR Receive FIFO RE-Sync */
1887 RAM_DEBUG_MESSAGE("Ram Enable 10\r\n");
1888 RAM_RESET_DDR_PTR(ctrl);
1891 /* 11 normal operation */
1892 RAM_DEBUG_MESSAGE("Ram Enable 11\r\n");
1893 do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
1896 // Reconfigure the row boundaries and Top of Low Memory
1897 // to match the true size of the DIMMs
1898 configure_e7501_ram_addresses(ctrl, dimm_mask);
1900 /* Finally enable refresh */
1901 dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
1902 dram_controller_mode |= (1 << 29);
1903 pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
1906 initialize_ecc(ctrl);
1908 dram_controller_mode = pci_read_config32(ctrl->d0, DRC); /* FCS_EN */
1909 dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit
1910 pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
1912 RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n");
1918 //----------------------------------------------------------------------------------
1919 // Function: sdram_set_spd_registers
1920 // Parameters: ctrl - PCI addresses of memory controller functions, and
1921 // SMBus addresses of DIMM slots on the mainboard
1922 // Return Value: None
1923 // Description: Configure SDRAM controller parameters that depend on
1924 // characteristics of the DIMMs installed in the system. These
1925 // characteristics are read from the DIMMs via the standard Serial
1926 // Presence Detect (SPD) interface.
1928 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
1932 RAM_DEBUG_MESSAGE("Reading SPD data...\r\n");
1934 //activate_spd_rom(ctrl); Not necessary for this chipset
1936 dimm_mask = spd_get_supported_dimms(ctrl);
1938 if (dimm_mask == 0) {
1939 print_debug("No usable memory for this controller\r\n");
1942 enable_e7501_clocks(ctrl, dimm_mask);
1944 RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n");
1946 configure_e7501_row_attributes(ctrl, dimm_mask);
1947 configure_e7501_dram_controller_mode(ctrl, dimm_mask);
1948 configure_e7501_cas_latency(ctrl, dimm_mask);
1949 RAM_RESET_DDR_PTR(ctrl);
1951 configure_e7501_dram_timing(ctrl, dimm_mask);
1953 RAM_DEBUG_MESSAGE("done\r\n");
1956 // NOTE: configure_e7501_ram_addresses() is NOT called here.
1957 // We want to keep the default 64 MB/row mapping until sdram_enable() is called,
1958 // even though the default mapping is almost certainly incorrect.
1959 // The default mapping makes it easy to initialize all of the DIMMs
1960 // even if the total system memory is > 4 GB.
1962 // Save the dimm_mask for when sdram_enable is called, so it can call
1963 // configure_e7501_ram_addresses() without having to regenerate the bitmask
1965 pci_write_config16(ctrl->d0, SKPD, dimm_mask);
1968 //----------------------------------------------------------------------------------
1969 // Function: sdram_set_registers
1970 // Parameters: ctrl - PCI addresses of memory controller functions, and
1971 // SMBus addresses of DIMM slots on the mainboard
1972 // Return Value: None
1973 // Description: Do basic ram setup that does NOT depend on serial presence detect
1974 // information (i.e. independent of DIMM specifics).
1976 static void sdram_set_registers(const struct mem_controller *ctrl)
1978 RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n");
1981 ram_set_rcomp_regs(ctrl);
1982 ram_set_d0f0_regs(ctrl);
1985 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1986 /* PUBLIC INTERFACE */
1987 /**********************************************************************************/