2 /* This was originally for the e7500, modified for e7501
3 * The primary differences are that 7501 apparently can
4 * support single channel RAM (i haven't tested),
5 * CAS1.5 is no longer supported, The ECC scrubber
6 * now supports a mode to zero RAM and init ECC in one step
7 * and the undocumented registers at 0x80 require new
8 * (undocumented) values determined by guesswork and
9 * comparison w/ OEM BIOS values.
10 * Steven James 02/06/2003
13 /* converted to C 6/2004 yhlu */
15 #define DEBUG_RAM_CONFIG 1
17 #define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0))
19 /* DDR DIMM Mode register Definitions */
21 #define BURST_2 (1<<0)
22 #define BURST_4 (2<<0)
23 #define BURST_8 (3<<0)
25 #define BURST_SEQUENTIAL (0<<3)
26 #define BURST_INTERLEAVED (1<<3)
28 #define CAS_2_0 (0x2<<4)
29 #define CAS_3_0 (0x3<<4)
30 #define CAS_1_5 (0x5<<4)
31 #define CAS_2_5 (0x6<<4)
33 #define MODE_NORM (0 << 7)
34 #define MODE_DLL_RESET (2 << 7)
35 #define MODE_TEST (1 << 7)
37 #define BURST_LENGTH BURST_4
38 #define BURST_TYPE BURST_INTERLEAVED
39 #define CAS_LATENCY CAS_2_0
40 //#define CAS_LATENCY CAS_2_5
41 //#define CAS_LATENCY CAS_1_5
43 #define MRS_VALUE (MODE_NORM | CAS_LATENCY | BURST_TYPE | BURST_LENGTH)
44 #define EMRS_VALUE 0x000
48 #define RAM_COMMAND_NONE 0x0
49 #define RAM_COMMAND_NOP 0x1
50 #define RAM_COMMAND_PRECHARGE 0x2
51 #define RAM_COMMAND_MRS 0x3
52 #define RAM_COMMAND_EMRS 0x4
53 #define RAM_COMMAND_CBR 0x6
54 #define RAM_COMMAND_NORMAL 0x7
57 static inline void do_ram_command (const struct mem_controller *ctrl, uint32_t value) {
62 #if DEBUG_RAM_CONFIG >= 2
64 print_debug_hex8(value);
67 /* %ecx - initial address to read from */
68 /* Compute the offset */
71 /* Set the ram command */
72 byte = pci_read_config8(ctrl->d0, 0x7c);
74 byte |= (uint8_t)(value & 0xff);
75 pci_write_config8(ctrl->d0, 0x7c, byte);
77 /* Assert the command to the memory */
78 #if DEBUG_RAM_CONFIG >= 2
80 print_debug_hex32(dword);
84 result = read32(dword);
86 /* Go to the next base address */
91 /* The command has been sent to all dimms so get out */
95 static inline void RAM_CMD(const struct mem_controller *ctrl, uint32_t command, uint32_t offset) {
96 uint32_t value = ((offset) << (MD_SHIFT + 16))|((command << 4) & 0x70) ;
97 do_ram_command(ctrl, value);
100 #define RAM_NOP(ctrl) RAM_CMD(ctrl, RAM_COMMAND_NOP, 0)
101 #define RAM_PRECHARGE(ctrl) RAM_CMD(ctrl, RAM_COMMAND_PRECHARGE, 0)
102 #define RAM_CBR(ctrl) RAM_CMD(ctrl, RAM_COMMAND_CBR, 0)
103 #define RAM_EMRS(ctrl) RAM_CMD(ctrl, RAM_COMMAND_EMRS, EMRS_VALUE)
105 static const uint8_t ram_cas_latency[] = {
106 CAS_2_5, CAS_2_0, CAS_1_5, CAS_2_5
109 static inline void ram_mrs(const struct mem_controller *ctrl, uint32_t value){
110 /* Read the cas latency setting */
113 byte = pci_read_config8(ctrl->d0, 0x78);
114 /* Transform it into the form expected by SDRAM */
115 dword = ram_cas_latency[(byte>>4) & 3];
117 value |= (dword<<(16+MD_SHIFT));
119 value |= (MODE_NORM | BURST_TYPE | BURST_LENGTH) << (16+MD_SHIFT);
121 do_ram_command(ctrl, value);
124 #define RAM_MRS(ctrl, dll_reset) ram_mrs( ctrl, (dll_reset << (8+MD_SHIFT+ 16)) | ((RAM_COMMAND_MRS <<4)& 0x70) )
126 static void RAM_NORMAL(const struct mem_controller *ctrl) {
128 byte = pci_read_config8(ctrl->d0, 0x7c);
130 byte |= (RAM_COMMAND_NORMAL << 4);
131 pci_write_config8(ctrl->d0, 0x7c, byte);
134 static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl) {
136 byte = pci_read_config8(ctrl->d0, 0x88);
138 pci_write_config8(ctrl->d0, 0x88, byte);
139 byte = pci_read_config8(ctrl->d0, 0x88);
141 pci_write_config8(ctrl->d0, 0x88, byte);
144 static void ENABLE_REFRESH(const struct mem_controller *ctrl)
147 dword = pci_read_config32(ctrl->d0, 0x7c);
149 pci_write_config32(ctrl->d0, 0x7c, dword);
153 * Table: constant_register_values
155 static const long register_values[] = {
156 /* SVID - Subsystem Vendor Identification Register
158 * [15:00] Subsytem Vendor ID (Indicates system board vendor)
160 /* SID - Subsystem Identification Register
162 * [15:00] Subsystem ID
164 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
168 * This register has something to do with CAS latencies,
169 * possibily this is the real chipset control.
170 * At 0x00 CAS latency 1.5 works.
171 * At 0x06 CAS latency 2.5 works.
172 * At 0x01 CAS latency 2.0 works.
174 /* This is still undocumented in e7501, but with different values
175 * CAS 2.0 values taken from Intel BIOS settings, others are a guess
176 * and may be terribly wrong. Old values preserved as comments until I
177 * figure this out for sure.
178 * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
180 * Steven James 02/06/2003
182 #if CAS_LATENCY == CAS_2_5
183 // 0x80, 0xfffffe00, 0x06 /* Intel E7500 recommended */
184 0x80, 0xfffff000, 0x0662, /* from Factory Bios */
185 #elif CAS_LATENCY == CAS_2_0
186 // 0x80, 0xfffffe00, 0x0d /* values for register 0x80 */
187 0x80, 0xfffff000, 0x0bb1, /* values for register 0x80 */
190 /* Enable periodic memory recalibration */
191 0x88, 0xffffff00, 0x80,
193 /* FDHC - Fixed DRAM Hole Control
196 * 0 == No memory Hole
197 * 1 == Memory Hole from 15MB to 16MB
200 * PAM - Programmable Attribute Map
201 * 0x59 [1:0] Reserved
202 * 0x59 [5:4] 0xF0000 - 0xFFFFF
203 * 0x5A [1:0] 0xC0000 - 0xC3FFF
204 * 0x5A [5:4] 0xC4000 - 0xC7FFF
205 * 0x5B [1:0] 0xC8000 - 0xCBFFF
206 * 0x5B [5:4] 0xCC000 - 0xCFFFF
207 * 0x5C [1:0] 0xD0000 - 0xD3FFF
208 * 0x5C [5:4] 0xD4000 - 0xD7FFF
209 * 0x5D [1:0] 0xD8000 - 0xDBFFF
210 * 0x5D [5:4] 0xDC000 - 0xDFFFF
211 * 0x5E [1:0] 0xE0000 - 0xE3FFF
212 * 0x5E [5:4] 0xE4000 - 0xE7FFF
213 * 0x5F [1:0] 0xE8000 - 0xEBFFF
214 * 0x5F [5:4] 0xEC000 - 0xEFFFF
215 * 00 == DRAM Disabled (All Access go to memory mapped I/O space)
216 * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
217 * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
218 * 11 == Normal (All Access go to DRAM)
220 0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
221 0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
223 /* DRB - DRAM Row Boundary Registers
225 * An array of 8 byte registers, which hold the ending
226 * memory address assigned to each pair of DIMMS, in 64MB
229 /* Conservatively say each row has 64MB of ram, we will fix this up later */
230 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
231 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
235 /* DRA - DRAM Row Attribute Register
240 * [7:7] Device width for Odd numbered rows
241 * 0 == 8 bits wide x8
242 * 1 == 4 bits wide x4
243 * [6:4] Row Attributes for Odd numbered rows
249 * [3:3] Device width for Even numbered rows
250 * 0 == 8 bits wide x8
251 * 1 == 4 bits wide x4
252 * [2:0] Row Attributes for Even numbered rows
256 * 101 == 64KB (This page size appears broken)
260 (((0<<3)|(0<<0))<< 0) |
261 (((0<<3)|(0<<0))<< 4) |
262 (((0<<3)|(0<<0))<< 8) |
263 (((0<<3)|(0<<0))<<12) |
264 (((0<<3)|(0<<0))<<16) |
265 (((0<<3)|(0<<0))<<20) |
266 (((0<<3)|(0<<0))<<24) |
267 (((0<<3)|(0<<0))<<28),
270 /* DRT - DRAM Time Register
273 * [29:29] Back to Back Write-Read Turn Around
274 * 0 == 3 clocks between WR-RD commands
275 * 1 == 2 clocks between WR-RD commands
276 * [28:28] Back to Back Read-Write Turn Around
277 * 0 == 5 clocks between RD-WR commands
278 * 1 == 4 clocks between RD-WR commands
279 * [27:27] Back to Back Read Turn Around
280 * 0 == 4 clocks between RD commands
281 * 1 == 3 clocks between RD commands
282 * [26:24] Read Delay (tRD)
288 * [18:16] DRAM idle timer
290 * 011 == 16 dram clocks
291 * 001 == Datasheet says reserved, but Intel BIOS sets it
293 * [10:09] Active to Precharge (tRAS)
299 * [05:04] Cas Latency (tCL)
304 * [03:03] Write Ras# to Cas# Delay (tRCD)
307 * [02:01] Read RAS# to CAS# Delay (tRCD)
310 * 10 == 3 DRAM Clocks
311 * 11 == 2 DRAM Clocks
312 * [00:00] DRAM RAS# to Precharge (tRP)
316 #define DRT_CAS_2_5 (0<<4)
317 #define DRT_CAS_2_0 (1<<4)
318 #define DRT_CAS_1_5 (2<<4)
319 #define DRT_CAS_MASK (3<<4)
321 #if CAS_LATENCY == CAS_2_5
322 #define DRT_CL DRT_CAS_2_5
323 #elif CAS_LATENCY == CAS_2_0
324 #define DRT_CL DRT_CAS_2_0
325 #elif CAS_LATENCY == CAS_1_5
326 #define DRT_CL DRT_CAS_1_5
329 /* Most aggressive settings possible */
330 // 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|DRT_CL|(1<<3)|(1<<1)|(1<<0),
331 // 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
332 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
334 /* FIXME why was I attempting to set a reserved bit? */
337 /* DRC - DRAM Contoller Mode Register
340 * [29:29] Initialization Complete
345 * 0 == Single channel
347 * [21:20] DRAM Data Integrity Mode
348 * 00 == Disabled, no ECC
350 * 10 == Error checking, using chip-kill, with correction
354 * [17:17] (Intel Undocumented) should always be set to 1
355 * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
359 * [10:08] Refresh mode select
360 * 000 == Refresh disabled
361 * 001 == Refresh interval 15.6 usec
362 * 010 == Refresh interval 7.8 usec
363 * 011 == Refresh interval 64 usec
364 * 111 == Refresh every 64 clocks (fast refresh)
366 * [06:04] Mode Select (SMS)
367 * 000 == Self Refresh Mode
369 * 010 == All Banks Precharge
370 * 011 == Mode Register Set
371 * 100 == Extended Mode Register Set
374 * 111 == Normal Operation
377 // .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
378 // .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
379 // .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
380 0x7c, 0xff82fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
383 /* Another Intel undocumented register */
384 0x88, 0x080007ff, (1<<31)|(1 << 30)|(1<<28)|(0 << 26)|(0x10 << 21)|(10 << 16)|(0x13 << 11),
386 /* CLOCK_DIS - CK/CK# Disable Register
402 0x8C, 0xfffffff0, 0xf,
404 /* TOLM - Top of Low Memory Register
406 * [15:11] Top of low memory (TOLM)
407 * The address below 4GB that should be treated as RAM,
408 * on a 128MB granularity.
411 /* REMAPBASE - Remap Base Address Regsiter
414 * [09:00] Remap Base Address [35:26] 64M aligned
415 * Bits [25:0] are assumed to be 0.
417 0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
418 /* REMAPLIMIT - Remap Limit Address Register
421 * [09:00] Remap Limit Address [35:26] 64M aligned
422 * When remaplimit < remapbase this register is disabled.
426 /* DVNP - Device Not Present Register
429 * [04:04] Device 4 Function 1 Present
432 * [03:03] Device 3 Function 1 Present
435 * [02:02] Device 2 Function 1 Present
439 * [00:00] Device 0 Function 1 Present
443 0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
444 0xd8, 0xffff9fff, 0x00000000,
445 0xf4, 0x3f8ffffd, 0x40300002,
446 0x1050, 0xffffffcf, 0x00000030,
451 * Routine: ram_set_registers
454 * Trashed: %eax, %ebx, %ecx, %edx, %esi, %eflags
455 * Effects: Do basic ram setup that does not depend on serial
456 * presence detect information.
457 * This sets PCI configuration registers to known good
458 * values based on the table:
459 * constant_register_values
460 * Which are a triple of configuration regiser, mask, and value.
463 /* from 1M or 512K */
464 #define RCOMP_MMIO 0x100000
466 /* DDR RECOMP table */
468 static const long ddr_rcomp_1[] = {
469 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
470 0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
472 static const long ddr_rcomp_2[] = {
473 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
474 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
476 static const long ddr_rcomp_3[] = {
477 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
478 0x88888888, 0x88888888, 0x88888888, 0x88888888,
481 #define rcomp_init_str "Setting RCOMP registers.\r\n"
483 static void write_8dwords(uint32_t src_addr, uint32_t dst_addr) {
487 dword = read32(src_addr);
488 write32(dst_addr, dword);
496 #define SLOW_DOWN_IO inb(0x80);
498 #define SLOW_DOWN_IO udelay(40);
501 static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
504 print_debug(rcomp_init_str);
507 /*enable access to the rcomp bar */
508 dword = pci_read_config32(ctrl->d0, 0x0f4);
510 dword |=((1<<30)|1<<22);
511 pci_write_config32(ctrl->d0, 0x0f4, dword);
514 /* Set the MMIO address to 512K */
515 pci_write_config32(ctrl->d0, 0x14, RCOMP_MMIO);
517 dword = read32(RCOMP_MMIO + 0x20);
519 write32(RCOMP_MMIO + 0x20, dword);
522 /* Begin to write the RCOMP registers */
524 write8(RCOMP_MMIO + 0x2c, 0xff);
525 write32(RCOMP_MMIO + 0x30, 0x01040444);
526 write8(RCOMP_MMIO + 0x34, 0x04);
527 write32(RCOMP_MMIO + 0x40, 0);
528 write16(RCOMP_MMIO + 0x44, 0);
529 write16(RCOMP_MMIO + 0x48, 0);
530 write16(RCOMP_MMIO + 0x50, 0);
531 write_8dwords((uint32_t)ddr_rcomp_1, RCOMP_MMIO + 0x60);
532 write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x80);
533 write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0xa0);
534 write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x140);
535 write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x1c0);
536 write_8dwords((uint32_t)ddr_rcomp_3, RCOMP_MMIO + 0x180);
538 dword = read32(RCOMP_MMIO + 0x20);
541 write32(RCOMP_MMIO + 0x20, dword);
546 /* unblock updates */
547 dword = read32(RCOMP_MMIO + 0x20);
549 write32(RCOMP_MMIO+0x20, dword);
551 write32(RCOMP_MMIO+0x20, dword);
553 write32(RCOMP_MMIO+0x20, dword);
558 /*disable access to the rcomp bar */
559 dword = pci_read_config32(ctrl->d0, 0x0f4);
561 pci_write_config32(ctrl->d0, 0x0f4, dword);
565 static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
566 #if DEBUG_RAM_CONFIG >= 2
571 max = sizeof(register_values)/sizeof(register_values[0]);
572 for(i = 0; i < max; i += 3) {
574 #if DEBUG_RAM_CONFIG >= 2
575 print_debug_hex32(register_values[i]);
577 print_debug_hex32(register_values[i+2]);
580 reg = pci_read_config32(ctrl->d0,register_values[i]);
581 reg &= register_values[i+1];
582 reg |= register_values[i+2] & ~(register_values[i+1]);
583 pci_write_config32(ctrl->d0,register_values[i], reg);
587 #if DEBUG_RAM_CONFIG >= 2
591 static void sdram_set_registers(const struct mem_controller *ctrl){
592 ram_set_rcomp_regs(ctrl);
593 ram_set_d0f0_regs(ctrl);
598 * Routine: sdram_spd_get_page_size
599 * Arguments: %bl SMBUS_MEM_DEVICE
601 * %edi log base 2 page size of DIMM side 1 in bits
602 * %esi log base 2 page size of DIMM side 2 in bits
604 * Preserved: %ebx (except %bh), %ebp
606 * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
607 * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
609 * Effects: Uses serial presence detect to set %edi & %esi
610 * to the page size of a dimm.
612 * %bl SMBUS_MEM_DEVICE
613 * %edi holds the page size for the first side of the DIMM.
614 * %esi holds the page size for the second side of the DIMM.
615 * memory size is represent as a power of 2.
617 * This routine may be worth moving into generic code somewhere.
619 struct dimm_page_size {
624 static struct dimm_page_size sdram_spd_get_page_size(unsigned device) {
628 struct dimm_page_size pgsz;
633 value = spd_read_byte(device, 4); /* columns */
634 if(value < 0) goto hw_err;
635 pgsz.side1 = value & 0xf;
637 /* Get the module data width and convert it to a power of two */
638 value = spd_read_byte(device,7); /* (high byte) */
639 if(value < 0) goto hw_err;
643 value = spd_read_byte(device, 6); /* (low byte) */
644 if(value < 0) goto hw_err;
645 ecx |= (value & 0xff);
647 pgsz.side1 += log2(ecx); /* compute cheap log base 2 */
650 value = spd_read_byte(device, 5); /* number of physical banks */
651 if(value < 0) goto hw_err;
652 if(value==1) goto out;
653 if(value!=2) goto val_err;
655 /* Start with the symmetrical case */
656 pgsz.side2 = pgsz.side1;
657 value = spd_read_byte(device,4); /* columns */
658 if(value < 0) goto hw_err;
659 if((value & 0xf0)==0 ) goto out;
660 pgsz.side2 -=value & 0xf; /* Subtract out columns on side 1 */
661 pgsz.side2 +=(value>>4)& 0xf; /* Add in columns on side 2 */
665 die("Bad SPD value\r\n");
666 /* If an hw_error occurs report that I have no memory */
676 * Routine: sdram_spd_get_width
677 * Arguments: %bl SMBUS_MEM_DEVICE
679 * %edi width of SDRAM chips on DIMM side 1 in bits
680 * %esi width of SDRAM chips on DIMM side 2 in bits
682 * Preserved: %ebx (except %bh), %ebp
684 * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
685 * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
687 * Effects: Uses serial presence detect to set %edi & %esi
688 * to the width of a dimm.
690 * %bl SMBUS_MEM_DEVICE
691 * %edi holds the width for the first side of the DIMM.
692 * %esi holds the width for the second side of the DIMM.
693 * memory size is represent as a power of 2.
695 * This routine may be worth moving into generic code somewhere.
702 static struct dimm_width sdram_spd_get_width(unsigned device) {
704 struct dimm_width wd;
710 value = spd_read_byte(device, 13); /* sdram width */
711 if(value < 0 ) goto hw_err;
714 wd.side1 = value & 0x7f;
717 value = spd_read_byte(device, 5); /* number of physical banks */
718 if(value < 0 ) goto hw_err;
719 if(value <=1 ) goto out;
721 /* Start with the symmetrical case */
724 if((ecx & 0x80)==0) goto out;
736 * Routine: sdram_spd_get_dimm_size
737 * Arguments: %bl SMBUS_MEM_DEVICE
739 * %edi log base 2 size of DIMM side 1 in bits
740 * %esi log base 2 size of DIMM side 2 in bits
742 * Preserved: %ebx (except %bh), %ebp
744 * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
745 * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
747 * Effects: Uses serial presence detect to set %edi & %esi
748 * the size of a dimm.
750 * %bl SMBUS_MEM_DEVICE
751 * %edi holds the memory size for the first side of the DIMM.
752 * %esi holds the memory size for the second side of the DIMM.
753 * memory size is represent as a power of 2.
755 * This routine may be worth moving into generic code somewhere.
763 static struct dimm_size spd_get_dimm_size(unsigned device)
765 /* Calculate the log base 2 size of a DIMM in bits */
771 /* Note it might be easier to use byte 31 here, it has the DIMM size as
772 * a multiple of 4MB. The way we do it now we can size both
773 * sides of an assymetric dimm.
775 value = spd_read_byte(device, 3); /* rows */
776 if (value < 0) goto hw_err;
777 // if ((value & 0xf) == 0) goto val_err;
778 sz.side1 += value & 0xf;
780 value = spd_read_byte(device, 4); /* columns */
781 if (value < 0) goto hw_err;
782 // if ((value & 0xf) == 0) goto val_err;
783 sz.side1 += value & 0xf;
785 value = spd_read_byte(device, 17); /* banks */
786 if (value < 0) goto hw_err;
787 // if ((value & 0xff) == 0) goto val_err;
789 sz.side1 += log2(value);
791 /* Get the module data width and convert it to a power of two */
792 value = spd_read_byte(device, 7); /* (high byte) */
793 if (value < 0) goto hw_err;
797 low = spd_read_byte(device, 6); /* (low byte) */
798 if (low < 0) goto hw_err;
799 value |= (low & 0xff);
800 // if ((value != 72) && (value != 64)) goto val_err;
801 sz.side1 += log2(value);
804 value = spd_read_byte(device, 5); /* number of physical banks */
805 if (value < 0) goto hw_err;
806 if (value == 1) goto out;
807 // if (value != 2) goto val_err;
809 /* Start with the symmetrical case */
812 value = spd_read_byte(device, 3); /* rows */
813 if (value < 0) goto hw_err;
814 if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */
815 sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
816 sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
818 value = spd_read_byte(device, 4); /* columns */
819 if (value < 0) goto hw_err;
820 // if ((value & 0xff) == 0) goto val_err;
821 sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
822 sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
826 die("Bad SPD value\r\n");
827 /* If an hw_error occurs report that I have no memory */
838 * This is a place holder fill this out
839 * Routine: spd_set_row_attributes
840 * Arguments: %bl SMBUS_MEM_DEVICE
842 * %edi log base 2 size of DIMM side 1 in bits
843 * %esi log base 2 size of DIMM side 2 in bits
845 * Preserved: %ebx (except %bh), %ebp
847 * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
848 * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
850 * Effects: Uses serial presence detect to set %edi & %esi
851 * the size of a dimm.
853 * %bl SMBUS_MEM_DEVICE
854 * %edi holds the memory size for the first side of the DIMM.
855 * %esi holds the memory size for the second side of the DIMM.
856 * memory size is represent as a power of 2.
858 * This routine may be worth moving into generic code somewhere.
860 static long spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) {
866 /* Walk through all dimms and find the interesection of the support
867 * for ecc sdram and refresh rates
871 for(i = 0; i < DIMM_SOCKETS; i++) {
872 if (!(dimm_mask & (1 << i))) {
875 /* Test to see if I have ecc sdram */
876 struct dimm_page_size sz;
877 sz = sdram_spd_get_page_size(ctrl->channel0[i]); /* SDRAM type */
878 #if DEBUG_RAM_CONFIG>=2
879 print_debug("page size =");
880 print_debug_hex32(sz.side1);
882 print_debug_hex32(sz.side2);
886 /* Test to see if the dimm is present */
889 /* Test for a valid dimm width */
890 if((sz.side1 <15) || (sz.side1>18) ) {
891 print_err("unsupported page size\r\n");
894 /* double because I have 2 channels */
897 /* Convert to the format needed for the DRA register */
900 /* Place in the %ebp the dra place holder */ //i
901 dword |= sz.side1<<(i<<3);
903 /* Test to see if the second side is present */
907 /* Test for a valid dimm width */
908 if((sz.side2 <15) || (sz.side2>18) ) {
909 print_err("unsupported page size\r\n");
912 /* double because I have 2 channels */
915 /* Convert to the format needed for the DRA register */
918 /* Place in the %ebp the dra place holder */ //i
919 dword |= sz.side2<<((i<<3) + 4 );
924 /* Now add the SDRAM chip width to the DRA */
925 struct dimm_width wd;
926 wd = sdram_spd_get_width(ctrl->channel0[i]);
929 print_debug("width =");
930 print_debug_hex32(wd.side1);
932 print_debug_hex32(wd.side2);
936 if(wd.side1 == 0) continue;
938 /* Enable an x4 device */
939 dword |= 0x08 << (i<<3);
942 if(wd.side2 == 0) continue;
944 /* Enable an x4 device */
945 dword |= 0x08 << ((i<<3 ) + 4);
948 /* go to the next DIMM */
951 /* Write the new row attributes register */
952 pci_write_config32(ctrl->d0, 0x70, dword);
957 #define spd_pre_init "Reading SPD data...\r\n"
958 #define spd_pre_set "setting based on SPD data...\r\n"
959 #define spd_post_init "done\r\n"
962 static const uint32_t refresh_rate_rank[]= {
963 /* Refresh rates ordered from most conservative (lowest)
964 * to most agressive (highest)
965 * disabled 0 -> rank 3
966 * 15.6usec 1 -> rank 1
967 * 7.8 usec 2 -> rank 0
971 static const uint32_t refresh_rate_index[] = {
972 /* Map the spd refresh rates to memory controller settings
982 #define MAX_SPD_REFRESH_RATE 5
984 static long spd_set_dram_controller_mode (const struct mem_controller *ctrl, long dimm_mask) {
992 /* Read the inititial state */
993 dword = pci_read_config32(ctrl->d0, 0x7c);
996 // Test if ECC cmos option is enabled
997 movb $RTC_BOOT_BYTE, %al
1002 // Clear the ecc enable
1003 andl $~(3 << 20), %esi
1008 /* Walk through all dimms and find the interesection of the support
1009 * for ecc sdram and refresh rates
1013 for(i = 0; i < DIMM_SOCKETS; i++) {
1014 if (!(dimm_mask & (1 << i))) {
1017 /* Test to see if I have ecc sdram */
1018 value = spd_read_byte(ctrl->channel0[i], 11); /* SDRAM type */
1019 if(value < 0) continue;
1021 /* Clear the ecc enable */
1022 dword &= ~(3 << 20);
1024 value = spd_read_byte(ctrl->channel0[i], 12); /* SDRAM refresh rate */
1025 if(value < 0 ) continue;
1027 if(value > MAX_SPD_REFRESH_RATE) { print_err("unsupported refresh rate\r\n");}
1028 // if(value == 0xff) { print_err("unsupported refresh rate\r\n");}
1030 ecx = refresh_rate_index[value];
1032 /* Isolate the old refresh rate setting */
1033 /* Load the refresh rate ranks */
1034 edx = refresh_rate_rank[(dword >> 8) & 3]<<8;
1035 edx |= refresh_rate_rank[ecx] & 0xff;
1037 /* See if the new refresh rate is more conservative than the old
1038 * refresh rate setting. (Lower ranks are more conservative)
1040 if((edx & 0xff)< ((edx >> 8) & 0xff) ) {
1041 /* Clear the old refresh rate */
1043 /* Move in the new refresh rate */
1047 value = spd_read_byte(ctrl->channel0[i], 33); /* Address and command hold time after clock */
1048 if(value < 0) continue;
1049 if(value >= 0xa0) { /* At 133Mhz this constant should be 0x75 */
1050 dword &= ~(1<<16); /* Use two clock cyles instead of one */
1053 /* go to the next DIMM */
1056 /* Now write the controller mode */
1057 pci_write_config32(ctrl->d0, 0x7c, dword);
1062 static long spd_enable_clocks(const struct mem_controller *ctrl, long dimm_mask)
1068 /* Read the inititial state */
1069 dword = pci_read_config32(ctrl->d0, 0x8c);
1071 # Intel clears top bit here, should we?
1072 # No the default is on and for normal timming it should be on. Tom Z
1077 for(i = 0; i < DIMM_SOCKETS; i++) {
1078 if (!(dimm_mask & (1 << i))) {
1081 /* Read any spd byte to see if the dimm is present */
1082 value = spd_read_byte(ctrl->channel0[i], 5); /* Physical Banks */
1083 if(value < 0) continue;
1088 pci_write_config32(ctrl->d0, 0x8c, dword);
1093 static const uint16_t cas_latency_80[] = {
1094 /* For cas latency 2.0 0x01 works and until I see a large test sample
1095 * I am not prepared to change this value, to the intel recommended value
1096 * of 0x0d. Eric Biederman
1098 /* The E7501 requires b1 rather than 01 for CAS2 or memory will be hosed
1099 * CAS 1.5 is claimed to be unsupported, will try to test that
1100 * will need to determine correct values for other CAS values
1101 * (perhaps b5, b1, b6?)
1102 * Steven James 02/06/2003
1105 //# .byte 0x05, 0x01, 0x06
1106 //# .byte 0xb5, 0xb1, 0xb6
1107 0x0, 0x0bb1, 0x0662 /* RCVEN */
1109 static const uint16_t cas_latency_80_4dimms[] = {
1114 static const uint8_t cas_latency_78[] = {
1115 DRT_CAS_1_5, DRT_CAS_2_0, DRT_CAS_2_5
1118 static long spd_set_cas_latency(const struct mem_controller *ctrl, long dimm_mask) {
1119 /* Walk through all dimms and find the interesection of the
1120 * supported cas latencies.
1123 /* Initially allow cas latencies 2.5, 2.0
1124 * which the chipset supports.
1126 uint32_t dword = (1<<3)| (1<<2);// esi
1135 for(i = 0; i < DIMM_SOCKETS; i++) {
1136 if (!(dimm_mask & (1 << i))) {
1139 value = spd_read_byte(ctrl->channel0[i], 18);
1140 if(value < 0) continue;
1141 /* Find the highest supported cas latency */
1142 ecx = log2(value & 0xff);
1145 /* Remember the supported cas latencies */
1146 ecx = (value & 0xff);
1148 /* Verify each cas latency at 133Mhz */
1149 /* Verify slowest/highest CAS latency */
1150 value = spd_read_byte(ctrl->channel0[i], 9);
1151 if(value < 0 ) continue;
1153 /* The bus is too fast so we cannot support this case latency */
1157 /* Verify the highest CAS latency - 0.5 clocks */
1160 value = spd_read_byte(ctrl->channel0[i], 23);
1161 if(value < 0 ) continue;
1163 /* The bus is too fast so we cannot support this cas latency */
1168 /* Verify the highest CAS latency - 1.0 clocks */
1171 value = spd_read_byte(ctrl->channel0[i], 25);
1172 if(value < 0 ) continue;
1174 /* The bus is too fast so we cannot support this cas latency */
1179 /* Now find which cas latencies are supported for the bus */
1181 /* go to the next DIMM */
1184 /* After all of the arduous calculation setup with the fastest
1185 * cas latency I can use.
1187 value = __builtin_bsf(dword); // bsrl = log2 how about bsfl?
1188 if(value ==0 ) return -1;
1191 byte = pci_read_config8(ctrl->d0, 0x78);
1192 byte &= ~(DRT_CAS_MASK);
1193 byte |= cas_latency_78[ecx];
1194 pci_write_config8(ctrl->d0,0x78, byte);
1196 /* set master DLL reset */
1197 dword = pci_read_config32(ctrl->d0, 0x88);
1200 /* the rest of the references are words */
1201 // ecx<<=1; // don't need shift left, because we already define that in u16 array
1202 pci_write_config32(ctrl->d0, 0x88, dword);
1205 dword &= 0x0c0000ff; /* patch try register 88 is undocumented tnz */
1206 dword |= 0xd2109800;
1208 pci_write_config32(ctrl->d0, 0x88, dword);
1210 word = pci_read_config16(ctrl->d0, 0x80);
1212 word |= cas_latency_80[ecx];
1214 dword = pci_read_config32(ctrl->d0, 0x70);
1216 if((dword & 0xff) !=0 ) {
1218 if((dword & 0xff)!=0) {
1220 if((dword & 0xff)!=0) {
1222 if( (dword & 0xff)!=0) {
1223 word &=~(0x0fff); /* we have dimms in all 4 slots */
1224 word |=cas_latency_80_4dimms[ecx];
1230 pci_write_config16(ctrl->d0, 0x80, word);
1232 dword = pci_read_config32(ctrl->d0, 0x88); /* reset master DLL reset */
1234 pci_write_config32(ctrl->d0, 0x88, dword);
1236 RAM_RESET_DDR_PTR(ctrl);
1242 static long spd_set_dram_timing(const struct mem_controller *ctrl, long dimm_mask) {
1243 /* Walk through all dimms and find the interesection of the
1244 * supported dram timings.
1251 /* Read the inititial state */
1252 dword = pci_read_config32(ctrl->d0, 0x78);
1254 # Intel clears top bit here, should we?
1255 # No the default is on and for normal timming it should be on. Tom Z
1260 for(i = 0; i < DIMM_SOCKETS; i++) {
1261 if (!(dimm_mask & (1 << i))) {
1265 value = spd_read_byte(ctrl->channel0[i], 27);
1266 if(value < 0) continue;
1267 if(value > (15<<2)) {
1268 /* At 133Mhz if row precharge time is above than 15ns than we
1269 * need 3 clocks not 2 clocks.
1274 value = spd_read_byte(ctrl->channel0[i],29);
1275 if(value < 0 ) continue;
1276 if(value > (15<<2)) {
1277 /* At 133Mhz if the Minimum ras to cas delay is about 15ns we
1278 * need 3 clocks not 2 clocks.
1280 dword &= ~((1<<3)|(1<<1));
1283 value = spd_read_byte(ctrl->channel0[i],30);
1284 if(value < 0 ) continue;
1285 /* Convert tRAS from ns to 133Mhz clock cycles */
1286 value <<=1; /* mult by 2 to make 7.5 15 */
1287 value += 15; /* Make certain we round up */
1289 value &= 0xff; /* Clear the upper bits of eax */
1292 /* Don't even process small timings */
1295 /* Die if the value is to large */
1297 die ("unsupported_rcd\r\n");
1299 /* Convert to clocks - 5 */
1301 /* Convert the existing value into clocks - 5 */
1302 tmp = (~((dword>>9) & 3) - 1) & 3;
1303 /* See if we need a slower timing */
1305 /* O.k. put in our slower timing */
1307 dword |= ((~(value + 1)) & 3)<<9 ;
1312 /* Set to a 7 clock read delay. This is for 133Mhz
1313 * with a CAS latency of 2.5 if 2.0 a 6 clock
1315 if( (pci_read_config8(ctrl->d0, 0x78) & 0x30) ==0 ){
1316 dword &= ~(7<<24); /* CAS latency is 2.5, make 7 clks */
1320 * Back to Back Read Turn Around
1322 /* Set to a 3 clock back to back read turn around. This
1323 * is good for CAS latencys 2.5 and 2.0 */
1326 * Back to Back Read-Write Turn Around
1328 /* Set to a 5 clock back to back read to write turn around.
1329 * 4 is a good delay if the CAS latency is 2.0 */
1330 if( ( pci_read_config8(ctrl->d0, 0x78) & (1<<4)) == 0) {
1334 * Back to Back Write-Read Turn Around
1336 /* Set to a 2 clock back to back write to read turn around.
1337 * This is good for 2.5 and 2.0 CAS Latencies. */
1341 pci_write_config32(ctrl->d0, 0x78, dword);
1346 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1351 #if DEBUG_RAM_CONFIG
1352 print_debug("spd_detect_dimms:\r\n");
1354 for(i = 0; i < DIMM_SOCKETS; i++) {
1357 #if DEBUG_RAM_CONFIG
1358 print_debug_hex32(i);
1359 print_debug("\r\n");
1361 device = ctrl->channel0[i];
1363 byte = spd_read_byte(ctrl->channel0[i], 2); /* Type */
1365 dimm_mask |= (1 << i);
1369 device = ctrl->channel1[i];
1371 byte = spd_read_byte(ctrl->channel1[i], 2);
1373 dimm_mask |= (1 << (i + DIMM_SOCKETS));
1379 i = (dimm_mask>>DIMM_SOCKETS);
1380 if(i != (dimm_mask & ( (1<<DIMM_SOCKETS) - 1) ) ) {
1381 die("now we only support dual channel\r\n");
1389 static uint32_t set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, uint32_t memsz, unsigned index)
1392 uint32_t base0, base1;
1396 /* Double the size if we are using dual channel memory */
1397 // if (is_dual_channel(ctrl)) {
1398 /* Since I have 2 identical channels double the sizes */
1403 if (sz.side1 != sz.side2) {
1407 /* Make certain side1 of the dimm is at least 64MB */
1408 if (sz.side1 >= (25 + 4)) {
1409 memsz += (1 << (sz.side1 - (25 + 4)) ) ;
1411 /* Write the size of side 1 of the dimm */
1413 pci_write_config8(ctrl->d0, 0x60+(index<<1), byte);
1415 /* Make certain side2 of the dimm is at least 64MB */
1416 if (sz.side2 >= (25 + 4)) {
1417 memsz += (1 << (sz.side2 - (25 + 4)) ) ;
1420 /* Write the size of side 2 of the dimm */
1422 pci_write_config8(ctrl->d0, 0x61+(index<<1), byte);
1424 /* now, fill in DRBs where no physical slot exists */
1426 for(i=index+1;i<4;i++) {
1427 pci_write_config8(ctrl->d0, 0x60+(i<<1),byte);
1428 pci_write_config8(ctrl->d0, 0x61+(i<<1),byte);
1435 /* LAST_DRB_SLOT is a constant for any E7500 board */
1436 #define LAST_DRB_SLOT 0x67
1438 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
1444 for(i = 0; i < DIMM_SOCKETS; i++) {
1445 struct dimm_size sz;
1446 if (!(dimm_mask & (1 << i))) {
1449 sz = spd_get_dimm_size(ctrl->channel0[i]);
1450 #if DEBUG_RAM_CONFIG
1451 print_debug("dimm size =");
1452 print_debug_hex32(sz.side1);
1454 print_debug_hex32(sz.side2);
1455 print_debug("\r\n");
1458 if (sz.side1 == 0) {
1459 return -1; /* Report SPD error */
1461 memsz = set_dimm_size(ctrl, sz, memsz, i);
1463 /* For now hardset everything at 128MB boundaries */
1464 /* %ebp has the ram size in multiples of 64MB */
1465 // cmpl $0, %ebp /* test if there is no mem - smbus went bad */
1466 // jz no_memory_bad_smbus
1468 /* I should really adjust all of this in C after I have resources
1469 * to all of the pcie devices.
1472 /* Round up to 128M granularity */
1477 pci_write_config16(ctrl->d0, 0xc4, word);
1480 /* FIXME will this work with 3.5G of ram? */
1481 /* Put TOLM at 3G */
1482 pci_write_config16(ctrl->d0, 0xc4, 0xc000);
1483 /* Hard code a 1G remap window, right after the ram */
1485 word = 0x40; /* Ensure we are over 4G */
1489 pci_write_config16(ctrl->d0, 0xc6, word);
1491 pci_write_config16(ctrl->d0, 0xc8, word);
1498 static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
1500 #if DEBUG_RAM_CONFIG
1501 print_debug(spd_pre_init);
1503 //activate_spd_rom(ctrl);
1504 dimm_mask = spd_detect_dimms(ctrl);
1505 if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
1506 print_debug("No memory for this controller\n");
1509 dimm_mask = spd_enable_clocks(ctrl, dimm_mask);
1512 //spd_verify_dimms(ctrl);
1513 #if DEBUG_RAM_CONFIG
1514 print_debug(spd_pre_set);
1516 dimm_mask = spd_set_row_attributes(ctrl,dimm_mask);
1519 dimm_mask = spd_set_dram_controller_mode(ctrl,dimm_mask);
1522 dimm_mask = spd_set_cas_latency(ctrl,dimm_mask);
1525 dimm_mask = spd_set_dram_timing(ctrl,dimm_mask);
1528 #if DEBUG_RAM_CONFIG
1529 print_debug(spd_post_init);
1531 //moved from dram_post_init
1532 spd_set_ram_size(ctrl, dimm_mask);
1535 /* Unrecoverable error reading SPD data */
1536 print_err("SPD error - reset\r\n");
1543 static void ram_postinit(const struct mem_controller *ctrl) {
1544 #if DEBUG_RAM_CONFIG
1547 /* Include a test to verify that memory is more or less working o.k.
1548 * This test is to catch programming errors and hardware that is out of
1549 * spec, not a test to see if the memory dimms are working 100%
1551 //# CALL_LABEL(verify_ram)
1552 spd_set_ram_size(ctrl);
1554 #define FIRST_NORMAL_REFERENCE() CALL_LABEL(ram_postinit)
1556 #define SPECIAL_FINISHUP() CALL_LABEL(dram_finish)
1560 #define ecc_pre_init "Initializing ECC state...\r\n"
1561 #define ecc_post_init "ECC state initialized.\r\n"
1562 static void dram_finish(const struct mem_controller *ctrl)
1566 /* Test to see if ECC support is enabled */
1567 dword = pci_read_config32(ctrl->d0, 0x7c);
1572 #if DEBUG_RAM_CONFIG
1573 print_debug(ecc_pre_init);
1575 /* Initialize ECC bits , use ECC zero mode (new to 7501)*/
1576 pci_write_config8(ctrl->d0, 0x52, 0x06);
1577 pci_write_config8(ctrl->d0, 0x52, 0x07);
1579 byte = pci_read_config8(ctrl->d0, 0x52);
1581 } while ( (byte & 0x08 ) == 0);
1583 pci_write_config8(ctrl->d0, 0x52, byte & 0xfc);
1584 #if DEBUG_RAM_CONFIG
1585 print_debug(ecc_post_init);
1588 /* Clear the ECC error bits */
1589 pci_write_config8(ctrl->d0f1, 0x80, 0x03); /* dev 0, function 1, offset 80 */
1590 pci_write_config8(ctrl->d0f1, 0x82, 0x03); /* dev 0, function 1, offset 82 */
1592 pci_write_config32(ctrl->d0f1, 0x40, 1<<18); /* clear dev 0, function 1, offset 40; bit 18 by writing a 1 to it */
1593 pci_write_config32(ctrl->d0f1, 0x44, 1<<18); /* clear dev 0, function 1, offset 44; bit 18 by writing a 1 to it */
1595 pci_write_config8(ctrl->d0, 0x52, 0x0d);
1598 dword = pci_read_config32(ctrl->d0, 0x7c); /* FCS_EN */
1600 pci_write_config32(ctrl->d0, 0x7c, dword);
1603 #if DEBUG_RAM_CONFIG >= 2
1610 #if ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG
1611 #define ram_enable_1 "Ram Enable 1\r\n"
1612 #define ram_enable_2 "Ram Enable 2\r\n"
1613 #define ram_enable_3 "Ram Enable 3\r\n"
1614 #define ram_enable_4 "Ram Enable 4\r\n"
1615 #define ram_enable_5 "Ram Enable 5\r\n"
1616 #define ram_enable_6 "Ram Enable 6\r\n"
1617 #define ram_enable_7 "Ram Enable 7\r\n"
1618 #define ram_enable_8 "Ram Enable 8\r\n"
1619 #define ram_enable_9 "Ram Enable 9\r\n"
1620 #define ram_enable_10 "Ram Enable 10\r\n"
1621 #define ram_enable_11 "Ram Enable 11\r\n"
1624 /* Estimate that SLOW_DOWN_IO takes about 50&76us*/
1625 /* delay for 200us */
1628 static void do_delay(void)
1631 for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
1633 #define DO_DELAY do_delay();
1639 #define EXTRA_DELAY DO_DELAY
1641 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1644 /* 1 & 2 Power up and start clocks */
1645 #if DEBUG_RAM_CONFIG
1646 print_debug(ram_enable_1);
1647 print_debug(ram_enable_2);
1650 /* A 200us delay is needed */
1656 #if DEBUG_RAM_CONFIG
1657 print_debug(ram_enable_3);
1662 /* 4 Precharge all */
1663 #if DEBUG_RAM_CONFIG
1664 print_debug(ram_enable_4);
1666 RAM_PRECHARGE(ctrl);
1669 /* wait until the all banks idle state... */
1670 /* 5. Issue EMRS to enable DLL */
1671 #if DEBUG_RAM_CONFIG
1672 print_debug(ram_enable_5);
1678 #if DEBUG_RAM_CONFIG
1679 print_debug(ram_enable_6);
1684 /* Ensure a 200us delay between the DLL reset in step 6 and the final
1685 * mode register set in step 9.
1686 * Infineon needs this before any other command is sent to the ram.
1691 /* 7 Precharge all */
1692 #if DEBUG_RAM_CONFIG
1693 print_debug(ram_enable_7);
1695 RAM_PRECHARGE(ctrl);
1698 /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1699 #if DEBUG_RAM_CONFIG
1700 print_debug(ram_enable_8);
1706 /* And for good luck 6 more CBRs */
1720 /* 9 mode register set */
1721 #if DEBUG_RAM_CONFIG
1722 print_debug(ram_enable_9);
1727 /* 10 DDR Receive FIFO RE-Sync */
1728 #if DEBUG_RAM_CONFIG
1729 print_debug(ram_enable_10);
1731 RAM_RESET_DDR_PTR(ctrl);
1734 /* 11 normal operation */
1735 #if DEBUG_RAM_CONFIG
1736 print_debug(ram_enable_11);
1742 //FIRST_NORMAL_REFERENCE();
1743 //spd_set_ram_size(ctrl, 0x03);
1745 /* Finally enable refresh */
1746 ENABLE_REFRESH(ctrl);
1748 //SPECIAL_FINISHUP();