1 #include <console/console.h>
5 #include <part/sizeram.h>
6 #include <device/device.h>
7 #include <device/pci.h>
13 struct mem_range *sizeram(void)
15 static struct mem_range mem[4];
16 /* the units of tolm are 64 KB */
17 /* the units of drb16 are 64 MB */
18 uint16_t tolm, remapbase, remaplimit, drb16;
19 uint16_t tolm_r, remapbase_r, remaplimit_r;
24 dev = dev_find_slot(0, 0); // d0f0
26 printk_err("Cannot find PCI: 0:0\n");
30 /* Calculate and report the top of low memory and
33 /* Test if the remap memory high option is set */
35 // if(get_option(&remap_high, "remap_memory_high")){
38 printk_debug("remap_high is %d\n", remap_high);
39 /* get out the value of the highest DRB. This tells the end of
40 * physical memory. The units are ticks of 64 MB i.e. 1 means
43 drb = pci_read_config8(dev, 0x67);
44 drb16 = (uint16_t)drb;
45 if(remap_high && (drb16 > 0x08)) {
46 /* We only come here if we have at least 512MB of memory,
47 * so it is safe to hard code tolm.
52 /* i.e 0x40 * 0x40 is 0x1000 which is 4 GB */
54 /* There is more than 4GB of memory put
55 * the remap window at the end of ram.
58 remaplimit = remapbase + 0x38;
62 remaplimit = remapbase + (drb16-8);
66 tolm = (uint16_t)((dev_root.resource[1].base >> 16)&0x0f800);
67 if((tolm>>8) >= (drb16<<2)) {
74 remaplimit = remapbase + ((0x0040-(tolm>>10))-1);
77 /* Write the ram configruation registers,
78 * preserving the reserved bits.
80 tolm_r = pci_read_config16(dev, 0xc4);
81 tolm |= (tolm_r & 0x7ff);
82 pci_write_config16(dev, 0xc4, tolm);
83 remapbase_r = pci_read_config16(dev, 0xc6);
84 remapbase |= (remapbase_r & 0xfc00);
85 pci_write_config16(dev, 0xc6, remapbase);
86 remaplimit_r = pci_read_config16(dev, 0xc8);
87 remaplimit |= (remaplimit_r & 0xfc00);
88 pci_write_config16(dev, 0xc8, remaplimit);
91 printk_debug("mem info tolm = %x, drb = %x, pci_memory_base = %x, remap = %x-%x\n",tolm,drb,pci_memory_base,remapbase,remaplimit);
97 /* Convert size in 64K bytes to size in K bytes */
98 mem[1].sizek = (tolm << 6) - mem[1].basek;
101 if ((drb << 16) > (tolm << 6)) {
102 /* We don't need to consider the remap window
103 * here because we put it immediately after the
105 * All we must do is calculate the amount
106 * of unused memory and report it at 4GB.
108 mem[2].basek = 4096*1024;
109 mem[2].sizek = (drb << 16) - (tolm << 6);
118 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
120 static void pci_domain_read_resources(device_t dev)
122 struct resource *resource;
125 /* Initialize the system wide io space constraints */
126 resource = new_resource(dev, 0);
127 resource->base = 0x400;
128 resource->limit = 0xffffUL;
129 resource->flags = IORESOURCE_IO;
130 compute_allocate_resource(&dev->link[0], resource,
131 IORESOURCE_IO, IORESOURCE_IO);
133 /* Initialize the system wide prefetchable memory resources constraints */
134 resource = new_resource(dev, 1);
135 resource->limit = 0xfcffffffffULL;
136 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
137 compute_allocate_resource(&dev->link[0], resource,
138 IORESOURCE_MEM | IORESOURCE_PREFETCH,
139 IORESOURCE_MEM | IORESOURCE_PREFETCH);
141 /* Initialize the system wide memory resources constraints */
142 resource = new_resource(dev, 2);
143 resource->limit = 0xfcffffffffULL;
144 resource->flags = IORESOURCE_MEM;
145 compute_allocate_resource(&dev->link[0], resource,
146 IORESOURCE_MEM | IORESOURCE_PREFETCH,
150 static void ram_resource(device_t dev, unsigned long index,
151 unsigned long basek, unsigned long sizek)
153 struct resource *resource;
158 resource = new_resource(dev, index);
159 resource->base = ((resource_t)basek) << 10;
160 resource->size = ((resource_t)sizek) << 10;
161 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
162 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
165 static void pci_domain_set_resources(device_t dev)
167 struct resource *io, *mem1, *mem2;
168 struct resource *resource, *last;
169 unsigned long mmio_basek;
173 unsigned basek, sizek;
174 device_t dev_memctrl;
177 /* Place the IO devices somewhere safe */
178 io = find_resource(dev, 0);
179 io->base = DEVICE_IO_START;
182 /* Now reallocate the pci resources memory with the
183 * highest addresses I can manage.
185 mem1 = find_resource(dev, 1);
186 mem2 = find_resource(dev, 2);
189 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
190 mem1->base, mem1->limit, mem1->size, mem1->align);
191 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
192 mem2->base, mem2->limit, mem2->size, mem2->align);
195 /* See if both resources have roughly the same limits */
196 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
197 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
199 /* If so place the one with the most stringent alignment first
201 if (mem2->align > mem1->align) {
202 struct resource *tmp;
207 /* Now place the memory as high up as it will go */
208 mem2->base = resource_max(mem2);
209 mem1->limit = mem2->base - 1;
210 mem1->base = resource_max(mem1);
213 /* Place the resources as high up as they will go */
214 mem2->base = resource_max(mem2);
215 mem1->base = resource_max(mem1);
219 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
220 mem1->base, mem1->limit, mem1->size, mem1->align);
221 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
222 mem2->base, mem2->limit, mem2->size, mem2->align);
225 pci_tolm = 0xffffffffUL;
226 last = &dev->resource[dev->resources];
227 for(resource = &dev->resource[0]; resource < last; resource++)
230 resource->flags |= IORESOURCE_ASSIGNED;
231 resource->flags &= ~IORESOURCE_STORED;
233 compute_allocate_resource(&dev->link[0], resource,
234 BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
236 resource->flags |= IORESOURCE_STORED;
237 report_resource_stored(dev, resource, "");
239 if ((resource->flags & IORESOURCE_MEM) &&
240 (pci_tolm > resource->base))
242 pci_tolm = resource->base;
246 #warning "FIXME handle interleaved nodes"
247 mmio_basek = pci_tolm >> 10;
248 /* Round mmio_basek to something the processor can support */
249 mmio_basek &= ~((1 << 6) -1);
252 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
253 /* Round the mmio hold to 64M */
254 mmio_basek &= ~((64*1024) - 1);
257 dev_memctrl = dev_find_slot(0, 0); // d0f0
258 drb = pci_read_config8(dev_memctrl, 0x67);
264 ram_resource(dev, idx++, basek, sizek);
267 sizek = mmio_basek - basek;
268 ram_resource(dev, idx++, basek, sizek);
270 if ((drb << 16) > mmio_basek) {
271 /* We don't need to consider the remap window
272 * here because we put it immediately after the
274 * All we must do is calculate the amount
275 * of unused memory and report it at 4GB.
278 sizek = (drb << 16) - mmio_basek;
279 ram_resource(dev, idx++, basek, sizek);
282 assign_resources(&dev->link[0]);
285 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
287 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
291 static struct device_operations pci_domain_ops = {
292 .read_resources = pci_domain_read_resources,
293 .set_resources = pci_domain_set_resources,
294 .enable_resources = enable_childrens_resources,
296 .scan_bus = pci_domain_scan_bus,
299 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
305 /* Find which cpus are present */
306 cpu_bus = &dev->link[0];
307 for(i = 0; i < 7; i+=6) {
309 struct device_path cpu_path;
311 //How to identify Intel CPU
312 /* Find the cpu's memory controller */
313 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
316 /* Build the cpu device path */
317 cpu_path.type = DEVICE_PATH_APIC;
318 cpu_path.u.apic.apic_id = i;
320 /* See if I can find the cpu */
321 cpu = find_dev_path(cpu_bus, &cpu_path);
323 /* Enable the cpu if I have the processor */
324 if (dev && dev->enabled) {
326 cpu = alloc_dev(cpu_bus, &cpu_path);
333 /* Disable the cpu if I don't have the processor */
334 if (cpu && (!dev || !dev->enabled)) {
340 /* Report what I have done */
342 printk_debug("CPU: %s %s\n",
343 dev_path(cpu), cpu->enabled?"enabled":"disabled");
349 static void cpu_bus_init(device_t dev)
351 initialize_cpus(&dev->link[0]);
354 static void cpu_bus_noop(device_t dev)
358 static struct device_operations cpu_bus_ops = {
359 .read_resources = cpu_bus_noop,
360 .set_resources = cpu_bus_noop,
361 .enable_resources = cpu_bus_noop,
362 .init = cpu_bus_init,
363 .scan_bus = cpu_bus_scan,
366 static void enable_dev(struct device *dev)
368 struct device_path path;
370 /* Set the operations if it is a special bus type */
371 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
372 dev->ops = &pci_domain_ops;
374 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
375 dev->ops = &cpu_bus_ops;
378 struct chip_operations northbridge_intel_e7501_ops = {
379 .name = "intel E7501 Northbridge",
380 .enable_dev = enable_dev,