src/northbridge/intel/e7501/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <bitops.h>
   9 #include "chip.h"
  10
  11 static void pci_domain_read_resources(device_t dev)
  12 {
  13         struct resource *resource;
  14         unsigned reg;
  15
  16         /* Initialize the system wide io space constraints */
  17         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  18         resource->limit = 0xffffUL;
  19         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  20
  21         /* Initialize the system wide memory resources constraints */
  22         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  23         resource->limit = 0xffffffffULL;
  24         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  25 }
  26
  27 static void ram_resource(device_t dev, unsigned long index,
  28         unsigned long basek, unsigned long sizek)
  29 {
  30         struct resource *resource;
  31
  32         if (!sizek) {
  33                 return;
  34         }
  35         resource = new_resource(dev, index);
  36         resource->base  = ((resource_t)basek) << 10;
  37         resource->size  = ((resource_t)sizek) << 10;
  38         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  39                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  40 }
  41
  42 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  43 {
  44         struct resource **best_p = gp;
  45         struct resource *best;
  46         best = *best_p;
  47         if (!best || (best->base > new->base)) {
  48                 best = new;
  49         }
  50         *best_p = best;
  51 }
  52
  53 static uint32_t find_pci_tolm(struct bus *bus)
  54 {
  55         struct resource *min;
  56         uint32_t tolm;
  57         min = 0;
  58         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  59         tolm = 0xffffffffUL;
  60         if (min && tolm > min->base) {
  61                 tolm = min->base;
  62         }
  63         return tolm;
  64 }
  65
  66 static void pci_domain_set_resources(device_t dev)
  67 {
  68         device_t mc_dev;
  69         uint32_t pci_tolm;
  70
  71         pci_tolm = find_pci_tolm(&dev->link[0]);
  72         mc_dev = dev->link[0].children;
  73         if (mc_dev) {
  74                 /* Figure out which areas are/should be occupied by RAM.
  75                  * This is all computed in kilobytes and converted to/from
  76                  * the memory controller right at the edges.
  77                  * Having different variables in different units is
  78                  * too confusing to get right.  Kilobytes are good up to
  79                  * 4 Terabytes of RAM...
  80                  */
  81                 uint16_t tolm_r, remapbase_r, remaplimit_r;
  82                 unsigned long tomk, tolmk;
  83                 unsigned long remapbasek, remaplimitk;
  84                 int idx;
  85
  86                 /* Get the value of the highest DRB. This tells the end of
  87                  * the physical memory.  The units are ticks of 64MB
  88                  * i.e. 1 means 64MB.
  89                  */
  90                 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
  91                 /* Compute the top of Low memory */
  92                 tolmk = pci_tolm >> 10;
  93                 if (tolmk >= tomk) {
  94                         /* The PCI hole does not overlap memory
  95                          * we won't use the remap window.
  96                          */
  97                         tolmk = tomk;
  98                         remapbasek   = 0x3ff << 16;
  99                         remaplimitk  = 0 << 16;
 100                 }
 101                 else {
 102                         /* The PCI memory hole overlaps memory
 103                          * setup the remap window.
 104                          */
 105                         /* Find the bottom of the remap window
 106                          * is it above 4G?
 107                          */
 108                         remapbasek = 4*1024*1024;
 109                         if (tomk > remapbasek) {
 110                                 remapbasek = tomk;
 111                         }
 112                         /* Find the limit of the remap window */
 113                         remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 114                 }
 115                 /* Write the ram configuration registers,
 116                  * preserving the reserved bits.
 117                  */
 118                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 119                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 120                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 121
 122                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 123                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 124                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 125
 126                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 127                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 128                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 129
 130                 /* Report the memory regions */
 131                 idx = 10;
 132                 ram_resource(dev, idx++, 0, 640);
 133                 ram_resource(dev, idx++, 768, tolmk - 768);
 134                 if (tomk > 4*1024*1024) {
 135                         ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
 136                 }
 137                 if (remaplimitk >= remapbasek) {
 138                         ram_resource(dev, idx++, remapbasek,
 139                                 (remaplimitk + 64*1024) - remapbasek);
 140                 }
 141         }
 142         assign_resources(&dev->link[0]);
 143 }
 144
 145 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 146 {
 147         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 148         return max;
 149 }
 150
 151 static struct device_operations pci_domain_ops = {
 152         .read_resources   = pci_domain_read_resources,
 153         .set_resources    = pci_domain_set_resources,
 154         .enable_resources = enable_childrens_resources,
 155         .init             = 0,
 156         .scan_bus         = pci_domain_scan_bus,
 157         .ops_pci_bus      = &pci_cf8_conf1,
 158 };
 159
 160 static void cpu_bus_init(device_t dev)
 161 {
 162         initialize_cpus(&dev->link[0]);
 163 }
 164
 165 static void cpu_bus_noop(device_t dev)
 166 {
 167 }
 168
 169 static struct device_operations cpu_bus_ops = {
 170         .read_resources   = cpu_bus_noop,
 171         .set_resources    = cpu_bus_noop,
 172         .enable_resources = cpu_bus_noop,
 173         .init             = cpu_bus_init,
 174         .scan_bus         = 0,
 175 };
 176
 177 static void enable_dev(struct device *dev)
 178 {
 179         /* Set the operations if it is a special bus type */
 180         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 181                 dev->ops = &pci_domain_ops;
 182         }
 183         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 184                 dev->ops = &cpu_bus_ops;
 185         }
 186 }
 187
 188 struct chip_operations northbridge_intel_e7501_ops = {
 189         CHIP_NAME("Intel E7501 northbridge")
 190 };