src/northbridge/emulation/qemu-i386/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/hypertransport.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "northbridge.h"
  12
  13 void hard_reset(void)
  14 {
  15         printk_err("Hard_RESET!!!\n");
  16 }
  17
  18 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  19
  20 static void pci_domain_read_resources(device_t dev)
  21 {
  22         struct resource *resource;
  23         unsigned reg;
  24
  25         /* Initialize the system wide io space constraints */
  26         resource = new_resource(dev, 0);
  27         resource->base  = 0x400;
  28         resource->limit = 0xffffUL;
  29         resource->flags = IORESOURCE_IO;
  30         compute_allocate_resource(&dev->link[0], resource,
  31                 IORESOURCE_IO, IORESOURCE_IO);
  32
  33         /* Initialize the system wide memory resources constraints */
  34         resource = new_resource(dev, 1);
  35         resource->limit = 0xffffffffULL;
  36         resource->flags = IORESOURCE_MEM;
  37         compute_allocate_resource(&dev->link[0], resource,
  38                 IORESOURCE_MEM, IORESOURCE_MEM);
  39 }
  40
  41 static void ram_resource(device_t dev, unsigned long index,
  42         unsigned long basek, unsigned long sizek)
  43 {
  44         struct resource *resource;
  45
  46         if (!sizek) {
  47                 return;
  48         }
  49         resource = new_resource(dev, index);
  50         resource->base  = ((resource_t)basek) << 10;
  51         resource->size  = ((resource_t)sizek) << 10;
  52         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  53                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  54 }
  55
  56
  57 static void pci_domain_set_resources(device_t dev)
  58 {
  59         struct resource *resource, *last;
  60         device_t mc_dev;
  61         uint32_t pci_tolm;
  62         uint32_t idx;
  63
  64         pci_tolm = 0xffffffffUL;
  65         last = &dev->resource[dev->resources];
  66         for(resource = &dev->resource[0]; resource < last; resource++)
  67         {
  68                 compute_allocate_resource(&dev->link[0], resource,
  69                         BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
  70
  71                 resource->flags |= IORESOURCE_STORED;
  72                 report_resource_stored(dev, resource, "");
  73
  74                 if ((resource->flags & IORESOURCE_MEM) &&
  75                         (pci_tolm > resource->base))
  76                 {
  77                         pci_tolm = resource->base;
  78                 }
  79         }
  80
  81
  82         mc_dev = dev->link[0].children;
  83         if (mc_dev) {
  84                 unsigned long tomk, tolmk;
  85                 /* Hard code the Top of memory for now */
  86                 tomk = 65536;
  87                 /* Compute the top of Low memory */
  88                 tolmk = pci_tolm >> 10;
  89                 if (tolmk >= tomk) {
  90                         /* The PCI hole does not overlap memory.
  91                          */
  92                         tolmk = tomk;
  93                 }
  94
  95                 /* Report the memory regions */
  96                 idx = 10;
  97                 ram_resource(dev, idx++, 0, 640);
  98                 ram_resource(dev, idx++, 768, tolmk - 768);
  99                 if (tomk > 4*1024*1024) {
 100                         ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
 101                 }
 102         }
 103         assign_resources(&dev->link[0]);
 104 }
 105
 106 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 107 {
 108         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 109         return max;
 110 }
 111
 112 static struct device_operations pci_domain_ops = {
 113         .read_resources   = pci_domain_read_resources,
 114         .set_resources    = pci_domain_set_resources,
 115         .enable_resources = enable_childrens_resources,
 116         .init             = 0,
 117         .scan_bus         = pci_domain_scan_bus,
 118 };
 119
 120 static void enable_dev(struct device *dev)
 121 {
 122         struct device_path path;
 123
 124         /* Set the operations if it is a special bus type */
 125         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 126                 dev->ops = &pci_domain_ops;
 127         }
 128 }
 129
 130 struct chip_operations northbridge_emulation_qemu_i386_ops = {
 131         // .name      = "QEMU Northbridge",
 132         .enable_dev = enable_dev,
 133 };