src/northbridge/emulation/qemu-i386/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <mem.h>
   5 #include <part/sizeram.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/hypertransport.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <bitops.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14
  15 void hard_reset(void)
  16 {
  17         printk_err("Hard_RESET!!!\n");
  18 }
  19
  20 struct mem_range *sizeram(void)
  21 {
  22         unsigned long mmio_basek;
  23         static struct mem_range mem[10];
  24         device_t dev;
  25         int i, idx;
  26         unsigned char rambits;
  27
  28         dev = dev_find_slot(0, 0);
  29         if (!dev) {
  30                 printk_err("Cannot find PCI: 0:0\n");
  31                 return 0;
  32         }
  33         mem[0].basek = 0;
  34         mem[0].sizek = 65536;
  35 #if 0
  36         idx = 1;
  37         while(idx < sizeof(mem)/sizeof(mem[0])) {
  38                 mem[idx].basek = 0;
  39                 mem[idx].sizek = 0;
  40                 idx++;
  41         }
  42         for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
  43                 unsigned char reg;
  44                 reg = pci_read_config8(dev, ramregs[i]);
  45                 /* these are ENDING addresses, not sizes.
  46                  * if there is memory in this slot, then reg will be > rambits.
  47                  * So we just take the max, that gives us total.
  48                  * We take the highest one to cover for once and future linuxbios
  49                  * bugs. We warn about bugs.
  50                  */
  51                 if (reg > rambits)
  52                         rambits = reg;
  53                 if (reg < rambits)
  54                         printk_err("ERROR! register 0x%x is not set!\n",
  55                                 ramregs[i]);
  56         }
  57
  58         printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
  59         mem[0].sizek = rambits*8*1024;
  60 #endif
  61 #if 1
  62         for(i = 0; i < idx; i++) {
  63                 printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
  64                         i, mem[i].basek, i, mem[i].sizek);
  65         }
  66 #endif
  67
  68         return mem;
  69 }
  70
  71 static void enumerate(struct chip *chip)
  72 {
  73         extern struct device_operations default_pci_ops_bus;
  74         chip_enumerate(chip);
  75         chip->dev->ops = &default_pci_ops_bus;
  76 }
  77
  78 static void random_fixup() {
  79         device_t pcidev = dev_find_slot(0, 0);
  80
  81         printk_warning("QEMU random fixup ...\n");
  82         if (pcidev) {
  83                 // pci_write_config8(pcidev, 0x0, 0x0);
  84         }
  85 }
  86
  87 static void northbridge_init(struct chip *chip, enum chip_pass pass)
  88 {
  89
  90         struct northbridge_dummy_qemu_i386_config *conf =
  91                 (struct northbridge_dummy_qemu_i386_config *)chip->chip_info;
  92
  93         switch (pass) {
  94         case CONF_PASS_PRE_PCI:
  95                 break;
  96
  97         case CONF_PASS_POST_PCI:
  98                 break;
  99
 100         case CONF_PASS_PRE_BOOT:
 101                 random_fixup();
 102                 break;
 103
 104         default:
 105                 /* nothing yet */
 106                 break;
 107         }
 108 }
 109
 110 struct chip_control northbridge_emulation_qemu_i386_control = {
 111         .enumerate = enumerate,
 112         .enable    = northbridge_init,
 113         .name      = "QEMU Northbridge",
 114 };