2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <cpu/amd/lxdef.h>
23 #include "southbridge/amd/cs5536/cs5536.h"
25 static const unsigned char NumColAddr[] = {
26 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
27 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
30 static void auto_size_dimm(unsigned int dimm)
32 uint32_t dimm_setting;
39 /* Check that we have a dimm */
40 if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
44 /* Field: Module Banks per DIMM */
45 /* EEPROM byte usage: (5) Number of DIMM Banks */
46 spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
47 if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
48 print_debug("Number of module banks not compatible\n");
49 POST_CODE(ERROR_BANK_SET);
50 __asm__ __volatile__("hlt\n");
52 dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
54 /* Field: Banks per SDRAM device */
55 /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
56 spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
57 if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
58 print_debug("Number of device banks not compatible\n");
59 POST_CODE(ERROR_BANK_SET);
60 __asm__ __volatile__("hlt\n");
62 dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
65 *; EEPROM byte usage: (3) Number or Row Addresses
66 *; (4) Number of Column Addresses
67 *; (5) Number of DIMM Banks
68 *; (31) Module Bank Density
69 *; Size = Module Density * Module Banks
71 if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
72 || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
73 print_debug("Assymetirc DIMM not compatible\n");
74 POST_CODE(ERROR_UNSUPPORTED_DIMM);
75 __asm__ __volatile__("hlt\n");
78 dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
79 dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
80 dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
82 /* Module Density * Module Banks */
83 dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
84 dimm_size = __builtin_ctz(dimm_size);
85 if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
86 print_debug("Only support up to 1 GB per DIMM\n");
87 POST_CODE(ERROR_DENSITY_DIMM);
88 __asm__ __volatile__("hlt\n");
90 dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
93 *; EEPROM byte usage: (4) Number of Column Addresses
94 *; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
96 *; But this really works by magic.
97 *;If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address
98 *;that MC generates, here is how the MC assigns the pa onto the ma pins:
100 *;ma 12 11 10 09 08 07 06 05 04 03 02 01 00
101 *;-------------------------------------------
102 *;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
103 *;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
104 *;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
105 *;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
106 *;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
107 *;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size)
108 *; *AP=autoprecharge bit
110 *;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
111 *;so lower 3 address bits are dont_cares.So from the table above,
112 *;it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
113 *;it adds 3 to get 10, then does 2^10=1K. Get it?*/
115 spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
116 if (spd_byte > MAX_COL_ADDR) {
117 print_debug("DIMM page size not compatible\n");
118 POST_CODE(ERROR_SET_PAGE);
119 __asm__ __volatile__("hlt\n");
122 if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */
123 spd_byte = 7; /* which means >32k so set to disabled */
125 dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
127 msr = rdmsr(MC_CF07_DATA);
129 msr.hi &= 0xFFFF0000;
130 msr.hi |= dimm_setting;
132 msr.hi &= 0x0000FFFF;
133 msr.hi |= dimm_setting << 16;
135 wrmsr(MC_CF07_DATA, msr);
138 static void checkDDRMax(void)
140 uint8_t spd_byte0, spd_byte1;
143 /* PC133 identifier */
144 spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
145 if (spd_byte0 == 0xFF) {
148 spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
149 if (spd_byte1 == 0xFF) {
153 /* I don't think you need this check.
154 if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){
155 print_debug("DIMM overclocked. Check GeodeLink Speed\n");
156 POST_CODE(POST_PLL_MEM_FAIL);
157 __asm__ __volatile__("hlt\n");
160 /* Use the slowest DIMM */
161 if (spd_byte0 < spd_byte1) {
162 spd_byte0 = spd_byte1;
165 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
166 speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));
168 /* current speed > max speed? */
169 if (GeodeLinkSpeed() > speed) {
170 print_debug("DIMM overclocked. Check GeodeLink Speed\r\n");
171 POST_CODE(POST_PLL_MEM_FAIL);
172 __asm__ __volatile__("hlt\n");
176 const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
178 static void set_refresh_rate(void)
180 uint8_t spd_byte0, spd_byte1;
181 uint16_t rate0, rate1;
184 spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
189 rate0 = REF_RATE[spd_byte0];
191 spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
196 rate1 = REF_RATE[spd_byte1];
198 /* Use the faster rate (lowest number) */
203 msr = rdmsr(MC_CF07_DATA);
204 msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
205 << CF07_LOWER_REF_INT_SHIFT;
206 wrmsr(MC_CF07_DATA, msr);
209 const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
211 static void setCAS(void)
213 /*;*****************************************************************************
216 ;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
217 ;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
218 ;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
220 ;* The CAS setting is based on the information provided in each DIMMs SPD.
221 ;* The speed at which a DIMM can run is described relative to the slowest
222 ;* CAS the DIMM supports. Each speed for the relative CAS settings is
223 ;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
224 ;* speed, the CAS setting is removed from the list of good settings for
225 ;* the DIMM. This is done for both DIMMs and the lists are compared to
226 ;* find the lowest common CAS latency setting. If there are no CAS settings
227 ;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
230 ;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
231 ;* Destroys: We really use everything !
232 ;*****************************************************************************/
233 uint16_t glspeed, dimm_speed;
234 uint8_t spd_byte, casmap0, casmap1;
237 glspeed = GeodeLinkSpeed();
239 /************************** DIMM0 **********************************/
240 casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
241 if (casmap0 != 0xFF) {
242 /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
243 spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
245 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
246 dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) +
248 if (dimm_speed >= glspeed) {
249 /* IF -1 timing is supported, check -1 timing > GeodeLink */
250 spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
252 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
253 dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
254 if (dimm_speed <= glspeed) {
255 /* set we can use -.5 timing but not -1 */
256 spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
257 /* just want bits in the lower byte since we have to cast to a 32 */
258 casmap0 &= 0xFF << (--spd_byte);
260 } /*MIN_CYCLE_10 !=0 */
262 /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
263 spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
264 /* just want bits in the lower byte since we have to cast to a 32 */
265 casmap0 &= 0xFF << (spd_byte);
267 } /*MIN_CYCLE_05 !=0 */
268 } else { /* No DIMM */
272 /************************** DIMM1 **********************************/
273 casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES);
274 if (casmap1 != 0xFF) {
275 /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
276 spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND);
278 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
279 dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
280 if (dimm_speed >= glspeed) {
281 /* IF -1 timing is supported, check -1 timing > GeodeLink */
282 spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD);
284 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
285 dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
286 if (dimm_speed <= glspeed) {
287 /* set we can use -.5 timing but not -1 */
288 spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
289 /* just want bits in the lower byte since we have to cast to a 32 */
290 casmap1 &= 0xFF << (--spd_byte);
292 } /*MIN_CYCLE_10 !=0 */
294 /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
295 spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
296 /* just want bits in the lower byte since we have to cast to a 32 */
297 casmap1 &= 0xFF << (spd_byte);
299 } /*MIN_CYCLE_05 !=0 */
300 } else { /* No DIMM */
304 /********************* CAS_LAT MAP COMPARE ***************************/
306 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)];
307 } else if (casmap1 == 0) {
308 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
309 } else if ((casmap0 &= casmap1)) {
310 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
312 print_debug("DIMM CAS Latencies not compatible\r\n");
313 POST_CODE(ERROR_DIFF_DIMMS);
314 __asm__ __volatile__("hlt\n");
317 msr = rdmsr(MC_CF8F_DATA);
318 msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
319 msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
320 wrmsr(MC_CF8F_DATA, msr);
323 static void set_latencies(void)
325 uint32_t memspeed, dimm_setting;
326 uint8_t spd_byte0, spd_byte1;
329 memspeed = GeodeLinkSpeed() / 2;
334 spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
335 if (spd_byte0 == 0xFF) {
338 spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
339 if (spd_byte1 == 0xFF) {
342 if (spd_byte0 < spd_byte1) {
343 spd_byte0 = spd_byte1;
346 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
347 spd_byte1 = (spd_byte0 * memspeed) / 1000;
348 if (((spd_byte0 * memspeed) % 1000)) {
351 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
354 spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
355 if (spd_byte0 == 0xFF) {
358 spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
359 if (spd_byte1 == 0xFF) {
362 if (spd_byte0 < spd_byte1) {
363 spd_byte0 = spd_byte1;
366 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
367 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
368 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
371 dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
374 spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
375 if (spd_byte0 == 0xFF) {
378 spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
379 if (spd_byte1 == 0xFF) {
382 if (spd_byte0 < spd_byte1) {
383 spd_byte0 = spd_byte1;
386 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
387 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
388 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
391 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
394 spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
395 if (spd_byte0 == 0xFF) {
398 spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
399 if (spd_byte1 == 0xFF) {
402 if (spd_byte0 < spd_byte1) {
403 spd_byte0 = spd_byte1;
406 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
407 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
408 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
411 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
413 /* tRC = tRP + tRAS */
414 dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
415 ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
416 << CF8F_LOWER_ACT2ACTREF_SHIFT;
418 msr = rdmsr(MC_CF8F_DATA);
419 msr.lo &= 0xF00000FF;
420 msr.lo |= dimm_setting;
421 msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
422 wrmsr(MC_CF8F_DATA, msr);
424 /* MC_CF1017 setup */
426 spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC);
427 if (spd_byte0 == 0xFF) {
430 spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC);
431 if (spd_byte1 == 0xFF) {
434 if (spd_byte0 < spd_byte1) {
435 spd_byte0 = spd_byte1;
439 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
440 spd_byte1 = (spd_byte0 * memspeed) / 1000;
441 if (((spd_byte0 * memspeed) % 1000)) {
444 } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
445 spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
447 dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */
448 msr = rdmsr(MC_CF1017_DATA);
449 msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);
450 msr.lo |= dimm_setting;
451 wrmsr(MC_CF1017_DATA, msr);
453 /* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */
454 if (memspeed > 198) {
455 msr = rdmsr(MC_CF1017_DATA);
456 msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
457 msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT;
458 wrmsr(MC_CF1017_DATA, msr);
462 static void set_extended_mode_registers(void)
464 uint8_t spd_byte0, spd_byte1;
466 spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
467 if (spd_byte0 == 0xFF) {
470 spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
471 if (spd_byte1 == 0xFF) {
474 spd_byte1 &= spd_byte0;
476 msr = rdmsr(MC_CF07_DATA);
477 if (spd_byte1 & 1) { /* Drive Strength Control */
478 msr.lo |= CF07_LOWER_EMR_DRV_SET;
480 if (spd_byte1 & 2) { /* FET Control */
481 msr.lo |= CF07_LOWER_EMR_QFC_SET;
483 wrmsr(MC_CF07_DATA, msr);
486 static void EnableMTest(void)
490 msr = rdmsr(GLCP_DELAY_CONTROLS);
491 msr.hi &= ~(7 << 20); /* clear bits 54:52 */
492 if (GeodeLinkSpeed() < 200) {
495 wrmsr(GLCP_DELAY_CONTROLS, msr);
497 msr = rdmsr(MC_CFCLK_DBUG);
499 CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET |
500 CFCLK_UPPER_MTST_RBEX_EN_SET;
501 msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
502 wrmsr(MC_CFCLK_DBUG, msr);
504 print_debug("Enabled MTest for TLA debug\r\n");
507 static void sdram_set_registers(const struct mem_controller *ctrl)
512 /* Set Timing Control */
513 msrnum = MC_CF1017_DATA;
515 msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
516 if (GeodeLinkSpeed() < 334) {
517 msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
519 msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
523 /* Set Refresh Staggering */
524 msrnum = MC_CF07_DATA;
527 msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */
530 /* Memory Interleave: Set HOI here otherwise default is LOI */
531 /* msrnum = MC_CF8F_DATA;
533 msr.hi |= CF8F_UPPER_HOI_LOI_SET;
534 wrmsr(msrnum, msr); */
537 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
541 POST_CODE(POST_MEM_SETUP); // post_70h
543 spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
544 /* Check DIMM is not Register and not Buffered DIMMs. */
545 if ((spd_byte != 0xFF) && (spd_byte & 3)) {
546 print_debug("DIMM0 NOT COMPATIBLE\r\n");
547 POST_CODE(ERROR_UNSUPPORTED_DIMM);
548 __asm__ __volatile__("hlt\n");
550 spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
551 if ((spd_byte != 0xFF) && (spd_byte & 3)) {
552 print_debug("DIMM1 NOT COMPATIBLE\n");
553 POST_CODE(ERROR_UNSUPPORTED_DIMM);
554 __asm__ __volatile__("hlt\n");
557 POST_CODE(POST_MEM_SETUP2); // post_72h
559 /* Check that the memory is not overclocked. */
563 POST_CODE(POST_MEM_SETUP3); // post_73h
564 auto_size_dimm(DIMM0);
565 POST_CODE(POST_MEM_SETUP4); // post_74h
566 auto_size_dimm(DIMM1);
568 /* Set CAS latency */
569 POST_CODE(POST_MEM_SETUP5); // post_75h
572 /* Set all the other latencies here (tRAS, tRP....) */
575 /* Set Extended Mode Registers */
576 set_extended_mode_registers();
578 /* Set Memory Refresh Rate */
583 /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
584 * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
585 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
590 /*********************************************************************
591 ;* Turn on MC/DIMM interface per JEDEC
592 ;* 1) Clock stabilizes > 200us
594 ;* 3) Precharge All to put all banks into an idles state
595 ;* 4) EMRS to enable DLL
596 ;* 6) MRS w/ memory config & reset DLL set
597 ;* 7) Wait 200 clocks (2us)
598 ;* 8) Precharge All and 2 Auto refresh
599 ;* 9) MRS w/ memory config & reset DLL clear
600 ;* 8) DDR SDRAM ready for normal operation
601 ;********************************************************************/
602 POST_CODE(POST_MEM_ENABLE); // post_76h
604 /* Only enable MTest for TLA memory debug */
607 /* If both Page Size = "Not Installed" we have a problems and should halt. */
608 msr = rdmsr(MC_CF07_DATA);
609 if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
610 ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
611 print_debug("No memory in the system\r\n");
612 POST_CODE(ERROR_NO_DIMMS);
613 __asm__ __volatile__("hlt\n");
617 msrnum = MC_CFCLK_DBUG;
619 msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
622 /* Force Precharge All on next command, EMRS */
623 msrnum = MC_CFCLK_DBUG;
625 msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
628 /* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
629 msrnum = MC_CF07_DATA;
631 msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;
633 msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
636 /* Clear Force Precharge All */
637 msrnum = MC_CFCLK_DBUG;
639 msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
642 /* MRS Reset DLL - set */
643 msrnum = MC_CF07_DATA;
645 msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;
647 msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
650 /* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */
651 /* Wait 2 PORT61 ticks. between 15us and 30us */
652 /* This would be endless if the timer is stuck. */
653 while ((inb(0x61))) ; /* find the first edge */
654 while (!(~inb(0x61))) ;
656 /* Force Precharge All on the next command, auto-refresh */
657 msrnum = MC_CFCLK_DBUG;
659 msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
662 /* Manually AUTO refresh #1 */
663 /* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */
664 msrnum = MC_CF07_DATA;
666 msr.lo |= CF07_LOWER_REF_TEST_SET;
668 msr.lo &= ~CF07_LOWER_REF_TEST_SET;
671 /* Clear Force Precharge All */
672 msrnum = MC_CFCLK_DBUG;
674 msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
677 /* Manually AUTO refresh */
678 /* The MC should insert the right delay between the refreshes */
679 msrnum = MC_CF07_DATA;
681 msr.lo |= CF07_LOWER_REF_TEST_SET;
683 msr.lo &= ~CF07_LOWER_REF_TEST_SET;
686 /* MRS Reset DLL - clear */
687 msrnum = MC_CF07_DATA;
689 msr.lo |= CF07_LOWER_PROG_DRAM_SET;
691 msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
694 /* Allow MC to tristate during idle cycles with MTEST OFF */
695 msrnum = MC_CFCLK_DBUG;
697 msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
700 /* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */
701 msr = rdmsr(MC_CF07_DATA);
702 if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==
703 (7 << CF07_UPPER_D1_PSZ_SHIFT)) {
704 msrnum = GLCP_DELAY_CONTROLS;
706 msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */
710 /* Set PMode0 Sensitivity Counter */
711 msr.lo = 0; /* pmode 0=0 most aggressive */
712 msr.hi = 0x200; /* pmode 1=200h */
713 wrmsr(MC_CF_PMCTR, msr);
715 /* Set PMode1 Up delay enable */
716 msrnum = MC_CF1017_DATA;
718 msr.lo |= (209 << 8); /* bits[15:8] = 209 */
721 print_debug("DRAM controller init done.\n");
722 POST_CODE(POST_MEM_SETUP_GOOD); //0x7E
724 /* make sure there is nothing stale in the cache */
725 /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
727 /* The RAM dll needs a write to lock on so generate a few dummy writes */
728 /* Note: The descriptor needs to be enabled to point at memory */
729 volatile unsigned long *ptr;
730 for (i = 0; i < 5; i++) {
732 *ptr = (unsigned long)i;
734 /* SWAPSiF for PBZ 4112 (Errata 34) */
735 /* check for failed DLL settings now that we have done a memory write. */
736 msrnum = GLCP_DELAY_CONTROLS;
738 if ((msr.lo & 0x7FF) == 0x104) {
740 /* If you had it you would need to clear out the fail boot count flag */
741 /* (depending on where it counts from etc). */
743 /* The reset we are about to perform clears the PM_SSC register in the */
744 /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */
745 /* it would do a normal boot */
747 /* Reset the system */
748 msrnum = MDD_SOFT_RESET;
753 print_debug("RAM DLL lock\n");