2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 static void pll_reset(char manualconf)
23 msr_t msrGlcpSysRstpll;
25 msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
27 print_debug("_MSR GLCP_SYS_RSTPLL (");
28 print_debug_hex32(GLCP_SYS_RSTPLL);
29 print_debug(") value is: ");
30 print_debug_hex32(msrGlcpSysRstpll.hi);
32 print_debug_hex32(msrGlcpSysRstpll.lo);
34 POST_CODE(POST_PLL_INIT);
36 if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
37 print_debug("Configuring PLL\n");
39 POST_CODE(POST_PLL_MANUAL);
40 /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
41 msrGlcpSysRstpll.hi = PLLMSRhi;
43 /* Hold Count - how long we will sit in reset */
44 msrGlcpSysRstpll.lo = PLLMSRlo;
46 /*automatic configuration (straps) */
47 POST_CODE(POST_PLL_STRAP);
48 msrGlcpSysRstpll.lo &=
49 ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
50 msrGlcpSysRstpll.lo |=
51 (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
52 msrGlcpSysRstpll.lo &=
53 ~(RSTPPL_LOWER_COREBYPASS_SET |
54 RSTPPL_LOWER_MBBYPASS_SET);
55 msrGlcpSysRstpll.lo |=
56 RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
58 /* Use SWFLAGS to remember: "we've already been here" */
59 msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
61 /* "reset the chip" value */
62 msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
63 wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
65 /* You should never get here..... The chip has reset. */
66 print_debug("CONFIGURING PLL FAILURE\n");
67 POST_CODE(POST_PLL_RESET_FAIL);
68 __asm__ __volatile__("hlt\n");
71 print_debug("Done cpuRegInit\n");
75 static unsigned int CPUSpeed(void)
80 msr = rdmsr(GLCP_SYS_RSTPLL);
81 speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
82 if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
87 static unsigned int GeodeLinkSpeed(void)
92 msr = rdmsr(GLCP_SYS_RSTPLL);
93 speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
94 if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
99 static unsigned int PCISpeed(void)
103 msr = rdmsr(GLCP_SYS_RSTPLL);
104 if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {