1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
11 #include "northbridge.h"
12 #include <cpu/amd/gx2def.h>
13 #include <cpu/x86/msr.h>
14 #include <cpu/x86/cache.h>
16 #define NORTHBRIDGE_FILE "northbridge.c"
20 /* todo: add a resource record. We don't do this here because this may be called when
21 * very little of the platform is actually working.
30 msr = rdmsr(0x20000018);
31 printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
37 sizem = (1 << ((dimm >> 12)-1)) * 8;
44 sizem += (1 << ((dimm >> 12)-1)) * 8;
46 printk_debug("sizeram: sizem 0x%x\n", sizem);
51 /* here is programming for the various MSRs.*/
52 #define IM_QWAIT 0x100000
54 #define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
55 #define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
57 /* these are the 8-bit attributes for controlling RCONF registers */
58 #define CACHE_DISABLE (1<<0)
59 #define WRITE_ALLOCATE (1<<1)
60 #define WRITE_PROTECT (1<<2)
61 #define WRITE_THROUGH (1<<3)
62 #define WRITE_COMBINE (1<<4)
63 #define WRITE_SERIALIZE (1<<5)
65 /* ram has none of this stuff */
66 #define RAM_PROPERTIES (0)
67 #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
68 #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_THROUGH|CACHE_DISABLE)
69 #define MSR_WS_CD_DEFAULT (0x21212121)
71 /* 1810-1817 give you 8 registers with which to program protection regions */
72 /* the are region configuration range registers, or RRCF */
73 /* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
74 /* so no left-shift needed for top or base */
75 #define RRCF_LOW(base,properties) (base|(1<<8)|properties)
76 #define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)
78 /* build initializer for P2D MSR */
79 #define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
80 #define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
81 #define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
82 #define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
83 #define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
84 #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
85 #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
93 {0x1700, {.hi = 0, .lo = IM_QWAIT}},
94 {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}},
95 /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
96 /* for 180a, for now, we assume VSM will configure it */
97 /* 180b is left at reset value,a0000-bffff is non-cacheable */
98 /* 180c, c0000-dffff is set to write serialize and non-cachable */
99 /* oops, 180c will be set by cpu bug handling in cpubug.c */
100 //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
101 /* 180d is left at default, e0000-fffff is non-cached */
103 /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
104 /* we will not set 0x180f, the DMM,yet */
105 {0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
106 {0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
107 {0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
108 {0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
109 /* now for GLPCI routing */
111 P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
112 P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
113 P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0x3),
115 P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
116 P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
117 P2D_SC(0x4000002d, 0x1, 0x0, 0x0, 0xff03, 0x3),
123 setup_gx2_cache(void)
126 unsigned long long val;
127 int sizembytes, sizereg;
129 sizembytes = sizeram();
130 printk_debug("enable_cache: enable for %dm bytes\n", sizembytes);
131 /* build up the rconf word. */
132 /* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
134 val = ((unsigned long long) ROM_PROPERTIES) << 56;
135 /* make rom base useful for 1M roms */
136 /* Flash base address -- sized for 1/2M for now*/
137 val |= ((unsigned long long) 0xfff800)<<36;
138 /* set the devrp properties */
139 val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
140 /* sigh. Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
141 /* yank off 8M for frame buffer and 1M for VSA */
143 sizereg = sizembytes;
148 val |= RAM_PROPERTIES;
150 msr.hi = (val >> 32);
151 printk_debug("msr will be set to %x:%x\n", msr.hi, msr.lo);
152 wrmsr(CPU_RCONF_DEFAULT, msr);
159 #define SMM_OFFSET 0x40400000
162 /* we have to do this here. We have not found a nicer way to do it */
167 unsigned long tmp, tmp2, tmp3;
169 unsigned long sizem, membytes;
171 sizem = setup_gx2_cache();
173 membytes = sizem * 1048576;
175 /* we need to set 0x10000028 and 0x40000029 */
176 printk_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
177 msr.hi = 0x20000000 | membytes>>24;
178 msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
179 wrmsr(0x10000028, msr);
180 msr.hi = 0x20000000 | membytes>>24;
181 msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
182 wrmsr(0x40000029, msr);
183 msr = rdmsr(0x10000028);
184 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
185 msr = rdmsr(0x40000029);
186 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
189 /* fixme: SMM MSR 0x10000026 and 0x400000023 */
190 /* calculate the OFFSET field */
191 tmp = membytes - SMM_OFFSET;
195 tmp |= (SMM_OFFSET >> 24);
197 /* calculate the PBASE and PMASK fields */
198 tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
199 tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
200 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
203 wrmsr(0x10000026, msr);
207 wrmsr(0x10000028, msr);
208 msr = rdmsr(0x10000028);
209 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
210 wrmsr(0x40000029, msr);
211 msr = rdmsr(0x40000029);
212 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
216 wrmsr(0x10000026, msr);
217 msr = rdmsr(0x10000026);
218 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
224 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
226 /* now do the default MSR values */
227 for(i = 0; msr_defaults[i].msr_no; i++) {
229 wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);
230 msr = rdmsr(msr_defaults[i].msr_no);
231 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
236 static void optimize_xbus(device_t dev)
238 /* Optimise X-Bus performance */
239 pci_write_config8(dev, 0x40, 0x1e);
240 pci_write_config8(dev, 0x41, 0x52);
241 pci_write_config8(dev, 0x43, 0xc1);
242 pci_write_config8(dev, 0x44, 0x00);
245 static void enable_shadow(device_t dev)
250 static void northbridge_init(device_t dev)
252 printk_debug("northbridge: %s()\n", __FUNCTION__);
259 static struct device_operations northbridge_operations = {
260 .read_resources = pci_dev_read_resources,
261 .set_resources = pci_dev_set_resources,
262 .enable_resources = pci_dev_enable_resources,
263 .init = northbridge_init,
268 static struct pci_driver northbridge_driver __pci_driver = {
269 .ops = &northbridge_operations,
270 .vendor = PCI_VENDOR_ID_CYRIX,
271 .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
276 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
278 static void pci_domain_read_resources(device_t dev)
280 struct resource *resource;
282 printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
284 /* Initialize the system wide io space constraints */
285 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
286 resource->limit = 0xffffUL;
287 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
289 /* Initialize the system wide memory resources constraints */
290 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
291 resource->limit = 0xffffffffULL;
292 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
295 static void ram_resource(device_t dev, unsigned long index,
296 unsigned long basek, unsigned long sizek)
298 struct resource *resource;
303 resource = new_resource(dev, index);
304 resource->base = ((resource_t)basek) << 10;
305 resource->size = ((resource_t)sizek) << 10;
306 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
307 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
310 static void tolm_test(void *gp, struct device *dev, struct resource *new)
312 struct resource **best_p = gp;
313 struct resource *best;
315 if (!best || (best->base > new->base)) {
321 static uint32_t find_pci_tolm(struct bus *bus)
323 struct resource *min;
326 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
328 if (min && tolm > min->base) {
334 #define FRAMEBUFFERK 4096
336 static void pci_domain_set_resources(device_t dev)
341 pci_tolm = find_pci_tolm(&dev->link[0]);
342 mc_dev = dev->link[0].children;
344 unsigned int tomk, tolmk;
345 unsigned int ramreg = 0;
347 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
348 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
350 for(i=0; i<0x20; i+= 0x10) {
351 unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
352 unsigned int mem_config = *mcreg;
354 if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
356 ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
361 /* Sort out the framebuffer size */
362 tomk -= FRAMEBUFFERK;
363 *bcdramtop = ((tomk << 10) - 1);
364 *mcgbaseadd = (tomk >> 9);
366 printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
367 printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
369 printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
371 /* Compute the top of Low memory */
372 tolmk = pci_tolm >> 10;
374 /* The PCI hole does does not overlap the memory.
378 /* Report the memory regions */
380 ram_resource(dev, idx++, 0, tolmk);
382 assign_resources(&dev->link[0]);
386 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
388 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
392 static struct device_operations pci_domain_ops = {
393 .read_resources = pci_domain_read_resources,
394 .set_resources = pci_domain_set_resources,
395 .enable_resources = enable_childrens_resources,
397 .scan_bus = pci_domain_scan_bus,
400 static void cpu_bus_init(device_t dev)
402 initialize_cpus(&dev->link[0]);
405 static void cpu_bus_noop(device_t dev)
409 static struct device_operations cpu_bus_ops = {
410 .read_resources = cpu_bus_noop,
411 .set_resources = cpu_bus_noop,
412 .enable_resources = cpu_bus_noop,
413 .init = cpu_bus_init,
417 static void enable_dev(struct device *dev)
419 printk_debug("gx2 north: enable_dev\n");
420 /* Set the operations if it is a special bus type */
421 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
422 extern void cpubug(void);
423 printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
424 /* cpubug MUST be called before setup_gx2(), so we force the issue here */
427 /* do this here for now -- this chip really breaks our device model */
428 setup_realmode_idt();
430 dev->ops = &pci_domain_ops;
432 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
434 printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
435 dev->ops = &cpu_bus_ops;
439 struct chip_operations northbridge_amd_gx2_ops = {
440 CHIP_NAME("AMD GX2 Northbridge")
441 .enable_dev = enable_dev,