src/northbridge/amd/gx1/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "northbridge.h"
  12 #include <cpu/amd/gx1def.h>
  13 #include <cpu/x86/cache.h>
  14 #include <cpu/cpu.h>
  15
  16 #define NORTHBRIDGE_FILE "northbridge.c"
  17 /*
  18 */
  19
  20 static void optimize_xbus(device_t dev)
  21 {
  22         /* Optimise X-Bus performance */
  23         pci_write_config8(dev, 0x40, 0x1e);
  24         pci_write_config8(dev, 0x41, 0x52);
  25         pci_write_config8(dev, 0x43, 0xc1);
  26         pci_write_config8(dev, 0x44, 0x00);
  27 }
  28
  29 /**
  30  * Enables memory from 0xC0000 up to 0xFFFFF.
  31  * So this region is read/write and cache able
  32  *
  33  * FIXME: What about PCI master access into
  34  *        this region?
  35  **/
  36
  37 static void enable_shadow(device_t dev)
  38 {
  39        writel(0x77777777,GX_BASE+BC_XMAP_2);
  40        writel(0x77777777,GX_BASE+BC_XMAP_3);
  41 }
  42
  43 static void northbridge_init(device_t dev)
  44 {
  45         printk_debug("northbridge: %s()\n", __FUNCTION__);
  46
  47         optimize_xbus(dev);
  48         enable_shadow(dev);
  49         printk_spew("Calling enable_cache()\n");
  50         enable_cache();
  51 }
  52
  53
  54 static struct device_operations northbridge_operations = {
  55         .read_resources   = pci_dev_read_resources,
  56         .set_resources    = pci_dev_set_resources,
  57         .enable_resources = pci_dev_enable_resources,
  58         .init             = northbridge_init,
  59         .enable           = 0,
  60         .ops_pci          = 0,
  61 };
  62
  63 static const struct pci_driver northbridge_driver __pci_driver = {
  64         .ops = &northbridge_operations,
  65         .vendor = PCI_VENDOR_ID_CYRIX,
  66         .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
  67 };
  68
  69
  70
  71 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  72
  73 static void pci_domain_read_resources(device_t dev)
  74 {
  75         struct resource *resource;
  76
  77         printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
  78
  79         /* Initialize the system wide io space constraints */
  80         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  81         resource->limit = 0xffffUL;
  82         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  83
  84         /* Initialize the system wide memory resources constraints */
  85         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  86         resource->limit = 0xffffffffULL;
  87         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  88 }
  89
  90 static void ram_resource(device_t dev, unsigned long index,
  91         unsigned long basek, unsigned long sizek)
  92 {
  93         struct resource *resource;
  94
  95         if (!sizek) {
  96                 return;
  97         }
  98         resource = new_resource(dev, index);
  99         resource->base  = ((resource_t)basek) << 10;
 100         resource->size  = ((resource_t)sizek) << 10;
 101         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 102                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 103 }
 104
 105 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 106 {
 107         struct resource **best_p = gp;
 108         struct resource *best;
 109         best = *best_p;
 110         if (!best || (best->base > new->base)) {
 111                 best = new;
 112         }
 113         *best_p = best;
 114 }
 115
 116 static uint32_t find_pci_tolm(struct bus *bus)
 117 {
 118         struct resource *min;
 119         uint32_t tolm;
 120         min = 0;
 121         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 122         tolm = 0xffffffffUL;
 123         if (min && tolm > min->base) {
 124                 tolm = min->base;
 125         }
 126         return tolm;
 127 }
 128
 129 static void pci_domain_set_resources(device_t dev)
 130 {
 131         device_t mc_dev;
 132         uint32_t pci_tolm;
 133
 134         pci_tolm = find_pci_tolm(&dev->link[0]);
 135         mc_dev = dev->link[0].children;
 136         if (mc_dev) {
 137                 unsigned int tomk, tolmk;
 138                 unsigned int ramreg = 0;
 139                 int i, idx;
 140                 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
 141                 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
 142
 143                 for(i=0; i<0x20; i+= 0x10) {
 144                         unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
 145                         unsigned int mem_config = *mcreg;
 146
 147                         if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
 148                                 continue;
 149                         ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
 150                 }
 151
 152                 tomk = ramreg << 10;
 153
 154                 /* Sort out the framebuffer size */
 155                 tomk -= CONFIG_VIDEO_MB * 1024;
 156                 *bcdramtop = ((tomk << 10) - 1);
 157                 *mcgbaseadd = (tomk >> 9);
 158
 159                 printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
 160                 printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 161
 162                 printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
 163
 164                 /* Compute the top of Low memory */
 165                 tolmk = pci_tolm >> 10;
 166                 if (tolmk >= tomk) {
 167                         /* The PCI hole does does not overlap the memory.
 168                          */
 169                         tolmk = tomk;
 170                 }
 171                 /* Report the memory regions */
 172                 idx = 10;
 173                 ram_resource(dev, idx++, 0, tolmk);
 174         }
 175         assign_resources(&dev->link[0]);
 176 }
 177
 178 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 179 {
 180         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 181         return max;
 182 }
 183
 184 static struct device_operations pci_domain_ops = {
 185         .read_resources   = pci_domain_read_resources,
 186         .set_resources    = pci_domain_set_resources,
 187         .enable_resources = enable_childrens_resources,
 188         .init             = 0,
 189         .scan_bus         = pci_domain_scan_bus,
 190 };
 191
 192 static void cpu_bus_init(device_t dev)
 193 {
 194         printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
 195         initialize_cpus(&dev->link[0]);
 196 }
 197
 198 static void cpu_bus_noop(device_t dev)
 199 {
 200 }
 201
 202 static struct device_operations cpu_bus_ops = {
 203         .read_resources   = cpu_bus_noop,
 204         .set_resources    = cpu_bus_noop,
 205         .enable_resources = cpu_bus_noop,
 206         .init             = cpu_bus_init,
 207         .scan_bus         = 0,
 208 };
 209
 210 static void enable_dev(struct device *dev)
 211 {
 212         printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
 213         /* Set the operations if it is a special bus type */
 214         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 215                 printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
 216                 dev->ops = &pci_domain_ops;
 217                 pci_set_method(dev);
 218         }
 219         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 220                 printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
 221                 dev->ops = &cpu_bus_ops;
 222         } else {
 223                 printk_spew("device path type %d\n",dev->path.type);
 224         }
 225 }
 226
 227 struct chip_operations northbridge_amd_gx1_ops = {
 228         CHIP_NAME("AMD GX1 Northbridge")
 229         .enable_dev = enable_dev,
 230 };