1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
11 #include "northbridge.h"
12 #include <cpu/amd/gx1def.h>
13 #include <cpu/x86/cache.h>
16 #define NORTHBRIDGE_FILE "northbridge.c"
20 static void optimize_xbus(device_t dev)
22 /* Optimise X-Bus performance */
23 pci_write_config8(dev, 0x40, 0x1e);
24 pci_write_config8(dev, 0x41, 0x52);
25 pci_write_config8(dev, 0x43, 0xc1);
26 pci_write_config8(dev, 0x44, 0x00);
30 * Enables memory from 0xC0000 up to 0xFFFFF.
31 * So this region is read/write and cache able
33 * FIXME: What about PCI master access into
37 static void enable_shadow(device_t dev)
39 writel(0x77777777,GX_BASE+BC_XMAP_2);
40 writel(0x77777777,GX_BASE+BC_XMAP_3);
43 static void northbridge_init(device_t dev)
45 printk_debug("northbridge: %s()\n", __func__);
49 printk_spew("Calling enable_cache()\n");
54 static struct device_operations northbridge_operations = {
55 .read_resources = pci_dev_read_resources,
56 .set_resources = pci_dev_set_resources,
57 .enable_resources = pci_dev_enable_resources,
58 .init = northbridge_init,
63 static const struct pci_driver northbridge_driver __pci_driver = {
64 .ops = &northbridge_operations,
65 .vendor = PCI_VENDOR_ID_CYRIX,
66 .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
71 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
73 static void pci_domain_read_resources(device_t dev)
75 struct resource *resource;
77 printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
79 /* Initialize the system wide io space constraints */
80 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
81 resource->limit = 0xffffUL;
82 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
84 /* Initialize the system wide memory resources constraints */
85 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
86 resource->limit = 0xffffffffULL;
87 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
90 static void ram_resource(device_t dev, unsigned long index,
91 unsigned long basek, unsigned long sizek)
93 struct resource *resource;
98 resource = new_resource(dev, index);
99 resource->base = ((resource_t)basek) << 10;
100 resource->size = ((resource_t)sizek) << 10;
101 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
102 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
105 static void tolm_test(void *gp, struct device *dev, struct resource *new)
107 struct resource **best_p = gp;
108 struct resource *best;
110 if (!best || (best->base > new->base)) {
116 static uint32_t find_pci_tolm(struct bus *bus)
118 struct resource *min;
121 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
123 if (min && tolm > min->base) {
129 #if HAVE_HIGH_TABLES==1
130 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
131 extern uint64_t high_tables_base, high_tables_size;
134 static void pci_domain_set_resources(device_t dev)
139 pci_tolm = find_pci_tolm(&dev->link[0]);
140 mc_dev = dev->link[0].children;
142 unsigned int tomk, tolmk;
143 unsigned int ramreg = 0;
145 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
146 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
148 for(i=0; i<0x20; i+= 0x10) {
149 unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
150 unsigned int mem_config = *mcreg;
152 if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
154 ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
159 /* Sort out the framebuffer size */
160 tomk -= CONFIG_VIDEO_MB * 1024;
161 *bcdramtop = ((tomk << 10) - 1);
162 *mcgbaseadd = (tomk >> 9);
164 printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
165 printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
167 printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
169 /* Compute the top of Low memory */
170 tolmk = pci_tolm >> 10;
172 /* The PCI hole does does not overlap the memory.
177 #if HAVE_HIGH_TABLES==1
178 /* Leave some space for ACPI, PIRQ and MP tables */
179 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
180 high_tables_size = HIGH_TABLES_SIZE * 1024;
183 /* Report the memory regions */
185 ram_resource(dev, idx++, 0, tolmk);
187 assign_resources(&dev->link[0]);
190 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
192 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
196 static struct device_operations pci_domain_ops = {
197 .read_resources = pci_domain_read_resources,
198 .set_resources = pci_domain_set_resources,
199 .enable_resources = enable_childrens_resources,
201 .scan_bus = pci_domain_scan_bus,
204 static void cpu_bus_init(device_t dev)
206 printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
207 initialize_cpus(&dev->link[0]);
210 static void cpu_bus_noop(device_t dev)
214 static struct device_operations cpu_bus_ops = {
215 .read_resources = cpu_bus_noop,
216 .set_resources = cpu_bus_noop,
217 .enable_resources = cpu_bus_noop,
218 .init = cpu_bus_init,
222 static void enable_dev(struct device *dev)
224 printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
225 /* Set the operations if it is a special bus type */
226 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
227 printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
228 dev->ops = &pci_domain_ops;
231 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
232 printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
233 dev->ops = &cpu_bus_ops;
235 printk_spew("device path type %d\n",dev->path.type);
239 struct chip_operations northbridge_amd_gx1_ops = {
240 CHIP_NAME("AMD GX1 Northbridge")
241 .enable_dev = enable_dev,