src/northbridge/amd/gx1/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "northbridge.h"
  12 #include <cpu/amd/gx1def.h>
  13 #include <cpu/x86/cache.h>
  14 #include <cpu/cpu.h>
  15
  16 #define NORTHBRIDGE_FILE "northbridge.c"
  17 /*
  18 */
  19
  20 static void optimize_xbus(device_t dev)
  21 {
  22         /* Optimise X-Bus performance */
  23         pci_write_config8(dev, 0x40, 0x1e);
  24         pci_write_config8(dev, 0x41, 0x52);
  25         pci_write_config8(dev, 0x43, 0xc1);
  26         pci_write_config8(dev, 0x44, 0x00);
  27 }
  28
  29 /**
  30  * Enables memory from 0xC0000 up to 0xFFFFF.
  31  * So this region is read/write and cache able
  32  *
  33  * FIXME: What about PCI master access into
  34  *        this region?
  35  **/
  36
  37 static void enable_shadow(device_t dev)
  38 {
  39        write32(GX_BASE+BC_XMAP_2, 0x77777777);
  40        write32(GX_BASE+BC_XMAP_3, 0x77777777);
  41 }
  42
  43 static void northbridge_init(device_t dev)
  44 {
  45         printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
  46
  47         optimize_xbus(dev);
  48         enable_shadow(dev);
  49         printk(BIOS_SPEW, "Calling enable_cache()\n");
  50         enable_cache();
  51 }
  52
  53
  54 static struct device_operations northbridge_operations = {
  55         .read_resources   = pci_dev_read_resources,
  56         .set_resources    = pci_dev_set_resources,
  57         .enable_resources = pci_dev_enable_resources,
  58         .init             = northbridge_init,
  59         .enable           = 0,
  60         .ops_pci          = 0,
  61 };
  62
  63 static const struct pci_driver northbridge_driver __pci_driver = {
  64         .ops = &northbridge_operations,
  65         .vendor = PCI_VENDOR_ID_CYRIX,
  66         .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
  67 };
  68
  69 #if CONFIG_WRITE_HIGH_TABLES==1
  70 #include <cbmem.h>
  71 #endif
  72
  73 static void pci_domain_set_resources(device_t dev)
  74 {
  75         device_t mc_dev;
  76         uint32_t pci_tolm;
  77
  78         pci_tolm = find_pci_tolm(dev->link_list);
  79         mc_dev = dev->link_list->children;
  80         if (mc_dev) {
  81                 unsigned int tomk, tolmk;
  82                 unsigned int ramreg = 0;
  83                 int i, idx;
  84                 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
  85                 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
  86
  87                 for(i=0; i<0x20; i+= 0x10) {
  88                         unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
  89                         unsigned int mem_config = *mcreg;
  90
  91                         if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
  92                                 continue;
  93                         ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
  94                 }
  95
  96                 tomk = ramreg << 10;
  97
  98                 /* Sort out the framebuffer size */
  99                 tomk -= CONFIG_VIDEO_MB * 1024;
 100                 *bcdramtop = ((tomk << 10) - 1);
 101                 *mcgbaseadd = (tomk >> 9);
 102
 103                 printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
 104                 printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 105
 106                 printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 107
 108                 /* Compute the top of Low memory */
 109                 tolmk = pci_tolm >> 10;
 110                 if (tolmk >= tomk) {
 111                         /* The PCI hole does does not overlap the memory.
 112                          */
 113                         tolmk = tomk;
 114                 }
 115
 116 #if CONFIG_WRITE_HIGH_TABLES==1
 117                 /* Leave some space for ACPI, PIRQ and MP tables */
 118                 high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
 119                 high_tables_size = HIGH_MEMORY_SIZE;
 120 #endif
 121
 122                 /* Report the memory regions */
 123                 idx = 10;
 124                 ram_resource(dev, idx++, 0, tolmk);
 125         }
 126         assign_resources(dev->link_list);
 127 }
 128
 129 static struct device_operations pci_domain_ops = {
 130         .read_resources   = pci_domain_read_resources,
 131         .set_resources    = pci_domain_set_resources,
 132         .enable_resources = NULL,
 133         .init             = NULL,
 134         .scan_bus         = pci_domain_scan_bus,
 135 };
 136
 137 static void cpu_bus_init(device_t dev)
 138 {
 139         printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 140         initialize_cpus(dev->link_list);
 141 }
 142
 143 static void cpu_bus_noop(device_t dev)
 144 {
 145 }
 146
 147 static struct device_operations cpu_bus_ops = {
 148         .read_resources   = cpu_bus_noop,
 149         .set_resources    = cpu_bus_noop,
 150         .enable_resources = cpu_bus_noop,
 151         .init             = cpu_bus_init,
 152         .scan_bus         = 0,
 153 };
 154
 155 static void enable_dev(struct device *dev)
 156 {
 157         printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 158         /* Set the operations if it is a special bus type */
 159         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 160                 printk(BIOS_SPEW, "DEVICE_PATH_PCI_DOMAIN\n");
 161                 dev->ops = &pci_domain_ops;
 162                 pci_set_method(dev);
 163         }
 164         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 165                 printk(BIOS_SPEW, "DEVICE_PATH_APIC_CLUSTER\n");
 166                 dev->ops = &cpu_bus_ops;
 167         } else {
 168                 printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
 169         }
 170 }
 171
 172 struct chip_operations northbridge_amd_gx1_ops = {
 173         CHIP_NAME("AMD GX1 Northbridge")
 174         .enable_dev = enable_dev,
 175 };