1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
11 #include "northbridge.h"
12 #include <cpu/amd/gx1def.h>
13 #include <cpu/x86/cache.h>
16 #define NORTHBRIDGE_FILE "northbridge.c"
20 static void optimize_xbus(device_t dev)
22 /* Optimise X-Bus performance */
23 pci_write_config8(dev, 0x40, 0x1e);
24 pci_write_config8(dev, 0x41, 0x52);
25 pci_write_config8(dev, 0x43, 0xc1);
26 pci_write_config8(dev, 0x44, 0x00);
30 * Enables memory from 0xC0000 up to 0xFFFFF.
31 * So this region is read/write and cache able
33 * FIXME: What about PCI master access into
37 static void enable_shadow(device_t dev)
39 write32(GX_BASE+BC_XMAP_2, 0x77777777);
40 write32(GX_BASE+BC_XMAP_3, 0x77777777);
43 static void northbridge_init(device_t dev)
45 printk_debug("northbridge: %s()\n", __func__);
49 printk_spew("Calling enable_cache()\n");
54 static struct device_operations northbridge_operations = {
55 .read_resources = pci_dev_read_resources,
56 .set_resources = pci_dev_set_resources,
57 .enable_resources = pci_dev_enable_resources,
58 .init = northbridge_init,
63 static const struct pci_driver northbridge_driver __pci_driver = {
64 .ops = &northbridge_operations,
65 .vendor = PCI_VENDOR_ID_CYRIX,
66 .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
69 static void ram_resource(device_t dev, unsigned long index,
70 unsigned long basek, unsigned long sizek)
72 struct resource *resource;
77 resource = new_resource(dev, index);
78 resource->base = ((resource_t)basek) << 10;
79 resource->size = ((resource_t)sizek) << 10;
80 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
81 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
84 static void tolm_test(void *gp, struct device *dev, struct resource *new)
86 struct resource **best_p = gp;
87 struct resource *best;
89 if (!best || (best->base > new->base)) {
95 static uint32_t find_pci_tolm(struct bus *bus)
100 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
102 if (min && tolm > min->base) {
108 #if CONFIG_WRITE_HIGH_TABLES==1
109 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
110 extern uint64_t high_tables_base, high_tables_size;
113 static void pci_domain_set_resources(device_t dev)
118 pci_tolm = find_pci_tolm(&dev->link[0]);
119 mc_dev = dev->link[0].children;
121 unsigned int tomk, tolmk;
122 unsigned int ramreg = 0;
124 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
125 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
127 for(i=0; i<0x20; i+= 0x10) {
128 unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
129 unsigned int mem_config = *mcreg;
131 if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
133 ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
138 /* Sort out the framebuffer size */
139 tomk -= CONFIG_VIDEO_MB * 1024;
140 *bcdramtop = ((tomk << 10) - 1);
141 *mcgbaseadd = (tomk >> 9);
143 printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
144 printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
146 printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
148 /* Compute the top of Low memory */
149 tolmk = pci_tolm >> 10;
151 /* The PCI hole does does not overlap the memory.
156 #if CONFIG_WRITE_HIGH_TABLES==1
157 /* Leave some space for ACPI, PIRQ and MP tables */
158 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
159 high_tables_size = HIGH_TABLES_SIZE * 1024;
162 /* Report the memory regions */
164 ram_resource(dev, idx++, 0, tolmk);
166 assign_resources(&dev->link[0]);
169 static struct device_operations pci_domain_ops = {
170 .read_resources = pci_domain_read_resources,
171 .set_resources = pci_domain_set_resources,
172 .enable_resources = enable_childrens_resources,
174 .scan_bus = pci_domain_scan_bus,
177 static void cpu_bus_init(device_t dev)
179 printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
180 initialize_cpus(&dev->link[0]);
183 static void cpu_bus_noop(device_t dev)
187 static struct device_operations cpu_bus_ops = {
188 .read_resources = cpu_bus_noop,
189 .set_resources = cpu_bus_noop,
190 .enable_resources = cpu_bus_noop,
191 .init = cpu_bus_init,
195 static void enable_dev(struct device *dev)
197 printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
198 /* Set the operations if it is a special bus type */
199 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
200 printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
201 dev->ops = &pci_domain_ops;
204 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
205 printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
206 dev->ops = &cpu_bus_ops;
208 printk_spew("device path type %d\n",dev->path.type);
212 struct chip_operations northbridge_amd_gx1_ops = {
213 CHIP_NAME("AMD GX1 Northbridge")
214 .enable_dev = enable_dev,