src/northbridge/amd/amdmct/wrappers/mcti_d.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* Call-backs */
  21 #include <delay.h>
  22
  23 static u16 mctGet_NVbits(u8 index)
  24 {
  25         u16 val = 0;
  26
  27         switch (index) {
  28         case NV_PACK_TYPE:
  29 #if CONFIG_CPU_SOCKET_TYPE == 0x10      /* Socket F */
  30                 val = 0;
  31 #elif CONFIG_CPU_SOCKET_TYPE == 0x11    /* AM3 */
  32                 val = 1;
  33 #elif CONFIG_CPU_SOCKET_TYPE == 0x13    /* ASB2 */
  34                 val = 4;
  35 //#elif SYSTEM_TYPE == MOBILE
  36 //              val = 2;
  37 #endif
  38                 break;
  39         case NV_MAX_NODES:
  40                 val = MAX_NODES_SUPPORTED;
  41                 break;
  42         case NV_MAX_DIMMS:
  43                 //val = MAX_DIMMS_SUPPORTED;
  44                 val = 8;
  45                 break;
  46         case NV_MAX_MEMCLK:
  47                 /* Maximum platform supported memclk */
  48                 //val =  200;   /* 200MHz(DDR400) */
  49                 //val =  266;   /* 266MHz(DDR533) */
  50                 //val =  333;   /* 333MHz(DDR667) */
  51                 val =  400;     /* 400MHz(DDR800) */
  52                 break;
  53         case NV_ECC_CAP:
  54 #if SYSTEM_TYPE == SERVER
  55                 val = 1;        /* memory bus ECC capable */
  56 #else
  57                 val = 0;        /* memory bus ECC not capable */
  58 #endif
  59                 break;
  60         case NV_4RANKType:
  61                 /* Quad Rank DIMM slot type */
  62                 val = 0;        /* normal */
  63                 //val = 1;      /* R4 (registered DIMMs in AMD server configuration) */
  64                 //val = 2;      /* S4 (Unbuffered SO-DIMMS) */
  65                 break;
  66         case NV_BYPMAX:
  67 #if   (UMA_SUPPORT == 0)
  68                 val = 4;
  69 #elif  (UMA_SUPPORT == 1)
  70                 val = 7;
  71 #endif
  72                 break;
  73         case NV_RDWRQBYP:
  74 #if  (UMA_SUPPORT == 0)
  75                 val = 2;
  76 #elif (UMA_SUPPORT == 1)
  77                 val = 3;
  78 #endif
  79                 break;
  80         case NV_MCTUSRTMGMODE:
  81                 val = 0;        /* Automatic (recommended) */
  82                 //val = 1;      /* Limited */
  83                 //val = 2;      /* Manual */
  84                 break;
  85         case NV_MemCkVal:
  86                 //val = 0;      /* 200MHz */
  87                 //val = 1;      /* 266MHz */
  88                 val = 2;        /* 333MHz */
  89                 break;
  90         case NV_BankIntlv:
  91                 /* Bank (chip select) interleaving */
  92                 //val = 0;      /* disabled */
  93                 val = 1;        /* enabled (recommended) */
  94                 break;
  95         case NV_MemHole:
  96                 //val = 0;      /* Disabled */
  97                 val = 1;        /* Enabled (recommended) */
  98                 break;
  99         case NV_AllMemClks:
 100                 val = 0;        /* Normal (only to slots that have enabled DIMMs) */
 101                 //val = 1;      /* Enable all memclocks */
 102                 break;
 103         case NV_SPDCHK_RESTRT:
 104                 val = 0;        /* Exit current node initialization if any DIMM has SPD checksum error */
 105                 //val = 1;      /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */
 106                 break;
 107         case NV_DQSTrainCTL:
 108                 //val = 0;      /*Skip dqs training */
 109                 val = 1;        /* Perform dqs training */
 110                 break;
 111         case NV_NodeIntlv:
 112                 val = 0;        /* Disabled (recommended) */
 113                 //val = 1;      /* Enable */
 114                 break;
 115         case NV_BurstLen32:
 116 #if (UMA_SUPPORT == 0)
 117                 val = 0;        /* 64 byte mode */
 118 #elif (UMA_SUPPORT == 1)
 119                 val = 1;        /* 32 byte mode */
 120 #endif
 121                 break;
 122         case NV_CKE_PDEN:
 123                 //val = 0;      /* Disable */
 124                 val = 1;        /* Enable */
 125                 break;
 126         case NV_CKE_CTL:
 127                 val = 0;        /* per channel control */
 128                 //val = 1;      /* per chip select control */
 129                 break;
 130         case NV_CLKHZAltVidC3:
 131                 val = 0;        /* disable */
 132                 //val = 1;      /* enable */
 133                 break;
 134         case NV_BottomIO:
 135                 val = 0xE0;     /* address bits [31:24] */
 136                 break;
 137         case NV_BottomUMA:
 138 #if (UMA_SUPPORT == 0)
 139                 val = 0xE0;     /* address bits [31:24] */
 140 #elif (UMA_SUPPORT == 1)
 141                 val = 0xB0;     /* address bits [31:24] */
 142 #endif
 143                 break;
 144         case NV_ECC:
 145 #if (SYSTEM_TYPE == SERVER)
 146                 val = 1;        /* Enable */
 147 #else
 148                 val = 0;        /* Disable */
 149 #endif
 150                 break;
 151         case NV_NBECC:
 152 #if (SYSTEM_TYPE == SERVER)
 153                 val = 1;        /* Enable */
 154 #else
 155                 val = 0;        /* Disable */
 156 #endif
 157                 break;
 158         case NV_ChipKill:
 159 #if (SYSTEM_TYPE == SERVER)
 160                 val = 1;        /* Enable */
 161 #else
 162                 val = 0;        /* Disable */
 163 #endif
 164                 break;
 165         case NV_ECCRedir:
 166                 val = 0;        /* Disable */
 167                 //val = 1;      /* Enable */
 168                 break;
 169         case NV_DramBKScrub:
 170                 val = 0x00;     /* Disabled */
 171                 //val = 0x01;   /* 40ns */
 172                 //val = 0x02;   /* 80ns */
 173                 //val = 0x03;   /* 160ns */
 174                 //val = 0x04;   /* 320ns */
 175                 //val = 0x05;   /* 640ns */
 176                 //val = 0x06;   /* 1.28us */
 177                 //val = 0x07;   /* 2.56us */
 178                 //val = 0x08;   /* 5.12us */
 179                 //val = 0x09;   /* 10.2us */
 180                 //val = 0x0a;   /* 20.5us */
 181                 //val = 0x0b;   /* 41us */
 182                 //val = 0x0c;   /* 81.9us */
 183                 //val = 0x0d;   /* 163.8us */
 184                 //val = 0x0e;   /* 327.7us */
 185                 //val = 0x0f;   /* 655.4us */
 186                 //val = 0x10;   /* 1.31ms */
 187                 //val = 0x11;   /* 2.62ms */
 188                 //val = 0x12;   /* 5.24ms */
 189                 //val = 0x13;   /* 10.49ms */
 190                 //val = 0x14;   /* 20.97sms */
 191                 //val = 0x15;   /* 42ms */
 192                 //val = 0x16;   /* 84ms */
 193                 break;
 194         case NV_L2BKScrub:
 195                 val = 0;        /* Disabled - See L2Scrub in BKDG */
 196                 break;
 197         case NV_DCBKScrub:
 198                 val = 0;        /* Disabled - See DcacheScrub in BKDG */
 199                 break;
 200         case NV_CS_SpareCTL:
 201                 val = 0;        /* Disabled */
 202                 //val = 1;      /* Enabled */
 203                 break;
 204         case NV_SyncOnUnEccEn:
 205                 val = 0;        /* Disabled */
 206                 //val = 1;      /* Enabled */
 207                 break;
 208         case NV_Unganged:
 209                 /* channel interleave is better performance than ganged mode at this time */
 210                 val = 1;                /* Enabled */
 211                 //val = 0;      /* Disabled */
 212                 break;
 213         case NV_ChannelIntlv:
 214                 val = 5;        /* Not currently checked in mctchi_d.c */
 215         /* Bit 0 =     0 - Disable
 216          *             1 - Enable
 217          * Bits[2:1] = 00b - Address bits 6
 218          *             01b - Address bits 1
 219          *             10b - Hash*, XOR of address bits [20:16, 6]
 220          *             11b - Hash*, XOR of address bits [20:16, 9]
 221          */
 222                 break;
 223         }
 224
 225         return val;
 226 }
 227
 228
 229 static void mctHookAfterDIMMpre(void)
 230 {
 231 }
 232
 233
 234 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 235 {
 236         pDCTstat->PresetmaxFreq = 400;
 237 }
 238
 239 #ifdef UNUSED_CODE
 240 static void mctAdjustAutoCycTmg(void)
 241 {
 242 }
 243 #endif
 244
 245
 246 static void mctAdjustAutoCycTmg_D(void)
 247 {
 248 }
 249
 250
 251 static void mctHookAfterAutoCycTmg(void)
 252 {
 253 }
 254
 255
 256 static void mctGetCS_ExcludeMap(void)
 257 {
 258 }
 259
 260
 261 static void mctHookAfterAutoCfg(void)
 262 {
 263 }
 264
 265
 266 static void mctHookAfterPSCfg(void)
 267 {
 268 }
 269
 270
 271 static void mctHookAfterHTMap(void)
 272 {
 273 }
 274
 275
 276 static void mctHookAfterCPU(void)
 277 {
 278 }
 279
 280
 281 static void mctSaveDQSSigTmg_D(void)
 282 {
 283 }
 284
 285
 286 static void mctGetDQSSigTmg_D(void)
 287 {
 288 }
 289
 290
 291 static void mctHookBeforeECC(void)
 292 {
 293 }
 294
 295
 296 static void mctHookAfterECC(void)
 297 {
 298 }
 299
 300 #ifdef UNUSED_CODE
 301 static void mctInitMemGPIOs_A(void)
 302 {
 303 }
 304 #endif
 305
 306
 307 static void mctInitMemGPIOs_A_D(void)
 308 {
 309 }
 310
 311
 312 static void mctNodeIDDebugPort_D(void)
 313 {
 314 }
 315
 316
 317 #ifdef UNUSED_CODE
 318 static void mctWarmReset(void)
 319 {
 320 }
 321 #endif
 322
 323
 324 static void mctWarmReset_D(void)
 325 {
 326 }
 327
 328
 329 static void mctHookBeforeDramInit(void)
 330 {
 331 }
 332
 333
 334 static void mctHookAfterDramInit(void)
 335 {
 336 }
 337
 338 static void coreDelay (void);
 339
 340
 341 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
 342 /* Erratum 350 */
 343 static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
 344 {
 345         u8 u8Channel;
 346         u8 u8Receiver;
 347         u32 u32Addr;
 348         u8 u8Valid;
 349         u32 u32DctDev;
 350
 351         // 1. dummy read for each installed DIMM */
 352         for (u8Channel = 0; u8Channel < 2; u8Channel++) {
 353                 // This will be 0 for vaild DIMMS, eles 8
 354                 u8Receiver = mct_InitReceiver_D(pDCTstat, u8Channel);
 355
 356                 for (; u8Receiver < 8; u8Receiver += 2) {
 357                         u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid);
 358
 359                         if(!u8Valid) {  /* Address not supported on current CS */
 360                                 print_t("vErrata350: Address not supported on current CS\n");
 361                                 continue;
 362                         }
 363                         print_t("vErrata350: dummy read \n");
 364                         read32_fs(u32Addr);
 365                 }
 366         }
 367
 368         print_t("vErrata350: step 2a\n");
 369
 370         /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */
 371         u32DctDev = pDCTstat->dev_dct;
 372         Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000);
 373         /*                                                ^--- value
 374                                                 ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG.
 375                                          ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
 376
 377         if(!pDCTstat->GangedMode) {
 378                 print_t("vErrata350: step 2b\n");
 379                 Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000);
 380                 /*                                                ^--- value
 381                                                         ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG
 382                                                 ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
 383         }
 384
 385         print_t("vErrata350: step 3\n");
 386         /* 3. Wait at least 300 nanoseconds. */
 387         coreDelay();
 388
 389         print_t("vErrata350: step 4\n");
 390         /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */
 391         Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000);
 392
 393         if(!pDCTstat->GangedMode) {
 394                 print_t("vErrata350: step 4b\n");
 395                 Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000);
 396         }
 397
 398         print_t("vErrata350: step 5\n");
 399         /* 5. Wait at least 2 microseconds. */
 400         coreDelay();
 401
 402 }
 403 #endif
 404
 405
 406 static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
 407 {
 408 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
 409         if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) {
 410                 vErrata350(pMCTstat, pDCTstatA);
 411         }
 412 #endif
 413 }
 414
 415 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
 416 static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val)
 417 {
 418         if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) {
 419                 if (pDCTstatA->Status & (1 << SB_Registered)) {
 420                         val ++;
 421                 }
 422         }
 423         return val;
 424 }
 425 #endif
 426
 427 static void mctHookAfterAnyTraining(void)
 428 {
 429 }
 430
 431 static u32 mctGetLogicalCPUID_D(u8 node)
 432 {
 433         return mctGetLogicalCPUID(node);
 434 }
 435
 436 #if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
 437 static u8 mctSetNodeBoundary_D(void)
 438 {
 439         return 0;
 440 }
 441 #endif