2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 static u16 mctGet_NVbits(u8 index)
28 #if CONFIG_CPU_SOCKET_TYPE == 0x10 /* Socket F */
30 #elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM3 */
32 #elif CONFIG_CPU_SOCKET_TYPE == 0x13 /* ASB2 */
34 //#elif SYSTEM_TYPE == MOBILE
39 val = MAX_NODES_SUPPORTED;
42 //val = MAX_DIMMS_SUPPORTED;
46 /* Maximum platform supported memclk */
47 //val = 200; /* 200MHz(DDR400) */
48 //val = 266; /* 266MHz(DDR533) */
49 //val = 333; /* 333MHz(DDR667) */
50 val = 400; /* 400MHz(DDR800) */
53 #if SYSTEM_TYPE == SERVER
54 val = 1; /* memory bus ECC capable */
56 val = 0; /* memory bus ECC not capable */
60 /* Quad Rank DIMM slot type */
62 //val = 1; /* R4 (registered DIMMs in AMD server configuration) */
63 //val = 2; /* S4 (Unbuffered SO-DIMMS) */
66 #if (UMA_SUPPORT == 0)
68 #elif (UMA_SUPPORT == 1)
73 #if (UMA_SUPPORT == 0)
75 #elif (UMA_SUPPORT == 1)
79 case NV_MCTUSRTMGMODE:
80 val = 0; /* Automatic (recommended) */
81 //val = 1; /* Limited */
82 //val = 2; /* Manual */
85 //val = 0; /* 200MHz */
86 //val = 1; /* 266MHz */
90 /* Bank (chip select) interleaving */
91 //val = 0; /* disabled */
92 val = 1; /* enabled (recommended) */
95 //val = 0; /* Disabled */
96 val = 1; /* Enabled (recommended) */
99 val = 0; /* Normal (only to slots that have enabled DIMMs) */
100 //val = 1; /* Enable all memclocks */
102 case NV_SPDCHK_RESTRT:
103 val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */
104 //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */
107 //val = 0; /*Skip dqs training */
108 val = 1; /* Perform dqs training */
111 val = 0; /* Disabled (recommended) */
112 //val = 1; /* Enable */
115 #if (UMA_SUPPORT == 0)
116 val = 0; /* 64 byte mode */
117 #elif (UMA_SUPPORT == 1)
118 val = 1; /* 32 byte mode */
122 //val = 0; /* Disable */
123 val = 1; /* Enable */
126 val = 0; /* per channel control */
127 //val = 1; /* per chip select control */
129 case NV_CLKHZAltVidC3:
130 val = 0; /* disable */
131 //val = 1; /* enable */
134 val = 0xE0; /* address bits [31:24] */
137 #if (UMA_SUPPORT == 0)
138 val = 0xE0; /* address bits [31:24] */
139 #elif (UMA_SUPPORT == 1)
140 val = 0xB0; /* address bits [31:24] */
144 #if (SYSTEM_TYPE == SERVER)
145 val = 1; /* Enable */
147 val = 0; /* Disable */
151 #if (SYSTEM_TYPE == SERVER)
152 val = 1; /* Enable */
154 val = 0; /* Disable */
158 #if (SYSTEM_TYPE == SERVER)
159 val = 1; /* Enable */
161 val = 0; /* Disable */
165 val = 0; /* Disable */
166 //val = 1; /* Enable */
169 val = 0x00; /* Disabled */
170 //val = 0x01; /* 40ns */
171 //val = 0x02; /* 80ns */
172 //val = 0x03; /* 160ns */
173 //val = 0x04; /* 320ns */
174 //val = 0x05; /* 640ns */
175 //val = 0x06; /* 1.28us */
176 //val = 0x07; /* 2.56us */
177 //val = 0x08; /* 5.12us */
178 //val = 0x09; /* 10.2us */
179 //val = 0x0a; /* 20.5us */
180 //val = 0x0b; /* 41us */
181 //val = 0x0c; /* 81.9us */
182 //val = 0x0d; /* 163.8us */
183 //val = 0x0e; /* 327.7us */
184 //val = 0x0f; /* 655.4us */
185 //val = 0x10; /* 1.31ms */
186 //val = 0x11; /* 2.62ms */
187 //val = 0x12; /* 5.24ms */
188 //val = 0x13; /* 10.49ms */
189 //val = 0x14; /* 20.97sms */
190 //val = 0x15; /* 42ms */
191 //val = 0x16; /* 84ms */
194 val = 0; /* Disabled - See L2Scrub in BKDG */
197 val = 0; /* Disabled - See DcacheScrub in BKDG */
200 val = 0; /* Disabled */
201 //val = 1; /* Enabled */
203 case NV_SyncOnUnEccEn:
204 val = 0; /* Disabled */
205 //val = 1; /* Enabled */
208 /* channel interleave is better performance than ganged mode at this time */
209 val = 1; /* Enabled */
210 //val = 0; /* Disabled */
212 case NV_ChannelIntlv:
213 val = 5; /* Not currently checked in mctchi_d.c */
214 /* Bit 0 = 0 - Disable
216 * Bits[2:1] = 00b - Address bits 6
217 * 01b - Address bits 1
218 * 10b - Hash*, XOR of address bits [20:16, 6]
219 * 11b - Hash*, XOR of address bits [20:16, 9]
228 static void mctHookAfterDIMMpre(void)
233 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
235 pDCTstat->PresetmaxFreq = 400;
239 static void mctAdjustAutoCycTmg(void)
245 static void mctAdjustAutoCycTmg_D(void)
250 static void mctHookAfterAutoCycTmg(void)
255 static void mctGetCS_ExcludeMap(void)
260 static void mctHookAfterAutoCfg(void)
265 static void mctHookAfterPSCfg(void)
270 static void mctHookAfterHTMap(void)
275 static void mctHookAfterCPU(void)
280 static void mctSaveDQSSigTmg_D(void)
285 static void mctGetDQSSigTmg_D(void)
290 static void mctHookBeforeECC(void)
295 static void mctHookAfterECC(void)
300 static void mctInitMemGPIOs_A(void)
306 static void mctInitMemGPIOs_A_D(void)
311 static void mctNodeIDDebugPort_D(void)
317 static void mctWarmReset(void)
323 static void mctWarmReset_D(void)
328 static void mctHookBeforeDramInit(void)
333 static void mctHookAfterDramInit(void)
337 static void coreDelay (void);
341 static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
349 // 1. dummy read for each installed DIMM */
350 for (u8Channel = 0; u8Channel < 2; u8Channel++) {
351 // This will be 0 for vaild DIMMS, eles 8
352 u8Receiver = mct_InitReceiver_D(pDCTstat, u8Channel);
354 for (; u8Receiver < 8; u8Receiver += 2) {
355 u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid);
357 if(!u8Valid) { /* Address not supported on current CS */
358 print_t("vErrata350: Address not supported on current CS\n");
361 print_t("vErrata350: dummy read \n");
366 print_t("vErrata350: step 2a\n");
368 /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */
369 u32DctDev = pDCTstat->dev_dct;
370 Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000);
372 ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG.
373 ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
375 if(!pDCTstat->GangedMode) {
376 print_t("vErrata350: step 2b\n");
377 Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000);
379 ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG
380 ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
383 print_t("vErrata350: step 3\n");
384 /* 3. Wait at least 300 nanoseconds. */
387 print_t("vErrata350: step 4\n");
388 /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */
389 Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000);
391 if(!pDCTstat->GangedMode) {
392 print_t("vErrata350: step 4b\n");
393 Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000);
396 print_t("vErrata350: step 5\n");
397 /* 5. Wait at least 2 microseconds. */
403 static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
405 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
406 if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) {
407 vErrata350(pMCTstat, pDCTstatA);
412 static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val)
414 if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) {
415 if (pDCTstatA->Status & (1 << SB_Registered)) {
422 static void mctHookAfterAnyTraining(void)
426 static u32 mctGetLogicalCPUID_D(u8 node)
428 return mctGetLogicalCPUID(node);
431 static u8 mctSetNodeBoundary_D(void)