2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 u16 mctGet_NVbits(u8 index)
28 #if SYSTEM_TYPE == SERVER
30 #elif SYSTEM_TYPE == DESKTOP
32 //#elif SYSTEM_TYPE == MOBILE
37 val = MAX_NODES_SUPPORTED;
40 //val = MAX_DIMMS_SUPPORTED;
44 /* Maximum platform supported memclk */
45 //val = 200; /* 200MHz(DDR400) */
46 //val = 266; /* 266MHz(DDR533) */
47 //val = 333; /* 333MHz(DDR667) */
48 val = 400; /* 400MHz(DDR800) */
51 #if SYSTEM_TYPE == SERVER
52 val = 1; /* memory bus ECC capable */
54 val = 0; /* memory bus ECC not capable */
58 /* Quad Rank DIMM slot type */
60 //val = 1; /* R4 (registered DIMMs in AMD server configuration) */
61 //val = 2; /* S4 (Unbuffered SO-DIMMS) */
64 #if (UMA_SUPPORT == 0)
66 #elif (UMA_SUPPORT == 1)
71 #if (UMA_SUPPORT == 0)
73 #elif (UMA_SUPPORT == 1)
77 case NV_MCTUSRTMGMODE:
78 val = 0; /* Automatic (recommended) */
79 //val = 1; /* Limited */
80 //val = 2; /* Manual */
83 //val = 0; /* 200MHz */
84 //val = 1; /* 266MHz */
88 /* Bank (chip select) interleaving */
89 //val = 0; /* disabled */
90 val = 1; /* enabled (recommended) */
93 //val = 0; /* Disabled */
94 val = 1; /* Enabled (recommended) */
97 val = 0; /* Normal (only to slots that have enabled DIMMs) */
98 //val = 1; /* Enable all memclocks */
100 case NV_SPDCHK_RESTRT:
101 val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */
102 //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */
105 //val = 0; /*Skip dqs training */
106 val = 1; /* Perform dqs training */
109 val = 0; /* Disabled (recommended) */
110 //val = 1; /* Enable */
113 #if (UMA_SUPPORT == 0)
114 val = 0; /* 64 byte mode */
115 #elif (UMA_SUPPORT == 1)
116 val = 1; /* 32 byte mode */
120 //val = 0; /* Disable */
121 val = 1; /* Enable */
124 val = 0; /* per channel control */
125 //val = 1; /* per chip select control */
127 case NV_CLKHZAltVidC3:
128 val = 0; /* disable */
129 //val = 1; /* enable */
132 val = 0xC0; /* address bits [31:24] */
135 #if (UMA_SUPPORT == 0)
136 val = 0xC0; /* address bits [31:24] */
137 #elif (UMA_SUPPORT == 1)
138 val = 0xB0; /* address bits [31:24] */
142 #if (SYSTEM_TYPE == SERVER)
143 val = 1; /* Enable */
145 val = 0; /* Disable */
149 #if (SYSTEM_TYPE == SERVER)
150 val = 1; /* Enable */
152 val = 0; /* Disable */
156 #if (SYSTEM_TYPE == SERVER)
157 val = 1; /* Enable */
159 val = 0; /* Disable */
163 val = 0; /* Disable */
164 //val = 1; /* Enable */
167 val = 0x00; /* Disabled */
168 //val = 0x01; /* 40ns */
169 //val = 0x02; /* 80ns */
170 //val = 0x03; /* 160ns */
171 //val = 0x04; /* 320ns */
172 //val = 0x05; /* 640ns */
173 //val = 0x06; /* 1.28us */
174 //val = 0x07; /* 2.56us */
175 //val = 0x08; /* 5.12us */
176 //val = 0x09; /* 10.2us */
177 //val = 0x0a; /* 20.5us */
178 //val = 0x0b; /* 41us */
179 //val = 0x0c; /* 81.9us */
180 //val = 0x0d; /* 163.8us */
181 //val = 0x0e; /* 327.7us */
182 //val = 0x0f; /* 655.4us */
183 //val = 0x10; /* 1.31ms */
184 //val = 0x11; /* 2.62ms */
185 //val = 0x12; /* 5.24ms */
186 //val = 0x13; /* 10.49ms */
187 //val = 0x14; /* 20.97sms */
188 //val = 0x15; /* 42ms */
189 //val = 0x16; /* 84ms */
192 val = 0; /* Disabled - See L2Scrub in BKDG */
195 val = 0; /* Disabled - See DcacheScrub in BKDG */
198 val = 0; /* Disabled */
199 //val = 1; /* Enabled */
200 case NV_SyncOnUnEccEn:
201 val = 0; /* Disabled */
202 //val = 1; /* Enabled */
204 /* channel interleave is better performance than ganged mode at this time */
205 val = 1; /* Enabled */
206 //val = 0; /* Disabled */
207 case NV_ChannelIntlv:
208 val = 5; /* Disabled */ /* Not currently checked in mctchi_d.c */
209 /* Bit 0 = 0 - Disable
211 * Bits[2:1] = 00b - Address bits 6
212 * 01b - Address bits 1
213 * 10b - Hash*, XOR of address bits [20:16, 6]
214 * 11b - Hash*, XOR of address bits [20:16, 9]
223 void mctHookAfterDIMMpre(void)
228 void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
230 pDCTstat->PresetmaxFreq = 400;
234 void mctAdjustAutoCycTmg(void)
238 void mctAdjustAutoCycTmg_D(void)
243 void mctHookAfterAutoCycTmg(void)
248 void mctGetCS_ExcludeMap(void)
253 void mctHookAfterAutoCfg(void)
258 void mctHookAfterPSCfg(void)
263 void mctHookAfterHTMap(void)
268 void mctHookAfterCPU(void)
273 void mctSaveDQSSigTmg_D(void)
278 void mctGetDQSSigTmg_D(void)
283 void mctHookBeforeECC(void)
288 void mctHookAfterECC(void)
293 void mctInitMemGPIOs_A(void)
298 void mctInitMemGPIOs_A_D(void)
303 void mctNodeIDDebugPort_D(void)
308 void mctWarmReset(void)
312 void mctWarmReset_D(void)
317 void mctHookBeforeDramInit(void)
322 void mctHookAfterDramInit(void)
327 void mctHookBeforeAnyTraining(void)
331 void mctHookAfterAnyTraining(void)
335 u32 mctGetLogicalCPUID_D(u8 node)
337 return mctGetLogicalCPUID(node);