2 #include <cpu/x86/lapic.h>
4 #define HT_INIT_CONTROL 0x6c
6 #define HTIC_ColdR_Detect (1<<4)
7 #define HTIC_BIOSR_Detect (1<<5)
8 #define HTIC_INIT_Detect (1<<6)
10 static int cpu_init_detected(unsigned nodeid)
15 dev = PCI_DEV(0, 0x18 + nodeid, 0);
16 htic = pci_read_config32(dev, HT_INIT_CONTROL);
18 return !!(htic & HTIC_INIT_Detect);
21 static int bios_reset_detected(void)
24 htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
26 return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
29 static int cold_reset_detected(void)
32 htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
34 return !(htic & HTIC_ColdR_Detect);
37 static void distinguish_cpu_resets(unsigned nodeid)
41 device = PCI_DEV(0, 0x18 + nodeid, 0);
42 htic = pci_read_config32(device, HT_INIT_CONTROL);
43 htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
44 pci_write_config32(device, HT_INIT_CONTROL, htic);
47 static void set_bios_reset(void)
50 htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
51 htic &= ~HTIC_BIOSR_Detect;
52 pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
55 static unsigned node_link_to_bus(unsigned node, unsigned link)
59 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
61 config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
62 if ((config_map & 3) != 3) {
65 if ((((config_map >> 4) & 7) == node) &&
66 (((config_map >> 8) & 3) == link))
68 return (config_map >> 16) & 0xff;
74 static unsigned get_sblk(void)
77 /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
78 reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
79 return ((reg>>8) & 3) ;
82 static unsigned get_sbbusn(unsigned sblk)
84 return node_link_to_bus(0, sblk);