src/northbridge/amd/amdk8/reset_test.c

   1 #include <stdint.h>
   2 #include <arch/smp/lapic.h>
   3 #define NODE_ID         0x60
   4 #define HT_INIT_CONTROL 0x6c
   5
   6 #define HTIC_ColdR_Detect  (1<<4)
   7 #define HTIC_BIOSR_Detect  (1<<5)
   8 #define HTIC_INIT_Detect   (1<<6)
   9
  10 static int cpu_init_detected(void)
  11 {
  12         unsigned long htic;
  13         device_t dev;
  14
  15         dev = PCI_DEV(0, 0x18 + lapicid(), 0);
  16         htic = pci_read_config32(dev, HT_INIT_CONTROL);
  17
  18         return !!(htic & HTIC_INIT_Detect);
  19 }
  20
  21 static int bios_reset_detected(void)
  22 {
  23         unsigned long htic;
  24         htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
  25
  26         return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
  27 }
  28
  29 static int cold_reset_detected(void)
  30 {
  31         unsigned long htic;
  32         htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
  33
  34         return !(htic & HTIC_ColdR_Detect);
  35 }
  36
  37 static void distinguish_cpu_resets(void)
  38 {
  39         uint32_t htic;
  40         device_t device;
  41         device = PCI_DEV(0, 0x18 + lapicid(), 0);
  42         htic = pci_read_config32(device, HT_INIT_CONTROL);
  43         htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
  44         pci_write_config32(device, HT_INIT_CONTROL, htic);
  45 }
  46
  47 static void set_bios_reset(void)
  48 {
  49         unsigned long htic;
  50         htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
  51         htic &= ~HTIC_BIOSR_Detect;
  52         pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
  53 }