2 * This file is part of the coreboot project.
4 * Copyright (C) 2002 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 YingHai Lu
7 * Copyright (C) 2008 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <cpu/x86/mem.h>
24 #include <cpu/x86/cache.h>
25 #include <cpu/x86/mtrr.h>
26 #include <cpu/x86/tsc.h>
33 #ifndef QRANK_DIMM_SUPPORT
34 #define QRANK_DIMM_SUPPORT 0
37 #if CONFIG_USE_PRINTK_IN_CAR
39 #error This file needs CONFIG_USE_PRINTK_IN_CAR
42 #define RAM_TIMING_DEBUG 0
44 #if RAM_TIMING_DEBUG == 1
45 #define printk_raminit printk_debug
47 #define printk_raminit(fmt, arg...)
51 #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
52 # error "CONFIG_LB_MEM_TOPK must be a power of 2"
55 #include "amdk8_f_pci.c"
58 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
59 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
62 [29: 0] DctOffset (Dram Controller Offset)
63 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
66 [31:31] DctAccessDone (Dram Controller Access Done)
67 0 = Access in progress
68 1 = No access is progress
71 [31: 0] DctOffsetData (Dram Controller Offset Data)
74 - Write the register num to DctOffset with
76 - poll the DctAccessDone until it = 1
77 - Read the data from DctOffsetData
79 - Write the data to DctOffsetData
80 - Write register num to DctOffset with DctAccessWrite = 1
81 - poll the DctAccessDone untio it = 1
85 static void setup_resource_map(const unsigned int *register_values, int max)
88 for (i = 0; i < max; i += 3) {
92 dev = register_values[i] & ~0xff;
93 where = register_values[i] & 0xff;
94 reg = pci_read_config32(dev, where);
95 reg &= register_values[i+1];
96 reg |= register_values[i+2];
97 pci_write_config32(dev, where, reg);
101 static int controller_present(const struct mem_controller *ctrl)
103 return pci_read_config32(ctrl->f0, 0) == 0x11001022;
106 static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
108 static const unsigned int register_values[] = {
110 /* Careful set limit registers before base registers which
111 contain the enables */
112 /* DRAM Limit i Registers
121 * [ 2: 0] Destination Node ID
131 * [10: 8] Interleave select
132 * specifies the values of A[14:12] to use with interleave enable.
134 * [31:16] DRAM Limit Address i Bits 39-24
135 * This field defines the upper address bits of a 40 bit address
136 * that define the end of the DRAM region.
138 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
139 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
140 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
141 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
142 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
143 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
144 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
145 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
146 /* DRAM Base i Registers
155 * [ 0: 0] Read Enable
158 * [ 1: 1] Write Enable
159 * 0 = Writes Disabled
162 * [10: 8] Interleave Enable
163 * 000 = No interleave
164 * 001 = Interleave on A[12] (2 nodes)
166 * 011 = Interleave on A[12] and A[14] (4 nodes)
170 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
172 * [13:16] DRAM Base Address i Bits 39-24
173 * This field defines the upper address bits of a 40-bit address
174 * that define the start of the DRAM region.
176 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
177 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
178 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
179 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
180 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
181 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
182 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
183 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
185 /* DRAM CS Base Address i Registers
194 * [ 0: 0] Chip-Select Bank Enable
198 * [ 2: 2] Memory Test Failed
200 * [13: 5] Base Address (21-13)
201 * An optimization used when all DIMM are the same size...
203 * [28:19] Base Address (36-27)
204 * This field defines the top 11 addresses bit of a 40-bit
205 * address that define the memory address space. These
206 * bits decode 32-MByte blocks of memory.
209 PCI_ADDR(0, 0x18, 2, 0x40), 0xe007c018, 0x00000000,
210 PCI_ADDR(0, 0x18, 2, 0x44), 0xe007c018, 0x00000000,
211 PCI_ADDR(0, 0x18, 2, 0x48), 0xe007c018, 0x00000000,
212 PCI_ADDR(0, 0x18, 2, 0x4C), 0xe007c018, 0x00000000,
213 PCI_ADDR(0, 0x18, 2, 0x50), 0xe007c018, 0x00000000,
214 PCI_ADDR(0, 0x18, 2, 0x54), 0xe007c018, 0x00000000,
215 PCI_ADDR(0, 0x18, 2, 0x58), 0xe007c018, 0x00000000,
216 PCI_ADDR(0, 0x18, 2, 0x5C), 0xe007c018, 0x00000000,
217 /* DRAM CS Mask Address i Registers
222 * Select bits to exclude from comparison with the DRAM Base address register.
224 * [13: 5] Address Mask (21-13)
225 * Address to be excluded from the optimized case
227 * [28:19] Address Mask (36-27)
228 * The bits with an address mask of 1 are excluded from address comparison
232 PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000,
233 PCI_ADDR(0, 0x18, 2, 0x64), 0xe007c01f, 0x00000000,
234 PCI_ADDR(0, 0x18, 2, 0x68), 0xe007c01f, 0x00000000,
235 PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000,
237 /* DRAM Control Register
239 * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
240 * 0x03-0x00: reserved
241 * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
244 * 010 = 1.5 Memory Clocks
245 * 011 = 2 Memory Clocks
246 * 100 = 2.5 Memory Clocks
247 * 101 = 3 Memory Clocks
248 * 110 = 3.5 Memory Clocks
251 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable)
252 * Enables the DDR memory clocks to be tristated when alternate VID
253 * mode is enabled. This bit has no effect if the DisNbClkRamp bit
255 * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time)
258 * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode)
259 * 0 = Normal DQS Receiver enable operation
260 * 1 = DQS receiver enable training mode
263 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0),
265 /* DRAM Initialization Register
267 * [15: 0] MrsAddress (Address for MRS/EMRS Commands)
268 * this field specifies the dsata driven on the DRAM address pins
269 * 15-0 for MRS and EMRS commands
270 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
271 * this files specifies the data driven on the DRAM bank pins for
272 * the MRS and EMRS commands
274 * [24:24] SendPchgAll (Send Precharge All Command)
275 * Setting this bit causes the DRAM controller to send a precharge
276 * all command. This bit is cleared by the hardware after the
278 * [25:25] SendAutoRefresh (Send Auto Refresh Command)
279 * Setting this bit causes the DRAM controller to send an auto
280 * refresh command. This bit is cleared by the hardware after the
282 * [26:26] SendMrsCmd (Send MRS/EMRS Command)
283 * Setting this bit causes the DRAM controller to send the MRS or
284 * EMRS command defined by the MrsAddress and MrsBank fields. This
285 * bit is cleared by the hardware adter the commmand completes
286 * [27:27] DeassertMemRstX (De-assert Memory Reset)
287 * Setting this bit causes the DRAM controller to de-assert the
288 * memory reset pin. This bit cannot be used to assert the memory
290 * [28:28] AssertCke (Assert CKE)
291 * setting this bit causes the DRAM controller to assert the CKE
292 * pins. This bit cannot be used to de-assert the CKE pins
294 * [31:31] EnDramInit (Enable DRAM Initialization)
295 * Setting this bit puts the DRAM controller in a BIOS controlled
296 * DRAM initialization mode. BIOS must clear this bit aster DRAM
297 * initialization is complete.
299 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
302 /* DRAM Bank Address Mapping Register
304 * Specify the memory module size
324 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000,
325 /* DRAM Timing Low Register
327 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
337 * [ 5: 4] Trcd (Ras#-active to Cas# read/write delay)
343 * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh)
349 * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time)
350 * 0 = 2 clocks for Burst Length of 32 Bytes
351 * 4 clocks for Burst Length of 64 Bytes
352 * 1 = 3 clocks for Burst Length of 32 Bytes
353 * 5 clocks for Burst Length of 64 Bytes
354 * [15:12] Tras (Minimum Ras# Active Time)
357 * 0010 = 5 bus clocks
359 * 1111 = 18 bus clocks
360 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto
361 * refresh of the same bank)
362 * 0000 = 11 bus clocks
363 * 0010 = 12 bus clocks
365 * 1110 = 25 bus clocks
366 * 1111 = 26 bus clocks
367 * [21:20] Twr (Write Recovery Time, From the last data to precharge,
368 * writes can go back-to-back)
373 * [23:22] Trrd (Active-to-active(Ras#-to-Ras#) Delay of different banks)
378 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
379 * BIOS should set it to reduce the power consumption)
380 * Bit F(1207) M2 Package S1g1 Package
382 * 1 N/A MA0_CLK1 MA0_CLK1
385 * 4 MA1_CLK MA1_CLK0 N/A
386 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
388 * 7 N/A MA0_CLK2 MA0_CLK2
390 PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ ,
391 /* DRAM Timing High Register
394 * [ 6: 4] TrwtTO (Read-to-Write Turnaround for Data, DQS Contention)
404 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
405 * minium write-to-read delay when both access the same chip select)
410 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum
411 * write-to-read delay when accessing two different DIMMs)
416 * [13:12] Twrwr (Write to Write Timing)
417 * 00 = 1 bus clocks ( 0 idle cycle on the bus)
418 * 01 = 2 bus clocks ( 1 idle cycle on the bus)
419 * 10 = 3 bus clocks ( 2 idle cycles on the bus)
421 * [15:14] Trdrd ( Read to Read Timing)
422 * 00 = 2 bus clocks ( 1 idle cycle on the bus)
423 * 01 = 3 bus clocks ( 2 idle cycles on the bus)
424 * 10 = 4 bus clocks ( 3 idle cycles on the bus)
425 * 11 = 5 bus clocks ( 4 idel cycles on the bus)
426 * [17:16] Tref (Refresh Rate)
427 * 00 = Undefined behavior
429 * 10 = Refresh interval of 7.8 microseconds
430 * 11 = Refresh interval of 3.9 microseconds
432 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
433 * based on DRAM density and speed)
434 * 000 = 75 ns (all speeds, 256Mbit)
435 * 001 = 105 ns (all speeds, 512Mbit)
436 * 010 = 127.5 ns (all speeds, 1Gbit)
437 * 011 = 195 ns (all speeds, 2Gbit)
438 * 100 = 327.5 ns (all speeds, 4Gbit)
442 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
443 * based on DRAM density and speed)
444 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
445 * based on DRAM density and speed)
446 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
447 * based on DRAM density and speed)
449 PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
450 /* DRAM Config Low Register
452 * [ 0: 0] InitDram (Initialize DRAM)
453 * 1 = write 1 cause DRAM controller to execute the DRAM
454 * initialization, when done it read to 0
455 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
456 * 1 = write 1 causes the DRAM controller to bring the DRAMs out
457 * for self refresh mode
459 * [ 5: 4] DramTerm (DRAM Termination)
460 * 00 = On die termination disabled
465 * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
466 * 0 = Normal drive strength mode.
467 * 1 = Weak drive strength mode
468 * [ 8: 8] ParEn (Parity Enable)
469 * 1 = Enable address parity computation output, PAR,
470 * and enables the parity error input, ERR
471 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
472 * 1 = Enable high temperature ( two times normal )
474 * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
477 * [11:11] Width128 ( Width of DRAM interface)
478 * 0 = the controller DRAM interface is 64-bits wide
479 * 1 = the controller DRAM interface is 128-bits wide
480 * [12:12] X4Dimm (DIMM 0 is x4)
481 * [13:13] X4Dimm (DIMM 1 is x4)
482 * [14:14] X4Dimm (DIMM 2 is x4)
483 * [15:15] X4Dimm (DIMM 3 is x4)
485 * 1 = x4 DIMM present
486 * [16:16] UnBuffDimm ( Unbuffered DIMMs)
488 * 1 = Unbuffered DIMMs
490 * [19:19] DimmEccEn ( DIMM ECC Enable )
491 * 1 = ECC checking is being enabled for all DIMMs on the DRAM
492 * controller ( Through F3 0x44[EccEn])
495 PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
496 /* DRAM Config High Register
498 * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
504 * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid)
505 * 1 = BIOS need to set the bit when setting up MemClkFreq to
507 * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
512 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
513 * registered DIMMs are present in the system
514 * 0 = DM pins function as data mask pins
515 * 1 = DM pins function as read DQS pins
517 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
518 * is set, the DRAM controller is disabled, and interface in low power
520 * 0 = Enabled (default)
522 * [15:15] PowerDownEn ( Power Down Mode Enable )
523 * 0 = Disabled (default)
525 * [16:16] PowerDown ( Power Down Mode )
526 * 0 = Channel CKE Control
527 * 1 = Chip Select CKE Control
528 * [17:17] FourRankSODimm (Four Rank SO-DIMM)
529 * 1 = this bit is set by BIOS to indicate that a four rank
531 * [18:18] FourRankRDimm (Four Rank Registered DIMM)
532 * 1 = this bit is set by BIOS to indicate that a four rank
533 * registered DIMM is present
535 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
536 * 0 = DRAM address and control signals are driven for one
538 * 1 = One additional MEMCLK of setup time is provided on all
539 * DRAM address and control signals except CS, CKE, and ODT;
540 * i.e., these signals are drivern for two MEMCLK cycles
543 * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
544 * 0 = Disabled (default)
547 * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
548 * 0000 = No bypass; the oldest request is never bypassed
549 * 0001 = The oldest request may be bypassed no more than 1 time
551 * 1111 = The oldest request may be bypassed no more than 15\
553 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than
554 * 4 banks in a 8 bank device are activated
555 * 0000 = No tFAW window restriction
556 * 0001 = 8 MEMCLK cycles
557 * 0010 = 9 MEMCLK cycles
559 * 1101 = 20 MEMCLK cycles
562 PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000,
563 /* DRAM Delay Line Register
565 * [ 0: 0] MemClrStatus (Memory Clear Status) : Readonly
566 * when set, this bit indicates that the memory clear function
567 * is complete. Only clear by reset. BIOS should not write or
568 * read the DRAM until this bit is set by hardware
569 * [ 1: 1] DisableJitter ( Disable Jitter)
570 * When set the DDR compensation circuit will not change the
571 * values unless the change is more than one step from the
573 * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
578 * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable)
579 * 1 When bit enables support for mismatched DIMMs when using
580 * 128-bit DRAM interface, the Width128 no effect, only for
582 * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable)
583 * When set to 1, indicates that each entry in the page tables
584 * dynamically adjusts the idle cycle limit based on page
585 * Conflict/Page Miss (PC/PM) traffic
586 * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
595 * [ 9: 9] DramEnabled ( DRAM Enabled)
596 * When Set, this bit indicates that the DRAM is enabled, this
597 * bit is set by hardware after DRAM initialization or on an exit
598 * from self refresh. The DRAM controller is intialized after the
599 * hardware-controlled initialization process ( initiated by the
600 * F2 0x90[DramInit]) completes or when the BIOS-controlled
601 * initialization process completes (F2 0x7c(EnDramInit] is
602 * written from 1 to 0)
604 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
605 * BIOS should set it to reduce the power consumption)
606 * Bit F(1207) M2 Package S1g1 Package
608 * 1 N/A MA0_CLK1 MA0_CLK1
611 * 4 MA1_CLK MA1_CLK0 N/A
612 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
614 * 7 N/A MA0_CLK2 MA0_CLK2
616 PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000,
618 /* DRAM Scrub Control Register
620 * [ 4: 0] DRAM Scrube Rate
622 * [12: 8] L2 Scrub Rate
624 * [20:16] Dcache Scrub
627 * 00000 = Do not scrub
649 * All Others = Reserved
651 PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
652 /* DRAM Scrub Address Low Register
654 * [ 0: 0] DRAM Scrubber Redirect Enable
656 * 1 = Scrubber Corrects errors found in normal operation
658 * [31: 6] DRAM Scrub Address 31-6
660 PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
661 /* DRAM Scrub Address High Register
663 * [ 7: 0] DRAM Scrubb Address 39-32
666 PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
668 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
669 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
672 [29: 0] DctOffset (Dram Controller Offset)
673 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
676 [31:31] DctAccessDone (Dram Controller Access Done)
677 0 = Access in progress
678 1 = No access is progress
681 [31: 0] DctOffsetData (Dram Controller Offset Data)
684 - Write the register num to DctOffset with DctAccessWrite = 0
685 - poll the DctAccessDone until it = 1
686 - Read the data from DctOffsetData
688 - Write the data to DctOffsetData
689 - Write register num to DctOffset with DctAccessWrite = 1
690 - poll the DctAccessDone untio it = 1
696 if (!controller_present(ctrl)) {
697 sysinfo->ctrl_present[ctrl->node_id] = 0;
700 sysinfo->ctrl_present[ctrl->node_id] = 1;
702 printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id);
703 max = ARRAY_SIZE(register_values);
704 for (i = 0; i < max; i += 3) {
708 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
709 where = register_values[i] & 0xff;
710 reg = pci_read_config32(dev, where);
711 reg &= register_values[i+1];
712 reg |= register_values[i+2];
713 pci_write_config32(dev, where, reg);
716 printk_spew("done.\n");
720 static int is_dual_channel(const struct mem_controller *ctrl)
723 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
724 return dcl & DCL_Width128;
728 static int is_opteron(const struct mem_controller *ctrl)
730 /* Test to see if I am an Opteron.
731 * FIXME Testing dual channel capability is correct for now
732 * but a better test is probably required.
733 * m2 and s1g1 support dual channel too. but only support unbuffered dimm
735 #warning "FIXME implement a better test for opterons"
737 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
738 return !!(nbcap & NBCAP_128Bit);
742 static int is_registered(const struct mem_controller *ctrl)
744 /* Test to see if we are dealing with registered SDRAM.
745 * If we are not registered we are unbuffered.
746 * This function must be called after spd_handle_unbuffered_dimms.
749 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
750 return !(dcl & DCL_UnBuffDimm);
754 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
756 /* Calculate the log base 2 size of a DIMM in bits */
763 value = spd_read_byte(device, SPD_ROW_NUM); /* rows */
764 if (value < 0) goto hw_err;
765 if ((value & 0xff) == 0) goto val_err; /* max is 16 ? */
766 sz->per_rank += value & 0xff;
767 sz->rows = value & 0xff;
769 value = spd_read_byte(device, SPD_COL_NUM); /* columns */
770 if (value < 0) goto hw_err;
771 if ((value & 0xff) == 0) goto val_err; /* max is 11 */
772 sz->per_rank += value & 0xff;
773 sz->col = value & 0xff;
775 value = spd_read_byte(device, SPD_BANK_NUM); /* banks */
776 if (value < 0) goto hw_err;
777 if ((value & 0xff) == 0) goto val_err;
778 sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3
779 sz->per_rank += sz->bank;
781 /* Get the module data width and convert it to a power of two */
782 value = spd_read_byte(device, SPD_DATA_WIDTH);
783 if (value < 0) goto hw_err;
785 if ((value != 72) && (value != 64)) goto val_err;
786 sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
788 /* How many ranks? */
789 /* number of physical banks */
790 value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);
791 if (value < 0) goto hw_err;
792 /* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */
793 value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
794 value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
796 rank == 1 only one rank or say one side
797 rank == 2 two side , and two ranks
798 rank == 4 two side , and four ranks total
799 Some one side two ranks, because of stacked
801 if ((value != 1) && (value != 2) && (value != 4 )) {
806 /* verify if per_rank is equal byte 31
807 it has the DIMM size as a multiple of 128MB.
809 value = spd_read_byte(device, SPD_RANK_SIZE);
810 if (value < 0) goto hw_err;
813 if (value <=4 ) value += 8; // add back to 1G to high
814 value += (27-5); // make 128MB to the real lines
815 if ( value != (sz->per_rank)) {
816 printk_err("Bad RANK Size --\n");
823 die("Bad SPD value\n");
824 /* If an hw_error occurs report that I have no memory */
836 static void set_dimm_size(const struct mem_controller *ctrl,
837 struct dimm_size *sz, unsigned index, struct mem_info *meminfo)
839 uint32_t base0, base1;
841 /* For each base register.
842 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
843 * The initialize dimm size is in bits.
844 * Set the base enable bit0.
849 /* Make certain side1 of the dimm is at least 128MB */
850 if (sz->per_rank >= 27) {
851 base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
854 /* Make certain side2 of the dimm is at least 128MB */
855 if (sz->rank > 1) { // 2 ranks or 4 ranks
856 base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
859 /* Double the size if we are using dual channel memory */
860 if (meminfo->is_Width128) {
861 base0 = (base0 << 1) | (base0 & 1);
862 base1 = (base1 << 1) | (base1 & 1);
865 /* Clear the reserved bits */
866 base0 &= ~0xe007fffe;
867 base1 &= ~0xe007fffe;
869 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
870 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
871 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
873 /* Set the appropriate DIMM base address register */
874 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
875 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
876 #if QRANK_DIMM_SUPPORT == 1
878 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
879 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
884 /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/
888 #if CPU_SOCKET_TYPE == 0x10 /* L1 */
889 ClkDis0 = DTL_MemClkDis0;
890 #elif CPU_SOCKET_TYPE == 0x11 /* AM2 */
891 ClkDis0 = DTL_MemClkDis0_AM2;
892 #elif CPU_SOCKET_TYPE == 0x12 /* S1G1 */
893 ClkDis0 = DTL_MemClkDis0_S1g1;
896 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
897 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
898 dword &= ~(ClkDis0 >> index);
899 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
902 dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
903 dword &= ~(ClkDis0 >> index);
904 #if QRANK_DIMM_SUPPORT == 1
906 dword &= ~(ClkDis0 >> (index+2));
909 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
911 if (meminfo->is_Width128) { // ChannelA+B
912 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
913 dword &= ~(ClkDis0 >> index);
914 #if QRANK_DIMM_SUPPORT == 1
916 dword &= ~(ClkDis0 >> (index+2));
919 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
926 /* row col bank for 64 bit
942 static void set_dimm_cs_map(const struct mem_controller *ctrl,
943 struct dimm_size *sz, unsigned index,
944 struct mem_info *meminfo)
946 static const uint8_t cs_map_aaa[24] = {
947 /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */
962 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
965 map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
966 map &= ~(0xf << (index * 4));
967 #if QRANK_DIMM_SUPPORT == 1
969 map &= ~(0xf << ( (index + 2) * 4));
973 /* Make certain side1 of the dimm is at least 128MB */
974 if (sz->per_rank >= 27) {
976 temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
977 map |= temp_map << (index*4);
978 #if QRANK_DIMM_SUPPORT == 1
980 map |= temp_map << ( (index + 2) * 4);
985 pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
990 static long spd_set_ram_size(const struct mem_controller *ctrl,
991 struct mem_info *meminfo)
995 for (i = 0; i < DIMM_SOCKETS; i++) {
996 struct dimm_size *sz = &(meminfo->sz[i]);
997 u32 spd_device = ctrl->channel0[i];
999 if (!(meminfo->dimm_mask & (1 << i))) {
1000 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1001 spd_device = ctrl->channel1[i];
1007 spd_get_dimm_size(spd_device, sz);
1008 if (sz->per_rank == 0) {
1009 return -1; /* Report SPD error */
1011 set_dimm_size(ctrl, sz, i, meminfo);
1012 set_dimm_cs_map (ctrl, sz, i, meminfo);
1014 return meminfo->dimm_mask;
1018 static void route_dram_accesses(const struct mem_controller *ctrl,
1019 unsigned long base_k, unsigned long limit_k)
1021 /* Route the addresses to the controller node */
1026 unsigned limit_reg, base_reg;
1029 node_id = ctrl->node_id;
1030 index = (node_id << 3);
1031 limit = (limit_k << 2);
1032 limit &= 0xffff0000;
1033 limit -= 0x00010000;
1034 limit |= ( 0 << 8) | (node_id << 0);
1035 base = (base_k << 2);
1037 base |= (0 << 8) | (1<<1) | (1<<0);
1039 limit_reg = 0x44 + index;
1040 base_reg = 0x40 + index;
1041 for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1);
1042 device += PCI_DEV(0, 1, 0)) {
1043 pci_write_config32(device, limit_reg, limit);
1044 pci_write_config32(device, base_reg, base);
1049 static void set_top_mem(unsigned tom_k, unsigned hole_startk)
1051 /* Error if I don't have memory */
1056 /* Report the amount of memory. */
1057 printk_debug("RAM: 0x%08x kB\n", tom_k);
1060 if (tom_k > (4*1024*1024)) {
1061 /* Now set top of memory */
1062 msr.lo = (tom_k & 0x003fffff) << 10;
1063 msr.hi = (tom_k & 0xffc00000) >> 22;
1064 wrmsr(TOP_MEM2, msr);
1067 /* Leave a 64M hole between TOP_MEM and TOP_MEM2
1068 * so I can see my rom chip and other I/O devices.
1070 if (tom_k >= 0x003f0000) {
1071 #if HW_MEM_HOLE_SIZEK != 0
1072 if (hole_startk != 0) {
1073 tom_k = hole_startk;
1078 msr.lo = (tom_k & 0x003fffff) << 10;
1079 msr.hi = (tom_k & 0xffc00000) >> 22;
1080 wrmsr(TOP_MEM, msr);
1083 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_Width128)
1087 static const uint8_t csbase_low_f0_shift[] = {
1088 /* 128MB */ (14 - (13-5)),
1089 /* 256MB */ (15 - (13-5)),
1090 /* 512MB */ (15 - (13-5)),
1091 /* 512MB */ (16 - (13-5)),
1092 /* 512MB */ (16 - (13-5)),
1093 /* 1GB */ (16 - (13-5)),
1094 /* 1GB */ (16 - (13-5)),
1095 /* 2GB */ (16 - (13-5)),
1096 /* 2GB */ (17 - (13-5)),
1097 /* 4GB */ (17 - (13-5)),
1098 /* 4GB */ (16 - (13-5)),
1099 /* 8GB */ (17 - (13-5)),
1102 /* cs_base_high is not changed */
1104 uint32_t csbase_inc;
1105 int chip_selects, index;
1107 unsigned common_size;
1108 unsigned common_cs_mode;
1109 uint32_t csbase, csmask;
1111 /* See if all of the memory chip selects are the same size
1112 * and if so count them.
1116 common_cs_mode = 0xff;
1117 for (index = 0; index < 8; index++) {
1122 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1124 /* Is it enabled? */
1129 size = (value >> 19) & 0x3ff;
1130 if (common_size == 0) {
1133 /* The size differed fail */
1134 if (common_size != size) {
1138 value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
1139 cs_mode =( value >> ((index>>1)*4)) & 0xf;
1140 if (common_cs_mode == 0xff) {
1141 common_cs_mode = cs_mode;
1143 /* The cs_mode differed fail */
1144 if (common_cs_mode != cs_mode) {
1149 /* Chip selects can only be interleaved when there is
1150 * more than one and their is a power of two of them.
1152 bits = log2(chip_selects);
1153 if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
1154 //chip_selects max = 8
1158 /* Find the bits of csbase that we need to interleave on */
1159 csbase_inc = 1 << (csbase_low_f0_shift[common_cs_mode]);
1165 /* Compute the initial values for csbase and csbask.
1166 * In csbase just set the enable bit and the base to zero.
1167 * In csmask set the mask bits for the size and page level interleave.
1170 csmask = (((common_size << bits) - 1) << 19);
1171 csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc);
1172 for (index = 0; index < 8; index++) {
1175 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1176 /* Is it enabled? */
1180 pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
1181 if ((index & 1) == 0) { //only have 4 CSMASK
1182 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((index>>1) << 2), csmask);
1184 csbase += csbase_inc;
1187 printk_debug("Interleaved\n");
1189 /* Return the memory size in K */
1190 return common_size << ((27-10) + bits);
1192 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
1196 /* Remember which registers we have used in the high 8 bits of tom */
1199 /* Find the largest remaining canidate */
1200 unsigned index, canidate;
1201 uint32_t csbase, csmask;
1205 for (index = 0; index < 8; index++) {
1207 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1209 /* Is it enabled? */
1214 /* Is it greater? */
1215 if (value <= csbase) {
1219 /* Has it already been selected */
1220 if (tom & (1 << (index + 24))) {
1223 /* I have a new canidate */
1228 /* See if I have found a new canidate */
1233 /* Remember the dimm size */
1234 size = csbase >> 19;
1236 /* Remember I have used this register */
1237 tom |= (1 << (canidate + 24));
1239 /* Recompute the cs base register value */
1240 csbase = (tom << 19) | 1;
1242 /* Increment the top of memory */
1245 /* Compute the memory mask */
1246 csmask = ((size -1) << 19);
1247 csmask |= 0x3fe0; /* For now don't optimize */
1249 /* Write the new base register */
1250 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
1251 /* Write the new mask register */
1252 if ((canidate & 1) == 0) { //only have 4 CSMASK
1253 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate >> 1) << 2), csmask);
1257 /* Return the memory size in K */
1258 return (tom & ~0xff000000) << (27-10);
1261 unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
1265 /* Find the last memory address used */
1267 for (node_id = 0; node_id < max_node_id; node_id++) {
1268 uint32_t limit, base;
1270 index = node_id << 3;
1271 base = pci_read_config32(ctrl->f1, 0x40 + index);
1272 /* Only look at the limit if the base is enabled */
1273 if ((base & 3) == 3) {
1274 limit = pci_read_config32(ctrl->f1, 0x44 + index);
1275 end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
1282 static void order_dimms(const struct mem_controller *ctrl,
1283 struct mem_info *meminfo)
1285 unsigned long tom_k, base_k;
1287 if (read_option(CMOS_VSTART_interleave_chip_selects,
1288 CMOS_VLEN_interleave_chip_selects, 1) != 0) {
1289 tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
1291 printk_debug("Interleaving disabled\n");
1296 tom_k = order_chip_selects(ctrl);
1299 /* Compute the memory base address */
1300 base_k = memory_end_k(ctrl, ctrl->node_id);
1302 route_dram_accesses(ctrl, base_k, tom_k);
1303 set_top_mem(tom_k, 0);
1307 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
1308 struct mem_info *meminfo)
1310 printk_debug("disabling dimm %02x\n", index);
1311 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
1312 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1313 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1315 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
1316 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
1317 #if QRANK_DIMM_SUPPORT == 1
1318 if (meminfo->sz[index].rank == 4) {
1319 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1320 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1325 meminfo->dimm_mask &= ~(1 << index);
1326 return meminfo->dimm_mask;
1330 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
1331 struct mem_info *meminfo)
1334 uint32_t registered;
1337 for (i = 0; (i < DIMM_SOCKETS); i++) {
1339 u32 spd_device = ctrl->channel0[i];
1340 if (!(meminfo->dimm_mask & (1 << i))) {
1341 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1342 spd_device = ctrl->channel1[i];
1347 value = spd_read_byte(spd_device, SPD_DIMM_TYPE);
1352 /* Registered dimm ? */
1354 if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
1355 //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
1356 registered |= (1<<i);
1360 if (is_opteron(ctrl)) {
1362 if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
1363 meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
1364 // die("Mixed buffered and registered dimms not supported");
1366 //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
1368 die("Unbuffered Dimms not supported on Opteron");
1374 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1375 dcl &= ~DCL_UnBuffDimm;
1376 meminfo->is_registered = 1;
1378 dcl |= DCL_UnBuffDimm;
1379 meminfo->is_registered = 0;
1381 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1384 if (meminfo->is_registered) {
1385 printk_debug("Registered\n");
1387 printk_debug("Unbuffered\n");
1390 return meminfo->dimm_mask;
1394 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1399 for (i = 0; i < DIMM_SOCKETS; i++) {
1402 device = ctrl->channel0[i];
1403 printk_raminit("DIMM socket %i, channel 0 SPD device is 0x%02x\n", i, device);
1405 byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */
1406 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1407 dimm_mask |= (1 << i);
1410 device = ctrl->channel1[i];
1411 printk_raminit("DIMM socket %i, channel 1 SPD device is 0x%02x\n", i, device);
1413 byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE);
1414 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1415 dimm_mask |= (1 << (i + DIMM_SOCKETS));
1422 static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_info *meminfo)
1426 /* SPD addresses to verify are identical */
1427 static const uint8_t addresses[] = {
1428 2, /* Type should be DDR2 SDRAM */
1429 3, /* *Row addresses */
1430 4, /* *Column addresses */
1431 5, /* *Number of DIMM Ranks */
1432 6, /* *Module Data Width*/
1433 11, /* *DIMM Conf Type */
1434 13, /* *Pri SDRAM Width */
1435 17, /* *Logical Banks */
1436 20, /* *DIMM Type Info */
1437 21, /* *SDRAM Module Attributes */
1438 27, /* *tRP Row precharge time */
1439 28, /* *Minimum Row Active to Row Active Delay (tRRD) */
1440 29, /* *tRCD RAS to CAS */
1441 30, /* *tRAS Activate to Precharge */
1442 36, /* *Write recovery time (tWR) */
1443 37, /* *Internal write to read command delay (tRDP) */
1444 38, /* *Internal read to precharge command delay (tRTP) */
1445 40, /* *Extension of Byte 41 tRC and Byte 42 tRFC */
1446 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */
1447 42, /* *Minimum Auto Refresh Command Time(Trfc) */
1448 /* The SPD addresses 18, 9, 23, 26 need special treatment like
1449 * in spd_set_memclk. Right now they cause many false negatives.
1450 * Keep them at the end to see other mismatches (if any).
1452 18, /* *Supported CAS Latencies */
1453 9, /* *Cycle time at highest CAS Latency CL=X */
1454 23, /* *Cycle time at CAS Latency (CLX - 1) */
1455 26, /* *Cycle time at CAS Latency (CLX - 2) */
1460 /* S1G1 and AM2 sockets are Mod64BitMux capable. */
1461 #if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12
1467 /* If the dimms are not in pairs do not do dual channels */
1468 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1469 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1470 goto single_channel;
1472 /* If the cpu is not capable of doing dual channels don't do dual channels */
1473 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1474 if (!(nbcap & NBCAP_128Bit)) {
1475 goto single_channel;
1477 for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1478 unsigned device0, device1;
1481 /* If I don't have a dimm skip this one */
1482 if (!(meminfo->dimm_mask & (1 << i))) {
1485 device0 = ctrl->channel0[i];
1486 device1 = ctrl->channel1[i];
1487 /* Abort if the chips don't support a common CAS latency. */
1488 common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
1490 printk_debug("No common CAS latency supported\n");
1491 goto single_channel;
1493 printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
1495 for (j = 0; j < ARRAY_SIZE(addresses); j++) {
1497 addr = addresses[j];
1498 value0 = spd_read_byte(device0, addr);
1502 value1 = spd_read_byte(device1, addr);
1506 if (value0 != value1) {
1507 printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr);
1508 goto single_channel;
1512 printk_spew("Enabling dual channel memory\n");
1513 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1514 dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
1515 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */
1516 dcl |= DCL_Width128;
1517 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1518 meminfo->is_Width128 = 1;
1519 return meminfo->dimm_mask;
1522 meminfo->is_Width128 = 0;
1523 meminfo->is_64MuxMode = 0;
1526 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1527 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1528 if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1529 /* mux capable and single dimm in channelB */
1531 printk_spew("Enable 64MuxMode & BurstLength32\n");
1532 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
1533 dcm |= DCM_Mode64BitMux;
1534 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
1535 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1536 //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
1537 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1538 meminfo->is_64MuxMode = 1;
1540 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1543 } else { /* unmatched dual dimms ? */
1544 /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
1545 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1546 printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
1548 return meminfo->dimm_mask;
1552 uint16_t cycle_time;
1553 uint8_t divisor; /* In 1/40 ns increments */
1558 uint8_t DcqByPassMax;
1559 uint32_t dch_memclk;
1563 static const struct mem_param speed[] = {
1566 .cycle_time = 0x500,
1567 .divisor = 200, // how many 1/40ns per clock
1568 .dch_memclk = DCH_MemClkFreq_200MHz, //0
1578 .cycle_time = 0x375,
1579 .divisor = 150, //????
1580 .dch_memclk = DCH_MemClkFreq_266MHz, //1
1589 .cycle_time = 0x300,
1591 .dch_memclk = DCH_MemClkFreq_333MHz, //2
1601 .cycle_time = 0x250,
1603 .dch_memclk = DCH_MemClkFreq_400MHz,//3
1611 .cycle_time = 0x000,
1615 static const struct mem_param *get_mem_param(unsigned min_cycle_time)
1618 const struct mem_param *param;
1619 for (param = &speed[0]; param->cycle_time ; param++) {
1620 if (min_cycle_time > (param+1)->cycle_time) {
1624 if (!param->cycle_time) {
1625 die("min_cycle_time to low");
1627 printk_debug("%s\n", param->name);
1631 static uint8_t get_exact_divisor(int i, uint8_t divisor)
1633 //input divisor could be 200(200), 150(266), 120(333), 100 (400)
1634 static const uint8_t dv_a[] = {
1635 /* 200 266 333 400 */
1636 /*4 */ 250, 250, 250, 250,
1637 /*5 */ 200, 200, 200, 100,
1638 /*6 */ 200, 166, 166, 100,
1639 /*7 */ 200, 171, 142, 100,
1641 /*8 */ 200, 150, 125, 100,
1642 /*9 */ 200, 156, 133, 100,
1643 /*10*/ 200, 160, 120, 100,
1644 /*11*/ 200, 163, 127, 100,
1646 /*12*/ 200, 150, 133, 100,
1647 /*13*/ 200, 153, 123, 100,
1648 /*14*/ 200, 157, 128, 100,
1649 /*15*/ 200, 160, 120, 100,
1656 /* Check for FID control support */
1657 struct cpuid_result cpuid1;
1658 cpuid1 = cpuid(0x80000007);
1659 if( cpuid1.edx & 0x02 ) {
1660 /* Use current FID */
1662 msr = rdmsr(0xc0010042);
1663 fid_cur = msr.lo & 0x3f;
1667 /* Use startup FID */
1669 msr = rdmsr(0xc0010015);
1670 fid_start = (msr.lo & (0x3f << 24));
1672 index = fid_start>>25;
1675 if (index>12) return divisor;
1677 if (i>3) return divisor;
1679 return dv_a[index * 4+i];
1684 struct spd_set_memclk_result {
1685 const struct mem_param *param;
1690 static unsigned convert_to_linear(unsigned value)
1692 static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 };
1695 /* We need to convert value to more readable */
1696 if ((value & 0xf) < 10) { //no .25, .33, .66, .75
1699 valuex = ((value & 0xf0) << 4) | fraction [(value & 0xf)-10];
1705 static const uint8_t latency_indicies[] = { 25, 23, 9 };
1707 int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
1709 int new_cycle_time, new_latency;
1714 /* First find the supported CAS latencies
1715 * Byte 18 for DDR SDRAM is interpreted:
1716 * bit 3 == CAS Latency = 3
1717 * bit 4 == CAS Latency = 4
1718 * bit 5 == CAS Latency = 5
1719 * bit 6 == CAS Latency = 6
1721 new_cycle_time = 0x500;
1724 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1728 printk_raminit("\tlatencies: %08x\n", latencies);
1729 /* Compute the lowest cas latency which can be expressed in this
1730 * particular SPD EEPROM. You can store at most settings for 3
1731 * contiguous CAS latencies, so by taking the highest CAS
1732 * latency maked as supported in the SPD and subtracting 2 you
1733 * get the lowest expressable CAS latency. That latency is not
1734 * necessarily supported, but a (maybe invalid) entry exists
1737 latency = log2(latencies) - 2;
1739 /* Loop through and find a fast clock with a low latency */
1740 for (index = 0; index < 3; index++, latency++) {
1742 if ((latency < 3) || (latency > 6) ||
1743 (!(latencies & (1 << latency)))) {
1746 value = spd_read_byte(spd_device, latency_indicies[index]);
1751 printk_raminit("\tindex: %08x\n", index);
1752 printk_raminit("\t\tlatency: %08x\n", latency);
1753 printk_raminit("\t\tvalue1: %08x\n", value);
1755 value = convert_to_linear(value);
1757 printk_raminit("\t\tvalue2: %08x\n", value);
1759 /* Only increase the latency if we decrease the clock */
1760 if (value >= *min_cycle_time ) {
1761 if (value < new_cycle_time) {
1762 new_cycle_time = value;
1763 new_latency = latency;
1764 } else if (value == new_cycle_time) {
1765 if (new_latency > latency) {
1766 new_latency = latency;
1770 printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time);
1771 printk_raminit("\t\tnew_latency: %08x\n", new_latency);
1775 if (new_latency > 6){
1779 /* Does min_latency need to be increased? */
1780 if (new_cycle_time > *min_cycle_time) {
1781 *min_cycle_time = new_cycle_time;
1784 /* Does min_cycle_time need to be increased? */
1785 if (new_latency > *min_latency) {
1786 *min_latency = new_latency;
1789 printk_raminit("2 min_cycle_time: %08x\n", *min_cycle_time);
1790 printk_raminit("2 min_latency: %08x\n", *min_latency);
1795 static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo)
1797 /* Compute the minimum cycle time for these dimms */
1798 struct spd_set_memclk_result result;
1799 unsigned min_cycle_time, min_latency, bios_cycle_time;
1803 static const uint16_t min_cycle_times[] = { // use full speed to compare
1804 [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */
1805 [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */
1806 [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */
1807 [NBCAP_MEMCLK_200MHZ] = 0x500, /* 5.0s */
1811 value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1812 min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
1813 bios_cycle_time = min_cycle_times[
1814 read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
1815 if (bios_cycle_time > min_cycle_time) {
1816 min_cycle_time = bios_cycle_time;
1820 printk_raminit("1 min_cycle_time: %08x\n", min_cycle_time);
1822 /* Compute the least latency with the fastest clock supported
1823 * by both the memory controller and the dimms.
1825 for (i = 0; i < DIMM_SOCKETS; i++) {
1828 printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask);
1829 printk_raminit("i: %08x\n",i);
1831 if (meminfo->dimm_mask & (1 << i)) {
1832 spd_device = ctrl->channel0[i];
1833 printk_raminit("Channel 0 settings:\n");
1835 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1843 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) {
1844 spd_device = ctrl->channel1[i];
1845 printk_raminit("Channel 1 settings:\n");
1847 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1857 /* Make a second pass through the dimms and disable
1858 * any that cannot support the selected memclk and cas latency.
1861 printk_raminit("3 min_cycle_time: %08x\n", min_cycle_time);
1862 printk_raminit("3 min_latency: %08x\n", min_latency);
1864 for (i = 0; (i < DIMM_SOCKETS); i++) {
1869 u32 spd_device = ctrl->channel0[i];
1871 if (!(meminfo->dimm_mask & (1 << i))) {
1872 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1873 spd_device = ctrl->channel1[i];
1879 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1880 if (latencies < 0) goto hw_error;
1881 if (latencies == 0) {
1885 /* Compute the lowest cas latency supported */
1886 latency = log2(latencies) -2;
1888 /* Walk through searching for the selected latency */
1889 for (index = 0; index < 3; index++, latency++) {
1890 if (!(latencies & (1 << latency))) {
1893 if (latency == min_latency)
1896 /* If I can't find the latency or my index is bad error */
1897 if ((latency != min_latency) || (index >= 3)) {
1901 /* Read the min_cycle_time for this latency */
1902 value = spd_read_byte(spd_device, latency_indicies[index]);
1903 if (value < 0) goto hw_error;
1905 value = convert_to_linear(value);
1906 /* All is good if the selected clock speed
1907 * is what I need or slower.
1909 if (value <= min_cycle_time) {
1912 /* Otherwise I have an error, disable the dimm */
1914 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
1917 printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time);
1919 /* Now that I know the minimum cycle time lookup the memory parameters */
1920 result.param = get_mem_param(min_cycle_time);
1922 /* Update DRAM Config High with our selected memory speed */
1923 value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1924 value &= ~(DCH_MemClkFreq_MASK << DCH_MemClkFreq_SHIFT);
1926 value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
1927 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
1929 printk_debug("%s\n", result.param->name);
1931 /* Update DRAM Timing Low with our selected cas latency */
1932 value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1933 value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
1934 value |= (min_latency - DTL_TCL_BASE) << DTL_TCL_SHIFT;
1935 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
1937 result.dimm_mask = meminfo->dimm_mask;
1940 result.param = (const struct mem_param *)0;
1941 result.dimm_mask = -1;
1945 static unsigned convert_to_1_4(unsigned value)
1947 static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 };
1950 /* We need to convert value to more readable */
1951 valuex = fraction [value & 0x7];
1955 int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
1960 value = spd_read_byte(spd_device, SPD_TRC);
1963 printk_raminit("update_dimm_Trc: tRC (41) = %08x\n", value);
1965 value2 = spd_read_byte(spd_device, SPD_TRC -1);
1967 value += convert_to_1_4(value2>>4);
1970 printk_raminit("update_dimm_Trc: tRC final value = %i\n", value);
1972 clocks = (value + param->divisor - 1)/param->divisor;
1973 printk_raminit("update_dimm_Trc: clocks = %i\n", clocks);
1975 if (clocks < DTL_TRC_MIN) {
1976 #warning We should die here or at least disable this bank.
1977 printk_notice("update_dimm_Trc: can't refresh fast enough, "
1978 "want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN);
1979 clocks = DTL_TRC_MIN;
1984 static int update_dimm_Trc(const struct mem_controller *ctrl,
1985 const struct mem_param *param,
1986 int i, long dimm_mask)
1988 int clocks, old_clocks;
1990 u32 spd_device = ctrl->channel0[i];
1992 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
1993 spd_device = ctrl->channel1[i];
1996 clocks = get_dimm_Trc_clocks(spd_device, param);
1999 if (clocks > DTL_TRC_MAX) {
2002 printk_raminit("update_dimm_Trc: clocks after adjustment = %i\n", clocks);
2004 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
2005 old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
2006 if (old_clocks >= clocks) { //?? someone did it
2007 // clocks = old_clocks;
2010 dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
2011 dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
2012 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2016 static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
2018 unsigned clocks, old_clocks;
2022 u32 spd_device = ctrl->channel0[i];
2024 if (!(meminfo->dimm_mask & (1 << i)) && (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2025 spd_device = ctrl->channel1[i];
2026 ch_b = 2; /* offset to channelB trfc setting */
2029 //get the cs_size --> logic dimm size
2030 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2035 value = 6 - log2(value); //4-->4, 8-->3, 16-->2
2037 clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
2039 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2041 old_clocks = ((dth >> (DTH_TRFC0_SHIFT + ((i + ch_b) * 3))) & DTH_TRFC_MASK);
2043 if (old_clocks >= clocks) { // some one did it?
2046 dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3)));
2047 dth |= clocks << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3));
2048 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2052 static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
2054 unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
2056 unsigned clocks, old_clocks;
2059 u32 spd_device = ctrl->channel0[i];
2061 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2062 spd_device = ctrl->channel1[i];
2065 value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns
2066 if (value < 0) return -1;
2068 clocks = (value + param->divisor -1)/param->divisor;
2069 if (clocks < TT_MIN) {
2073 if (clocks > TT_MAX) {
2074 printk_info("warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
2078 dtl = pci_read_config32(ctrl->f2, TT_REG);
2080 old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
2081 if (old_clocks >= clocks) { //some one did it?
2082 // clocks = old_clocks;
2085 dtl &= ~(TT_MASK << TT_SHIFT);
2086 dtl |= ((clocks - TT_BASE) << TT_SHIFT);
2087 pci_write_config32(ctrl->f2, TT_REG, dtl);
2092 static int update_dimm_Trcd(const struct mem_controller *ctrl,
2093 const struct mem_param *param, int i, long dimm_mask)
2095 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
2098 static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2100 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
2103 static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2105 unsigned clocks, old_clocks;
2108 u32 spd_device = ctrl->channel0[i];
2110 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2111 spd_device = ctrl->channel1[i];
2114 value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns
2115 if (value < 0) return -1;
2116 printk_raminit("update_dimm_Tras: 0 value= %08x\n", value);
2118 value <<= 2; //convert it to in 1/4ns
2121 printk_raminit("update_dimm_Tras: 1 value= %08x\n", value);
2123 clocks = (value + param->divisor - 1)/param->divisor;
2124 printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor);
2125 printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks);
2126 if (clocks < DTL_TRAS_MIN) {
2127 clocks = DTL_TRAS_MIN;
2130 if (clocks > DTL_TRAS_MAX) {
2134 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
2135 old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
2136 if (old_clocks >= clocks) { // someone did it?
2140 dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
2141 dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
2142 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2146 static int update_dimm_Trp(const struct mem_controller *ctrl,
2147 const struct mem_param *param, int i, long dimm_mask)
2149 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX);
2153 static int update_dimm_Trtp(const struct mem_controller *ctrl,
2154 const struct mem_param *param, int i, struct mem_info *meminfo)
2156 /* need to figure if it is 32 byte burst or 64 bytes burst */
2158 if (!meminfo->is_Width128) {
2160 dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2161 if ((dword & DCL_BurstLength32)) offset = 0;
2163 return update_dimm_TT_1_4(ctrl, param, i, meminfo->dimm_mask, DRAM_TIMING_LOW, SPD_TRTP, DTL_TRTP_SHIFT, DTL_TRTP_MASK, DTL_TRTP_BASE+offset, DTL_TRTP_MIN+offset, DTL_TRTP_MAX+offset);
2167 static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2169 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TWR, DTL_TWR_SHIFT, DTL_TWR_MASK, DTL_TWR_BASE, DTL_TWR_MIN, DTL_TWR_MAX);
2173 static int update_dimm_Tref(const struct mem_controller *ctrl,
2174 const struct mem_param *param, int i, long dimm_mask)
2176 uint32_t dth, dth_old;
2178 u32 spd_device = ctrl->channel0[i];
2180 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2181 spd_device = ctrl->channel1[i];
2184 value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
2185 if (value < 0) return -1;
2193 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2196 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
2197 dth |= (value << DTH_TREF_SHIFT);
2198 if (dth_old != dth) {
2199 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2205 static void set_4RankRDimm(const struct mem_controller *ctrl,
2206 const struct mem_param *param, struct mem_info *meminfo)
2208 #if QRANK_DIMM_SUPPRT == 1
2213 if (!(meminfo->is_registered)) return;
2217 for (i = 0; i < DIMM_SOCKETS; i++) {
2218 if (!(dimm_mask & (1 << i))) {
2222 if (meminfo->sz.rank == 4) {
2230 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2231 dch |= DCH_FourRankRDimm;
2232 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2238 static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
2239 struct mem_info *meminfo)
2245 uint32_t mask_single_rank;
2246 uint32_t mask_page_1k;
2248 #if QRANK_DIMM_SUPPORT == 1
2252 long dimm_mask = meminfo->dimm_mask;
2257 mask_single_rank = 0;
2260 for (i = 0; i < DIMM_SOCKETS; i++) {
2261 u32 spd_device = ctrl->channel0[i];
2262 if (!(dimm_mask & (1 << i))) {
2263 if (dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2264 spd_device = ctrl->channel1[i];
2270 if (meminfo->sz[i].rank == 1) {
2271 mask_single_rank |= 1<<i;
2274 if (meminfo->sz[i].col==10) {
2275 mask_page_1k |= 1<<i;
2279 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2281 #if QRANK_DIMM_SUPPORT == 1
2282 rank = meminfo->sz[i].rank;
2287 #if QRANK_DIMM_SUPPORT == 1
2289 mask_x4 |= 1<<(i+2);
2292 } else if (value==16) {
2294 #if QRANK_DIMM_SUPPORT == 1
2296 mask_x16 |= 1<<(i+2);
2303 meminfo->x4_mask= mask_x4;
2304 meminfo->x16_mask = mask_x16;
2306 meminfo->single_rank_mask = mask_single_rank;
2307 meminfo->page_1k_mask = mask_page_1k;
2314 static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2317 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2318 dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT);
2319 dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT);
2320 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2324 static int count_ones(uint32_t dimm_mask)
2329 for (index = 0; index < (2 * DIMM_SOCKETS); index++, dimm_mask >>= 1) {
2330 if (dimm_mask & 1) {
2338 static void set_DramTerm(const struct mem_controller *ctrl,
2339 const struct mem_param *param, struct mem_info *meminfo)
2345 if (param->divisor == 100) { //DDR2 800
2346 if (meminfo->is_Width128) {
2347 if (count_ones(meminfo->dimm_mask & 0x0f)==2) {
2355 #if DIMM_SUPPORT == 0x0204
2356 odt = 0x2; /* 150 ohms */
2359 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2360 dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
2361 dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
2362 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2366 static void set_ecc(const struct mem_controller *ctrl,
2367 const struct mem_param *param, struct mem_info *meminfo)
2372 uint32_t dcl, nbcap;
2373 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
2374 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2375 dcl &= ~DCL_DimmEccEn;
2376 if (nbcap & NBCAP_ECC) {
2377 dcl |= DCL_DimmEccEn;
2379 if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
2380 dcl &= ~DCL_DimmEccEn;
2382 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2384 meminfo->is_ecc = 1;
2385 if (!(dcl & DCL_DimmEccEn)) {
2386 meminfo->is_ecc = 0;
2387 return; // already disabled the ECC, so don't need to read SPD any more
2390 for (i = 0; i < DIMM_SOCKETS; i++) {
2391 u32 spd_device = ctrl->channel0[i];
2392 if (!(meminfo->dimm_mask & (1 << i))) {
2393 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2394 spd_device = ctrl->channel1[i];
2395 printk_debug("set_ecc spd_device: 0x%x\n", spd_device);
2401 value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONF_TYPE);
2403 if (!(value & SPD_DIMM_CONF_TYPE_ECC)) {
2404 dcl &= ~DCL_DimmEccEn;
2405 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2406 meminfo->is_ecc = 0;
2414 static int update_dimm_Twtr(const struct mem_controller *ctrl,
2415 const struct mem_param *param, int i, long dimm_mask)
2417 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX);
2420 static void set_TT(const struct mem_controller *ctrl,
2421 const struct mem_param *param, unsigned TT_REG, unsigned TT_SHIFT,
2422 unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX,
2423 unsigned val, const char *str)
2427 if ((val < TT_MIN) || (val > TT_MAX)) {
2432 reg = pci_read_config32(ctrl->f2, TT_REG);
2433 reg &= ~(TT_MASK << TT_SHIFT);
2434 reg |= ((val - TT_BASE) << TT_SHIFT);
2435 pci_write_config32(ctrl->f2, TT_REG, reg);
2440 static void set_TrwtTO(const struct mem_controller *ctrl,
2441 const struct mem_param *param)
2443 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO");
2447 static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param)
2449 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd");
2453 static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param)
2455 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
2459 static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
2461 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
2465 static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
2467 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
2471 static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2473 static const uint8_t faw_1k[] = {8, 10, 13, 14};
2474 static const uint8_t faw_2k[] = {10, 14, 17, 18};
2475 unsigned memclkfreq_index;
2479 memclkfreq_index = param->dch_memclk;
2481 if (meminfo->page_1k_mask != 0) { //1k page
2482 faw = faw_1k[memclkfreq_index];
2484 faw = faw_2k[memclkfreq_index];
2487 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
2492 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
2498 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2499 dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
2501 //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
2505 dch |= ((async_lat - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
2506 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2510 static void set_SlowAccessMode(const struct mem_controller *ctrl)
2514 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2518 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2523 DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
2524 DRAM_ADDR_TIMING_CTRL 04, 0x24
2526 static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo)
2530 unsigned SlowAccessMode = 0;
2532 long dimm_mask = meminfo->dimm_mask & 0x0f;
2534 #if DIMM_SUPPORT==0x0104 /* DDR2 and REG */
2537 dwordx = 0x002f0000;
2538 switch (meminfo->memclk_set) {
2539 case DCH_MemClkFreq_266MHz:
2540 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2541 dwordx = 0x002f2700;
2544 case DCH_MemClkFreq_333MHz:
2545 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2546 if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
2547 dwordx = 0x002f2f00;
2551 case DCH_MemClkFreq_400MHz:
2552 dwordx = 0x002f3300;
2558 #if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
2560 dwordx = 0x002F2F00;
2562 switch (meminfo->memclk_set) {
2563 case DCH_MemClkFreq_200MHz: /* nothing to be set here */
2565 case DCH_MemClkFreq_266MHz:
2566 if ((meminfo->single_rank_mask == 0)
2567 && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
2568 dwordx = 0x002C2C00; /* Double rank x8 */
2569 /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
2571 case DCH_MemClkFreq_333MHz:
2572 if ((meminfo->single_rank_mask == 1)
2573 && (meminfo->x16_mask == 1)) /* SR x16 */
2574 dwordx = 0x00272700;
2575 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2576 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2578 dwordx = 0x00002800;
2579 } else { /* SR x8, DR x16 */
2580 dwordx = 0x002A2A00;
2583 case DCH_MemClkFreq_400MHz:
2584 if ((meminfo->single_rank_mask == 1)
2585 && (meminfo->x16_mask == 1)) /* SR x16 */
2586 dwordx = 0x00292900;
2587 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2588 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2590 dwordx = 0x00002A00;
2591 } else { /* SR x8, DR x16 */
2592 dwordx = 0x002A2A00;
2598 #if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
2599 /* for UNBUF DIMM */
2601 dwordx = 0x002f2f00;
2602 switch (meminfo->memclk_set) {
2603 case DCH_MemClkFreq_200MHz:
2604 if (dimm_mask == 0x03) {
2609 case DCH_MemClkFreq_266MHz:
2610 if (dimm_mask == 0x03) {
2613 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2614 switch (meminfo->single_rank_mask) {
2616 dwordx = 0x00002f00; //x8 single Rank
2619 dwordx = 0x00342f00; //x8 double Rank
2622 dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
2624 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2625 dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
2626 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2627 dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
2631 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
2632 dwordx = 0x002f2f00;
2634 dwordx = 0x002b2f00;
2638 case DCH_MemClkFreq_333MHz:
2639 dwordx = 0x00202220;
2640 if (dimm_mask == 0x03) {
2643 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2644 switch (meminfo->single_rank_mask) {
2646 dwordx = 0x00302220; //x8 single Rank
2649 dwordx = 0x002b2220; //x8 double Rank
2652 dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
2654 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2655 dwordx = 0x002c2220; //x8 Double Rank and x16 single Rank mixed
2656 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2657 dwordx = 0x002c2220; //x16 single Rank and x8 double Rank mixed
2661 case DCH_MemClkFreq_400MHz:
2662 dwordx = 0x00202520;
2664 if (dimm_mask == 0x03) {
2672 printk_raminit("\tdimm_mask = %08x\n", meminfo->dimm_mask);
2673 printk_raminit("\tx4_mask = %08x\n", meminfo->x4_mask);
2674 printk_raminit("\tx16_mask = %08x\n", meminfo->x16_mask);
2675 printk_raminit("\tsingle_rank_mask = %08x\n", meminfo->single_rank_mask);
2676 printk_raminit("\tODC = %08x\n", dword);
2677 printk_raminit("\tAddr Timing= %08x\n", dwordx);
2680 #if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2681 if (SlowAccessMode) {
2682 set_SlowAccessMode(ctrl);
2686 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
2687 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2688 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2690 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2691 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2693 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2694 pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword);
2695 if (meminfo->is_Width128) {
2696 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2699 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2700 pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx);
2701 if (meminfo->is_Width128) {
2702 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2708 static void set_RDqsEn(const struct mem_controller *ctrl,
2709 const struct mem_param *param, struct mem_info *meminfo)
2711 #if CPU_SOCKET_TYPE==0x10
2712 //only need to set for reg and x8
2715 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2718 if ((!meminfo->x4_mask) && (!meminfo->x16_mask)) {
2722 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2727 static void set_idle_cycle_limit(const struct mem_controller *ctrl,
2728 const struct mem_param *param)
2731 /* AMD says to Hardcode this */
2732 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
2733 dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT);
2734 dcm |= DCM_ILD_lmt_16 << DCM_ILD_lmt_SHIFT;
2736 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
2740 static void set_RdWrQByp(const struct mem_controller *ctrl,
2741 const struct mem_param *param)
2743 set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
2747 static long spd_set_dram_timing(const struct mem_controller *ctrl,
2748 const struct mem_param *param,
2749 struct mem_info *meminfo)
2753 for (i = 0; i < DIMM_SOCKETS; i++) {
2755 if (!(meminfo->dimm_mask & (1 << i)) &&
2756 !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) {
2759 printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i);
2760 /* DRAM Timing Low Register */
2761 printk_raminit("\ttrc\n");
2762 if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2764 printk_raminit("\ttrcd\n");
2765 if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2767 printk_raminit("\ttrrd\n");
2768 if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2770 printk_raminit("\ttras\n");
2771 if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2773 printk_raminit("\ttrp\n");
2774 if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2776 printk_raminit("\ttrtp\n");
2777 if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2779 printk_raminit("\ttwr\n");
2780 if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2782 /* DRAM Timing High Register */
2783 printk_raminit("\ttref\n");
2784 if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2786 printk_raminit("\ttwtr\n");
2787 if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2789 printk_raminit("\ttrfc\n");
2790 if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2792 /* DRAM Config Low */
2796 printk_debug("spd_set_dram_timing dimm_err!\n");
2800 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
2803 get_extra_dimm_mask(ctrl, meminfo); // will be used by RDqsEn and dimm_x4
2804 /* DRAM Timing Low Register */
2806 /* DRAM Timing High Register */
2807 set_TrwtTO(ctrl, param);
2808 set_Twrrd (ctrl, param);
2809 set_Twrwr (ctrl, param);
2810 set_Trdrd (ctrl, param);
2812 set_4RankRDimm(ctrl, param, meminfo);
2814 /* DRAM Config High */
2815 set_Tfaw(ctrl, param, meminfo);
2816 set_DcqBypassMax(ctrl, param);
2817 set_max_async_latency(ctrl, param);
2818 set_RDqsEn(ctrl, param, meminfo);
2820 /* DRAM Config Low */
2821 set_ecc(ctrl, param, meminfo);
2822 set_dimm_x4(ctrl, param, meminfo);
2823 set_DramTerm(ctrl, param, meminfo);
2825 /* DRAM Control Misc */
2826 set_idle_cycle_limit(ctrl, param);
2827 set_RdWrQByp(ctrl, param);
2829 return meminfo->dimm_mask;
2832 static void sdram_set_spd_registers(const struct mem_controller *ctrl,
2833 struct sys_info *sysinfo)
2835 struct spd_set_memclk_result result;
2836 const struct mem_param *param;
2837 struct mem_param paramx;
2838 struct mem_info *meminfo;
2840 if (!sysinfo->ctrl_present[ctrl->node_id]) {
2844 meminfo = &sysinfo->meminfo[ctrl->node_id];
2846 printk_debug("sdram_set_spd_registers: paramx :%p\n", ¶mx);
2848 activate_spd_rom(ctrl);
2849 meminfo->dimm_mask = spd_detect_dimms(ctrl);
2851 printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask);
2853 if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
2855 printk_debug("No memory for this cpu\n");
2858 meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
2859 printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask);
2860 if (meminfo->dimm_mask == -1)
2863 meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo);
2864 printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask);
2865 if (meminfo->dimm_mask == -1)
2868 meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo);
2869 printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask);
2870 if (meminfo->dimm_mask == -1)
2873 result = spd_set_memclk(ctrl, meminfo);
2874 param = result.param;
2875 meminfo->dimm_mask = result.dimm_mask;
2876 printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask);
2877 if (meminfo->dimm_mask == -1)
2880 //store memclk set to sysinfo, incase we need rebuilt param again
2881 meminfo->memclk_set = param->dch_memclk;
2883 memcpy(¶mx, param, sizeof(paramx));
2885 paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor);
2887 meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo);
2888 printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask);
2889 if (meminfo->dimm_mask == -1)
2892 order_dimms(ctrl, meminfo);
2896 /* Unrecoverable error reading SPD data */
2897 die("Unrecoverable error reading SPD data. No qualified DIMMs?");
2901 #define TIMEOUT_LOOPS 300000
2903 #include "raminit_f_dqs.c"
2905 #if HW_MEM_HOLE_SIZEK != 0
2906 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
2909 uint32_t carry_over;
2911 uint32_t base, limit;
2916 carry_over = (4*1024*1024) - hole_startk;
2918 for (ii=controllers - 1;ii>i;ii--) {
2919 base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
2920 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2923 limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
2924 limit += (carry_over << 2 );
2925 base += (carry_over << 2 );
2926 for (j = 0; j < controllers; j++) {
2927 pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
2928 pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
2931 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2932 limit += (carry_over << 2);
2933 for (j = 0; j < controllers; j++) {
2934 pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit);
2937 base = pci_read_config32(dev, 0x40 + (i << 3));
2938 basek = (base & 0xffff0000) >> 2;
2939 if (basek == hole_startk) {
2940 //don't need set memhole here, because hole off set will be 0, overflow
2941 //so need to change base reg instead, new basek will be 4*1024*1024
2943 base |= (4*1024*1024)<<2;
2944 for (j = 0; j < controllers; j++) {
2945 pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
2948 hoist = /* hole start address */
2949 ((hole_startk << 10) & 0xff000000) +
2950 /* hole address to memory controller address */
2951 (((basek + carry_over) >> 6) & 0x0000ff00) +
2954 pci_write_config32(dev, 0xf0, hoist);
2960 static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
2963 uint32_t hole_startk;
2966 hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
2968 #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
2969 /* We need to double check if the hole_startk is valid, if it is equal
2970 to basek, we need to decrease it some */
2972 for (i=0; i<controllers; i++) {
2975 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2976 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2979 base_k = (base & 0xffff0000) >> 2;
2980 if (base_k == hole_startk) {
2981 /* decrease mem hole startk to make sure it is
2982 on middle of previous node */
2983 hole_startk -= (base_k - basek_pri) >> 1;
2984 break; //only one hole
2989 /* find node index that need do set hole */
2990 for (i=0; i < controllers; i++) {
2991 uint32_t base, limit;
2992 unsigned base_k, limit_k;
2993 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2994 if ((base & ((1 << 1) | (1 << 0))) != ((1 << 1) | (1 << 0))) {
2997 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2998 base_k = (base & 0xffff0000) >> 2;
2999 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
3000 if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
3002 hoist_memory(controllers, ctrl, hole_startk, i);
3003 end_k = memory_end_k(ctrl, controllers);
3004 set_top_mem(end_k, hole_startk);
3005 break; //only one hole
3013 static void sdram_enable(int controllers, const struct mem_controller *ctrl,
3014 struct sys_info *sysinfo)
3018 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3019 unsigned cpu_f0_f1[8];
3020 /* FIXME: How about 32 node machine later? */
3023 printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
3027 /* Error if I don't have memory */
3028 if (memory_end_k(ctrl, controllers) == 0) {
3032 /* Before enabling memory start the memory clocks */
3033 for (i = 0; i < controllers; i++) {
3035 if (!sysinfo->ctrl_present[ i ])
3037 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3039 /* if no memory installed, disabled the interface */
3040 if (sysinfo->meminfo[i].dimm_mask==0x00){
3041 dch |= DCH_DisDramInterface;
3042 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3045 dch |= DCH_MemClkFreqVal;
3046 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3047 /* address timing and Output driver comp Control */
3048 set_misc_timing(ctrl+i, sysinfo->meminfo+i );
3052 /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
3053 memreset(controllers, ctrl);
3055 printk_debug("prepare to InitDram:");
3056 for (i=0; i<10; i++) {
3057 printk_debug("%08x", i);
3058 print_debug("\b\b\b\b\b\b\b\b");
3063 for (i = 0; i < controllers; i++) {
3065 if (!sysinfo->ctrl_present[ i ])
3067 /* Skip everything if I don't have any memory on this controller */
3068 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3069 if (!(dch & DCH_MemClkFreqVal)) {
3074 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3075 if (dcl & DCL_DimmEccEn) {
3077 printk_spew("ECC enabled\n");
3078 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
3080 if (dcl & DCL_Width128) {
3081 mnc |= MNC_CHIPKILL_EN;
3083 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
3086 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3087 cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
3089 //Rev F0/F1 workaround
3091 /* Set the DqsRcvEnTrain bit */
3092 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
3093 dword |= DC_DqsRcvEnTrain;
3094 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
3101 /* Set the DqsRcvEnTrain bit */
3102 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
3103 dword |= DC_DqsRcvEnTrain;
3104 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
3107 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3108 dcl |= DCL_InitDram;
3109 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3112 for (i = 0; i < controllers; i++) {
3113 uint32_t dcl, dch, dcm;
3114 if (!sysinfo->ctrl_present[ i ])
3116 /* Skip everything if I don't have any memory on this controller */
3117 if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
3119 printk_debug("Initializing memory: ");
3122 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3124 if ((loops & 1023) == 0) {
3127 } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
3128 if (loops >= TIMEOUT_LOOPS) {
3129 printk_debug(" failed\n");
3133 /* Wait until it is safe to touch memory */
3135 dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
3136 } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
3138 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3142 print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3143 print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
3145 if (tsc.lo<tsc0[i].lo) {
3148 tsc.lo -= tsc0[i].lo;
3149 tsc.hi -= tsc0[i].hi;
3151 tsc0[i].lo = tsc.lo;
3152 tsc0[i].hi = tsc.hi;
3154 print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3157 printk_debug(" done\n");
3160 #if HW_MEM_HOLE_SIZEK != 0
3161 /* init hw mem hole here */
3162 /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
3163 set_hw_mem_hole(controllers, ctrl);
3166 /* store tom to sysinfo, and it will be used by dqs_timing */
3170 msr = rdmsr(TOP_MEM);
3171 sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2;
3174 msr = rdmsr(TOP_MEM2);
3175 sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2;
3178 for (i = 0; i < controllers; i++) {
3179 sysinfo->mem_trained[i] = 0;
3181 if (!sysinfo->ctrl_present[ i ])
3184 /* Skip everything if I don't have any memory on this controller */
3185 if (sysinfo->meminfo[i].dimm_mask==0x00)
3188 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
3192 #if MEM_TRAIN_SEQ == 0
3193 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3194 dqs_timing(controllers, ctrl, tsc0, sysinfo);
3196 dqs_timing(controllers, ctrl, sysinfo);
3200 #if MEM_TRAIN_SEQ == 2
3201 /* need to enable mtrr, so dqs training could access the test address */
3202 setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
3205 for (i = 0; i < controllers; i++) {
3206 /* Skip everything if I don't have any memory on this controller */
3207 if (sysinfo->mem_trained[i]!=0x80)
3210 dqs_timing(i, &ctrl[i], sysinfo, 1);
3212 #if MEM_TRAIN_SEQ == 1
3213 break; // only train the first node with ram
3217 #if MEM_TRAIN_SEQ == 2
3218 clear_mtrr_dqs(sysinfo->tom2_k);
3223 #if MEM_TRAIN_SEQ != 1
3224 wait_all_core0_mem_trained(sysinfo);
3230 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
3231 const uint16_t *spd_addr)
3235 struct mem_controller *ctrl;
3236 for (i=0;i<controllers; i++) {
3239 ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
3240 ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
3241 ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
3242 ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
3244 if (spd_addr == (void *)0) continue;
3246 for (j=0;j<DIMM_SOCKETS;j++) {
3247 ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
3248 ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];