1 #include <cpu/k8/mtrr.h>
7 #define DRAM_CSBASE 0x40
8 #define DRAM_CSMASK 0x60
9 #define DRAM_BANK_ADDR_MAP 0x80
10 #define DRAM_TIMING_LOW 0x88
11 #define DTL_TCL_SHIFT 0
12 #define DTL_TCL_MASK 0x7
16 #define DTL_TRC_SHIFT 4
17 #define DTL_TRC_MASK 0xf
18 #define DTL_TRC_BASE 7
20 #define DTL_TRC_MAX 22
21 #define DTL_TRFC_SHIFT 8
22 #define DTL_TRFC_MASK 0xf
23 #define DTL_TRFC_BASE 9
24 #define DTL_TRFC_MIN 9
25 #define DTL_TRFC_MAX 24
26 #define DTL_TRCD_SHIFT 12
27 #define DTL_TRCD_MASK 0x7
28 #define DTL_TRCD_BASE 0
29 #define DTL_TRCD_MIN 2
30 #define DTL_TRCD_MAX 6
31 #define DTL_TRRD_SHIFT 16
32 #define DTL_TRRD_MASK 0x7
33 #define DTL_TRRD_BASE 0
34 #define DTL_TRRD_MIN 2
35 #define DTL_TRRD_MAX 4
36 #define DTL_TRAS_SHIFT 20
37 #define DTL_TRAS_MASK 0xf
38 #define DTL_TRAS_BASE 0
39 #define DTL_TRAS_MIN 5
40 #define DTL_TRAS_MAX 15
41 #define DTL_TRP_SHIFT 24
42 #define DTL_TRP_MASK 0x7
43 #define DTL_TRP_BASE 0
46 #define DTL_TWR_SHIFT 28
47 #define DTL_TWR_MASK 0x1
48 #define DTL_TWR_BASE 2
51 #define DRAM_TIMING_HIGH 0x8c
52 #define DTH_TWTR_SHIFT 0
53 #define DTH_TWTR_MASK 0x1
54 #define DTH_TWTR_BASE 1
55 #define DTH_TWTR_MIN 1
56 #define DTH_TWTR_MAX 2
57 #define DTH_TRWT_SHIFT 4
58 #define DTH_TRWT_MASK 0x7
59 #define DTH_TRWT_BASE 1
60 #define DTH_TRWT_MIN 1
61 #define DTH_TRWT_MAX 6
62 #define DTH_TREF_SHIFT 8
63 #define DTH_TREF_MASK 0x1f
64 #define DTH_TREF_100MHZ_4K 0x00
65 #define DTH_TREF_133MHZ_4K 0x01
66 #define DTH_TREF_166MHZ_4K 0x02
67 #define DTH_TREF_200MHZ_4K 0x03
68 #define DTH_TREF_100MHZ_8K 0x08
69 #define DTH_TREF_133MHZ_8K 0x09
70 #define DTH_TREF_166MHZ_8K 0x0A
71 #define DTH_TREF_200MHZ_8K 0x0B
72 #define DTH_TWCL_SHIFT 20
73 #define DTH_TWCL_MASK 0x7
74 #define DTH_TWCL_BASE 1
75 #define DTH_TWCL_MIN 1
76 #define DTH_TWCL_MAX 2
77 #define DRAM_CONFIG_LOW 0x90
78 #define DCL_DLL_Disable (1<<0)
79 #define DCL_D_DRV (1<<1)
80 #define DCL_QFC_EN (1<<2)
81 #define DCL_DisDqsHys (1<<3)
82 #define DCL_DramInit (1<<8)
83 #define DCL_DramEnable (1<<10)
84 #define DCL_MemClrStatus (1<<11)
85 #define DCL_ESR (1<<12)
86 #define DCL_SRS (1<<13)
87 #define DCL_128BitEn (1<<16)
88 #define DCL_DimmEccEn (1<<17)
89 #define DCL_UnBufDimm (1<<18)
90 #define DCL_32ByteEn (1<<19)
91 #define DCL_x4DIMM_SHIFT 20
92 #define DRAM_CONFIG_HIGH 0x94
93 #define DCH_ASYNC_LAT_SHIFT 0
94 #define DCH_ASYNC_LAT_MASK 0xf
95 #define DCH_ASYNC_LAT_BASE 0
96 #define DCH_ASYNC_LAT_MIN 0
97 #define DCH_ASYNC_LAT_MAX 15
98 #define DCH_RDPREAMBLE_SHIFT 8
99 #define DCH_RDPREAMBLE_MASK 0xf
100 #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
101 #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
102 #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
103 #define DCH_IDLE_LIMIT_SHIFT 16
104 #define DCH_IDLE_LIMIT_MASK 0x7
105 #define DCH_IDLE_LIMIT_0 0
106 #define DCH_IDLE_LIMIT_4 1
107 #define DCH_IDLE_LIMIT_8 2
108 #define DCH_IDLE_LIMIT_16 3
109 #define DCH_IDLE_LIMIT_32 4
110 #define DCH_IDLE_LIMIT_64 5
111 #define DCH_IDLE_LIMIT_128 6
112 #define DCH_IDLE_LIMIT_256 7
113 #define DCH_DYN_IDLE_CTR_EN (1 << 19)
114 #define DCH_MEMCLK_SHIFT 20
115 #define DCH_MEMCLK_MASK 0x7
116 #define DCH_MEMCLK_100MHZ 0
117 #define DCH_MEMCLK_133MHZ 2
118 #define DCH_MEMCLK_166MHZ 5
119 #define DCH_MEMCLK_200MHZ 7
120 #define DCH_MEMCLK_VALID (1 << 25)
121 #define DCH_MEMCLK_EN0 (1 << 26)
122 #define DCH_MEMCLK_EN1 (1 << 27)
123 #define DCH_MEMCLK_EN2 (1 << 28)
124 #define DCH_MEMCLK_EN3 (1 << 29)
127 #define MCA_NB_CONFIG 0x44
128 #define MNC_ECC_EN (1 << 22)
129 #define MNC_CHIPKILL_EN (1 << 23)
130 #define SCRUB_CONTROL 0x58
134 #define SCRUB_160ns 3
135 #define SCRUB_320ns 4
136 #define SCRUB_640ns 5
137 #define SCRUB_1_28us 6
138 #define SCRUB_2_56us 7
139 #define SCRUB_5_12us 8
140 #define SCRUB_10_2us 9
141 #define SCRUB_20_5us 10
142 #define SCRUB_41_0us 11
143 #define SCRUB_81_9us 12
144 #define SCRUB_163_8us 13
145 #define SCRUB_327_7us 14
146 #define SCRUB_655_4us 15
147 #define SCRUB_1_31ms 16
148 #define SCRUB_2_62ms 17
149 #define SCRUB_5_24ms 18
150 #define SCRUB_10_49ms 19
151 #define SCRUB_20_97ms 20
152 #define SCRUB_42ms 21
153 #define SCRUB_84ms 22
154 #define SC_DRAM_SCRUB_RATE_SHFIT 0
155 #define SC_DRAM_SCRUB_RATE_MASK 0x1f
156 #define SC_L2_SCRUB_RATE_SHIFT 8
157 #define SC_L2_SCRUB_RATE_MASK 0x1f
158 #define SC_L1D_SCRUB_RATE_SHIFT 16
159 #define SC_L1D_SCRUB_RATE_MASK 0x1f
160 #define SCRUB_ADDR_LOW 0x5C
161 #define SCRUB_ADDR_HIGH 0x60
162 #define NORTHBRIDGE_CAP 0xE8
163 #define NBCAP_128Bit 0x0001
164 #define NBCAP_MP 0x0002
165 #define NBCAP_BIG_MP 0x0004
166 #define NBCAP_ECC 0x0004
167 #define NBCAP_CHIPKILL_ECC 0x0010
168 #define NBCAP_MEMCLK_SHIFT 5
169 #define NBCAP_MEMCLK_MASK 3
170 #define NBCAP_MEMCLK_100MHZ 3
171 #define NBCAP_MEMCLK_133MHZ 2
172 #define NBCAP_MEMCLK_166MHZ 1
173 #define NBCAP_MEMCLK_200MHZ 0
174 #define NBCAP_MEMCTRL 0x0100
177 static void setup_resource_map(const unsigned int *register_values, int max)
181 unsigned int amd8111_link_nr;
183 print_debug("setting up resource map....\r\n");
185 * determine the HT link number the southbridge is connected to
186 * bits 8-9 of the Unit ID register
188 amd8111_link_nr = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64) & 0x00000300) >> 8;
189 print_debug(" AMD8111 southbridge is connected to HT link ");
190 print_debug_hex32(amd8111_link_nr);
194 print_debug("setting up resource map....\r\n");
195 for(i = 0; i < max; i += 3) {
201 print_debug_hex32(register_values[i]);
203 print_debug_hex32(register_values[i+2]);
206 dev = register_values[i] & ~0xff;
207 where = register_values[i] & 0xff;
208 reg = pci_read_config32(dev, where);
209 reg &= register_values[i+1];
210 reg |= register_values[i+2];
213 * set correct HT link to the southbridge
214 * otherwise we cut of the acces to the flash we are from
218 reg |= amd8111_link_nr << 4;
220 reg |= amd8111_link_nr << 4;
222 reg |= amd8111_link_nr << 8;
224 pci_write_config32(dev, where, reg);
226 reg = pci_read_config32(register_values[i]);
227 reg &= register_values[i+1];
228 reg |= register_values[i+2] & ~register_values[i+1];
229 pci_write_config32(register_values[i], reg);
232 print_debug("done.\r\n");
235 static void setup_default_resource_map(void)
237 static const unsigned int register_values[] = {
238 /* Careful set limit registers before base registers which contain the enables */
239 /* DRAM Limit i Registers
248 * [ 2: 0] Destination Node ID
258 * [10: 8] Interleave select
259 * specifies the values of A[14:12] to use with interleave enable.
261 * [31:16] DRAM Limit Address i Bits 39-24
262 * This field defines the upper address bits of a 40 bit address
263 * that define the end of the DRAM region.
265 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
266 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
267 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
268 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
269 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
270 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
271 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
272 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
273 /* DRAM Base i Registers
282 * [ 0: 0] Read Enable
285 * [ 1: 1] Write Enable
286 * 0 = Writes Disabled
289 * [10: 8] Interleave Enable
290 * 000 = No interleave
291 * 001 = Interleave on A[12] (2 nodes)
293 * 011 = Interleave on A[12] and A[14] (4 nodes)
297 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
299 * [13:16] DRAM Base Address i Bits 39-24
300 * This field defines the upper address bits of a 40-bit address
301 * that define the start of the DRAM region.
303 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
304 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
305 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
306 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
307 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
308 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
309 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
310 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
312 /* Memory-Mapped I/O Limit i Registers
321 * [ 2: 0] Destination Node ID
331 * [ 5: 4] Destination Link ID
338 * 0 = CPU writes may be posted
339 * 1 = CPU writes must be non-posted
340 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
341 * This field defines the upp adddress bits of a 40-bit address that
342 * defines the end of a memory-mapped I/O region n
344 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
345 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
346 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
347 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
348 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
349 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
350 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
351 PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
353 /* Memory-Mapped I/O Base i Registers
362 * [ 0: 0] Read Enable
365 * [ 1: 1] Write Enable
366 * 0 = Writes disabled
368 * [ 2: 2] Cpu Disable
369 * 0 = Cpu can use this I/O range
370 * 1 = Cpu requests do not use this I/O range
372 * 0 = base/limit registers i are read/write
373 * 1 = base/limit registers i are read-only
375 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
376 * This field defines the upper address bits of a 40bit address
377 * that defines the start of memory-mapped I/O region i
379 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
380 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
381 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
382 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
383 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
384 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
385 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
386 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
388 /* PCI I/O Limit i Registers
393 * [ 2: 0] Destination Node ID
403 * [ 5: 4] Destination Link ID
409 * [24:12] PCI I/O Limit Address i
410 * This field defines the end of PCI I/O region n
413 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
414 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
415 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
416 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
418 /* PCI I/O Base i Registers
423 * [ 0: 0] Read Enable
426 * [ 1: 1] Write Enable
427 * 0 = Writes Disabled
431 * 0 = VGA matches Disabled
432 * 1 = matches all address < 64K and where A[9:0] is in the
433 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
435 * 0 = ISA matches Disabled
436 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
437 * from matching agains this base/limit pair
439 * [24:12] PCI I/O Base i
440 * This field defines the start of PCI I/O region n
443 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
444 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
445 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
446 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
448 /* Config Base and Limit i Registers
453 * [ 0: 0] Read Enable
456 * [ 1: 1] Write Enable
457 * 0 = Writes Disabled
459 * [ 2: 2] Device Number Compare Enable
460 * 0 = The ranges are based on bus number
461 * 1 = The ranges are ranges of devices on bus 0
463 * [ 6: 4] Destination Node
473 * [ 9: 8] Destination Link
479 * [23:16] Bus Number Base i
480 * This field defines the lowest bus number in configuration region i
481 * [31:24] Bus Number Limit i
482 * This field defines the highest bus number in configuration regin i
484 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
485 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
486 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
487 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
490 max = sizeof(register_values)/sizeof(register_values[0]);
491 setup_resource_map(register_values, max);
494 static void sdram_set_registers(const struct mem_controller *ctrl)
496 static const unsigned int register_values[] = {
498 /* Careful set limit registers before base registers which contain the enables */
499 /* DRAM Limit i Registers
508 * [ 2: 0] Destination Node ID
518 * [10: 8] Interleave select
519 * specifies the values of A[14:12] to use with interleave enable.
521 * [31:16] DRAM Limit Address i Bits 39-24
522 * This field defines the upper address bits of a 40 bit address
523 * that define the end of the DRAM region.
525 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
526 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
527 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
528 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
529 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
530 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
531 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
532 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
533 /* DRAM Base i Registers
542 * [ 0: 0] Read Enable
545 * [ 1: 1] Write Enable
546 * 0 = Writes Disabled
549 * [10: 8] Interleave Enable
550 * 000 = No interleave
551 * 001 = Interleave on A[12] (2 nodes)
553 * 011 = Interleave on A[12] and A[14] (4 nodes)
557 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
559 * [13:16] DRAM Base Address i Bits 39-24
560 * This field defines the upper address bits of a 40-bit address
561 * that define the start of the DRAM region.
563 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
564 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
565 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
566 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
567 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
568 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
569 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
570 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
572 /* DRAM CS Base Address i Registers
581 * [ 0: 0] Chip-Select Bank Enable
585 * [15: 9] Base Address (19-13)
586 * An optimization used when all DIMM are the same size...
588 * [31:21] Base Address (35-25)
589 * This field defines the top 11 addresses bit of a 40-bit
590 * address that define the memory address space. These
591 * bits decode 32-MByte blocks of memory.
593 PCI_ADDR(0, 0x18, 2, 0x40), 0x001f01fe, 0x00000000,
594 PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00000000,
595 PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x00000000,
596 PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x00000000,
597 PCI_ADDR(0, 0x18, 2, 0x50), 0x001f01fe, 0x00000000,
598 PCI_ADDR(0, 0x18, 2, 0x54), 0x001f01fe, 0x00000000,
599 PCI_ADDR(0, 0x18, 2, 0x58), 0x001f01fe, 0x00000000,
600 PCI_ADDR(0, 0x18, 2, 0x5C), 0x001f01fe, 0x00000000,
601 /* DRAM CS Mask Address i Registers
610 * Select bits to exclude from comparison with the DRAM Base address register.
612 * [15: 9] Address Mask (19-13)
613 * Address to be excluded from the optimized case
615 * [29:21] Address Mask (33-25)
616 * The bits with an address mask of 1 are excluded from address comparison
620 PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000,
621 PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000,
622 PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00000000,
623 PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00000000,
624 PCI_ADDR(0, 0x18, 2, 0x70), 0xC01f01ff, 0x00000000,
625 PCI_ADDR(0, 0x18, 2, 0x74), 0xC01f01ff, 0x00000000,
626 PCI_ADDR(0, 0x18, 2, 0x78), 0xC01f01ff, 0x00000000,
627 PCI_ADDR(0, 0x18, 2, 0x7C), 0xC01f01ff, 0x00000000,
628 /* DRAM Bank Address Mapping Register
630 * Specify the memory module size
635 * 000 = 32Mbyte (Rows = 12 & Col = 8)
636 * 001 = 64Mbyte (Rows = 12 & Col = 9)
637 * 010 = 128Mbyte (Rows = 13 & Col = 9)|(Rows = 12 & Col = 10)
638 * 011 = 256Mbyte (Rows = 13 & Col = 10)|(Rows = 12 & Col = 11)
639 * 100 = 512Mbyte (Rows = 13 & Col = 11)|(Rows = 14 & Col = 10)
640 * 101 = 1Gbyte (Rows = 14 & Col = 11)|(Rows = 13 & Col = 12)
641 * 110 = 2Gbyte (Rows = 14 & Col = 12)
648 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000000,
649 /* DRAM Timing Low Register
651 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
661 * [ 7: 4] Trc (Row Cycle Time, Ras#-active to Ras#-active/bank auto refresh)
662 * 0000 = 7 bus clocks
663 * 0001 = 8 bus clocks
665 * 1110 = 21 bus clocks
666 * 1111 = 22 bus clocks
667 * [11: 8] Trfc (Row refresh Cycle time, Auto-refresh-active to RAS#-active or RAS#auto-refresh)
668 * 0000 = 9 bus clocks
669 * 0010 = 10 bus clocks
671 * 1110 = 23 bus clocks
672 * 1111 = 24 bus clocks
673 * [14:12] Trcd (Ras#-active to Case#-read/write Delay)
683 * [18:16] Trrd (Ras# to Ras# Delay)
693 * [23:20] Tras (Minmum Ras# Active Time)
694 * 0000 to 0100 = reserved
695 * 0101 = 5 bus clocks
697 * 1111 = 15 bus clocks
698 * [26:24] Trp (Row Precharge Time)
708 * [28:28] Twr (Write Recovery Time)
713 PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x02522001 /* 0x03623125 */ ,
714 /* DRAM Timing High Register
716 * [ 0: 0] Twtr (Write to Read Delay)
720 * [ 6: 4] Trwt (Read to Write Delay)
730 * [12: 8] Tref (Refresh Rate)
731 * 00000 = 100Mhz 4K rows
732 * 00001 = 133Mhz 4K rows
733 * 00010 = 166Mhz 4K rows
734 * 00011 = 200Mhz 4K rows
735 * 01000 = 100Mhz 8K/16K rows
736 * 01001 = 133Mhz 8K/16K rows
737 * 01010 = 166Mhz 8K/16K rows
738 * 01011 = 200Mhz 8K/16K rows
740 * [22:20] Twcl (Write CAS Latency)
741 * 000 = 1 Mem clock after CAS# (Unbuffered Dimms)
742 * 001 = 2 Mem clocks after CAS# (Registered Dimms)
745 PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0),
746 /* DRAM Config Low Register
748 * [ 0: 0] DLL Disable
757 * [ 3: 3] Disable DQS Hystersis (FIXME handle this one carefully)
758 * 0 = Enable DQS input filter
759 * 1 = Disable DQS input filtering
762 * 0 = Initialization done or not yet started.
763 * 1 = Initiate DRAM intialization sequence
764 * [ 9: 9] SO-Dimm Enable
766 * 1 = SO-Dimms present
768 * 0 = DRAM not enabled
769 * 1 = DRAM initialized and enabled
770 * [11:11] Memory Clear Status
771 * 0 = Memory Clear function has not completed
772 * 1 = Memory Clear function has completed
773 * [12:12] Exit Self-Refresh
774 * 0 = Exit from self-refresh done or not yet started
775 * 1 = DRAM exiting from self refresh
776 * [13:13] Self-Refresh Status
777 * 0 = Normal Operation
778 * 1 = Self-refresh mode active
779 * [15:14] Read/Write Queue Bypass Count
784 * [16:16] 128-bit/64-Bit
785 * 0 = 64bit Interface to DRAM
786 * 1 = 128bit Interface to DRAM
787 * [17:17] DIMM ECC Enable
788 * 0 = Some DIMMs do not have ECC
789 * 1 = ALL DIMMS have ECC bits
790 * [18:18] UnBuffered DIMMs
792 * 1 = Unbuffered DIMMS
793 * [19:19] Enable 32-Byte Granularity
794 * 0 = Optimize for 64byte bursts
795 * 1 = Optimize for 32byte bursts
796 * [20:20] DIMM 0 is x4
797 * [21:21] DIMM 1 is x4
798 * [22:22] DIMM 2 is x4
799 * [23:23] DIMM 3 is x4
801 * 1 = x4 DIMM present
802 * [24:24] Disable DRAM Receivers
803 * 0 = Receivers enabled
804 * 1 = Receivers disabled
806 * 000 = Arbiters chois is always respected
807 * 001 = Oldest entry in DCQ can be bypassed 1 time
808 * 010 = Oldest entry in DCQ can be bypassed 2 times
809 * 011 = Oldest entry in DCQ can be bypassed 3 times
810 * 100 = Oldest entry in DCQ can be bypassed 4 times
811 * 101 = Oldest entry in DCQ can be bypassed 5 times
812 * 110 = Oldest entry in DCQ can be bypassed 6 times
813 * 111 = Oldest entry in DCQ can be bypassed 7 times
816 PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000,
818 (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
819 (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)|
820 (2 << 14)|(0 << 13)|(0 << 12)|
821 (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
822 (0 << 3) |(0 << 1) |(0 << 0),
823 /* DRAM Config High Register
825 * [ 0: 3] Maximum Asynchronous Latency
830 * [11: 8] Read Preamble
848 * [18:16] Idle Cycle Limit
857 * [19:19] Dynamic Idle Cycle Center Enable
858 * 0 = Use Idle Cycle Limit
859 * 1 = Generate a dynamic Idle cycle limit
860 * [22:20] DRAM MEMCLK Frequency
870 * [25:25] Memory Clock Ratio Valid (FIXME carefully enable memclk)
871 * 0 = Disable MemClks
873 * [26:26] Memory Clock 0 Enable
876 * [27:27] Memory Clock 1 Enable
879 * [28:28] Memory Clock 2 Enable
882 * [29:29] Memory Clock 3 Enable
887 PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0,
888 (0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)|
889 (0 << 20)|(0 << 19)|(DCH_IDLE_LIMIT_16 << 16)|(0 << 8)|(0 << 0),
890 /* DRAM Delay Line Register
892 * Adjust the skew of the input DQS strobe relative to DATA
894 * [23:16] Delay Line Adjust
895 * Adjusts the DLL derived PDL delay by one or more delay stages
896 * in either the faster or slower direction.
897 * [24:24} Adjust Slower
899 * 1 = Adj is used to increase the PDL delay
900 * [25:25] Adjust Faster
902 * 1 = Adj is used to decrease the PDL delay
905 PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
906 /* DRAM Scrub Control Register
908 * [ 4: 0] DRAM Scrube Rate
910 * [12: 8] L2 Scrub Rate
912 * [20:16] Dcache Scrub
915 * 00000 = Do not scrub
937 * All Others = Reserved
939 PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
940 /* DRAM Scrub Address Low Register
942 * [ 0: 0] DRAM Scrubber Redirect Enable
944 * 1 = Scrubber Corrects errors found in normal operation
946 * [31: 6] DRAM Scrub Address 31-6
948 PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
949 /* DRAM Scrub Address High Register
951 * [ 7: 0] DRAM Scrubb Address 39-32
954 PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
956 #if ENABLE_IOMMU != 0
957 /* BY LYH add IOMMU 64M APERTURE */
958 PCI_ADDR(0, 0x18, 3, 0x94), 0xffff8000, 0x00000f70,
959 PCI_ADDR(0, 0x18, 3, 0x90), 0xffffff80, 0x00000002,
960 PCI_ADDR(0, 0x18, 3, 0x98), 0x0000000f, 0x00068300,
965 print_debug("setting up CPU");
966 print_debug_hex8(ctrl->node_id);
967 print_debug(" northbridge registers\r\n");
968 max = sizeof(register_values)/sizeof(register_values[0]);
969 for(i = 0; i < max; i += 3) {
974 print_debug_hex32(register_values[i]);
976 print_debug_hex32(register_values[i+2]);
979 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
980 where = register_values[i] & 0xff;
981 reg = pci_read_config32(dev, where);
982 reg &= register_values[i+1];
983 reg |= register_values[i+2];
984 pci_write_config32(dev, where, reg);
987 reg = pci_read_config32(register_values[i]);
988 reg &= register_values[i+1];
989 reg |= register_values[i+2];
990 pci_write_config32(register_values[i], reg);
993 print_debug("done.\r\n");
997 static int is_dual_channel(const struct mem_controller *ctrl)
1000 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1001 return dcl & DCL_128BitEn;
1004 static int is_opteron(const struct mem_controller *ctrl)
1006 /* Test to see if I am an Opteron.
1007 * FIXME Testing dual channel capability is correct for now
1008 * but a beter test is probably required.
1010 #warning "FIXME implement a better test for opterons"
1012 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1013 return !!(nbcap & NBCAP_128Bit);
1016 static int is_registered(const struct mem_controller *ctrl)
1018 /* Test to see if we are dealing with registered SDRAM.
1019 * If we are not registered we are unbuffered.
1020 * This function must be called after spd_handle_unbuffered_dimms.
1023 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1024 return !(dcl & DCL_UnBufDimm);
1028 unsigned long side1;
1029 unsigned long side2;
1032 static struct dimm_size spd_get_dimm_size(unsigned device)
1034 /* Calculate the log base 2 size of a DIMM in bits */
1035 struct dimm_size sz;
1040 /* Note it might be easier to use byte 31 here, it has the DIMM size as
1041 * a multiple of 4MB. The way we do it now we can size both
1042 * sides of an assymetric dimm.
1044 value = spd_read_byte(device, 3); /* rows */
1045 if (value < 0) goto out;
1046 sz.side1 += value & 0xf;
1048 value = spd_read_byte(device, 4); /* columns */
1049 if (value < 0) goto out;
1050 sz.side1 += value & 0xf;
1052 value = spd_read_byte(device, 17); /* banks */
1053 if (value < 0) goto out;
1054 sz.side1 += log2(value & 0xff);
1056 /* Get the module data width and convert it to a power of two */
1057 value = spd_read_byte(device, 7); /* (high byte) */
1058 if (value < 0) goto out;
1062 low = spd_read_byte(device, 6); /* (low byte) */
1063 if (low < 0) goto out;
1064 value = value | (low & 0xff);
1065 sz.side1 += log2(value);
1068 value = spd_read_byte(device, 5); /* number of physical banks */
1069 if (value <= 1) goto out;
1071 /* Start with the symmetrical case */
1072 sz.side2 = sz.side1;
1074 value = spd_read_byte(device, 3); /* rows */
1075 if (value < 0) goto out;
1076 if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */
1077 sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
1078 sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
1080 value = spd_read_byte(device, 4); /* columns */
1081 if (value < 0) goto out;
1082 sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
1083 sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
1089 static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index)
1091 uint32_t base0, base1, map;
1095 print_debug("set_dimm_size: (");
1096 print_debug_hex32(sz.side1);
1097 print_debug_char(',');
1098 print_debug_hex32(sz.side2);
1099 print_debug_char(',');
1100 print_debug_hex32(index);
1101 print_debug(")\r\n");
1103 if (sz.side1 != sz.side2) {
1106 map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
1107 map &= ~(0xf << (index + 4));
1109 /* For each base register.
1110 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
1111 * The initialize dimm size is in bits.
1112 * Set the base enable bit0.
1117 /* Make certain side1 of the dimm is at least 32MB */
1118 if (sz.side1 >= (25 +3)) {
1119 map |= (sz.side1 - (25 + 3)) << (index *4);
1120 base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1;
1122 /* Make certain side2 of the dimm is at least 32MB */
1123 if (sz.side2 >= (25 + 3)) {
1124 base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1;
1127 /* Double the size if we are using dual channel memory */
1128 if (is_dual_channel(ctrl)) {
1129 base0 = (base0 << 1) | (base0 & 1);
1130 base1 = (base1 << 1) | (base1 & 1);
1133 /* Clear the reserved bits */
1134 base0 &= ~0x001ffffe;
1135 base1 &= ~0x001ffffe;
1137 /* Set the appropriate DIMM base address register */
1138 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
1139 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
1140 pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
1142 /* Enable the memory clocks for this DIMM */
1144 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1145 dch |= DCH_MEMCLK_EN0 << index;
1146 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
1150 static void spd_set_ram_size(const struct mem_controller *ctrl)
1154 for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1155 struct dimm_size sz;
1156 sz = spd_get_dimm_size(ctrl->channel0[i]);
1157 set_dimm_size(ctrl, sz, i);
1161 static void route_dram_accesses(const struct mem_controller *ctrl,
1162 unsigned long base_k, unsigned long limit_k)
1164 /* Route the addresses to the controller node */
1169 unsigned limit_reg, base_reg;
1172 node_id = ctrl->node_id;
1173 index = (node_id << 3);
1174 limit = (limit_k << 2);
1175 limit &= 0xffff0000;
1176 limit -= 0x00010000;
1177 limit |= ( 0 << 8) | (node_id << 0);
1178 base = (base_k << 2);
1180 base |= (0 << 8) | (1<<1) | (1<<0);
1182 limit_reg = 0x44 + index;
1183 base_reg = 0x40 + index;
1184 for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
1185 pci_write_config32(device, limit_reg, limit);
1186 pci_write_config32(device, base_reg, base);
1190 static void set_top_mem(unsigned tom_k)
1192 /* Error if I don't have memory */
1195 print_debug("No memory - reset");
1197 pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
1203 /* Report the amount of memory. */
1204 print_debug("RAM: 0x");
1205 print_debug_hex32(tom_k);
1206 print_debug(" KB\r\n");
1209 /* Now set top of memory */
1211 msr.lo = (tom_k & 0x003fffff) << 10;
1212 msr.hi = (tom_k & 0xffc00000) >> 22;
1213 wrmsr(TOP_MEM2, msr);
1215 /* Leave a 64M hole between TOP_MEM and TOP_MEM2
1216 * so I can see my rom chip and other I/O devices.
1218 if (tom_k >= 0x003f0000) {
1221 msr.lo = (tom_k & 0x003fffff) << 10;
1222 msr.hi = (tom_k & 0xffc00000) >> 22;
1223 wrmsr(TOP_MEM, msr);
1226 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
1229 static const uint32_t csbase_low[] = {
1230 /* 32MB */ (1 << (13 - 4)),
1231 /* 64MB */ (1 << (14 - 4)),
1232 /* 128MB */ (1 << (14 - 4)),
1233 /* 256MB */ (1 << (15 - 4)),
1234 /* 512MB */ (1 << (15 - 4)),
1235 /* 1GB */ (1 << (16 - 4)),
1236 /* 2GB */ (1 << (16 - 4)),
1238 uint32_t csbase_inc;
1239 int chip_selects, index;
1242 unsigned common_size;
1243 uint32_t csbase, csmask;
1245 /* See if all of the memory chip selects are the same size
1246 * and if so count them.
1250 for(index = 0; index < 8; index++) {
1254 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1256 /* Is it enabled? */
1262 if (common_size == 0) {
1265 /* The size differed fail */
1266 if (common_size != size) {
1270 /* Chip selects can only be interleaved when there is
1271 * more than one and their is a power of two of them.
1273 bits = log2(chip_selects);
1274 if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
1278 /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
1279 if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
1280 print_debug("8 4GB chip selects cannot be interleaved\r\n");
1283 /* Find the bits of csbase that we need to interleave on */
1284 if (is_dual_channel(ctrl)) {
1285 csbase_inc = csbase_low[log2(common_size) - 1] << 1;
1287 csbase_inc = csbase_low[log2(common_size)];
1289 /* Compute the initial values for csbase and csbask.
1290 * In csbase just set the enable bit and the base to zero.
1291 * In csmask set the mask bits for the size and page level interleave.
1294 csmask = (((common_size << bits) - 1) << 21);
1295 csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc);
1296 for(index = 0; index < 8; index++) {
1299 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1300 /* Is it enabled? */
1304 pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
1305 pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
1306 csbase += csbase_inc;
1310 print_debug("Interleaved\r\n");
1312 /* Return the memory size in K */
1313 return common_size << (15 + bits);
1316 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
1320 /* Remember which registers we have used in the high 8 bits of tom */
1323 /* Find the largest remaining canidate */
1324 unsigned index, canidate;
1325 uint32_t csbase, csmask;
1329 for(index = 0; index < 8; index++) {
1331 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1333 /* Is it enabled? */
1338 /* Is it greater? */
1339 if (value <= csbase) {
1343 /* Has it already been selected */
1344 if (tom & (1 << (index + 24))) {
1347 /* I have a new canidate */
1351 /* See if I have found a new canidate */
1356 /* Remember the dimm size */
1357 size = csbase >> 21;
1359 /* Remember I have used this register */
1360 tom |= (1 << (canidate + 24));
1362 /* Recompute the cs base register value */
1363 csbase = (tom << 21) | 1;
1365 /* Increment the top of memory */
1368 /* Compute the memory mask */
1369 csmask = ((size -1) << 21);
1370 csmask |= 0xfe00; /* For now don't optimize */
1371 #warning "Don't forget to optimize the DIMM size"
1373 /* Write the new base register */
1374 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
1375 /* Write the new mask register */
1376 pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
1379 /* Return the memory size in K */
1380 return (tom & ~0xff000000) << 15;
1383 static void order_dimms(const struct mem_controller *ctrl)
1385 unsigned long tom, tom_k, base_k;
1388 tom_k = interleave_chip_selects(ctrl);
1390 tom_k = order_chip_selects(ctrl);
1392 /* Compute the memory base address */
1394 for(node_id = 0; node_id < ctrl->node_id; node_id++) {
1395 uint32_t limit, base;
1397 index = node_id << 3;
1398 base = pci_read_config32(ctrl->f1, 0x40 + index);
1399 /* Only look at the limit if the base is enabled */
1400 if ((base & 3) == 3) {
1401 limit = pci_read_config32(ctrl->f1, 0x44 + index);
1402 base_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
1407 print_debug("base_k: ");
1408 print_debug_hex32(base_k);
1409 print_debug(" tom_k: ");
1410 print_debug_hex32(tom_k);
1411 print_debug("\r\n");
1413 route_dram_accesses(ctrl, base_k, tom_k);
1417 static void disable_dimm(const struct mem_controller *ctrl, unsigned index)
1419 print_debug("disabling dimm");
1420 print_debug_hex8(index);
1421 print_debug("\r\n");
1422 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
1423 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
1427 static void spd_handle_unbuffered_dimms(const struct mem_controller *ctrl)
1435 for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1437 value = spd_read_byte(ctrl->channel0[i], 21);
1439 disable_dimm(ctrl, i);
1442 /* Registered dimm ? */
1443 if (value & (1 << 1)) {
1446 /* Otherwise it must be an unbuffered dimm */
1451 if (unbuffered && registered) {
1452 die("Mixed buffered and registered dimms not supported");
1454 if (unbuffered && is_opteron(ctrl)) {
1455 die("Unbuffered Dimms not supported on Opteron");
1458 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1459 dcl &= ~DCL_UnBufDimm;
1461 dcl |= DCL_UnBufDimm;
1463 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1465 if (is_registered(ctrl)) {
1466 print_debug("Registered\r\n");
1468 print_debug("Unbuffered\r\n");
1473 static void spd_enable_2channels(const struct mem_controller *ctrl)
1477 /* SPD addresses to verify are identical */
1478 #warning "FINISHME review and see if these are the bytes I need"
1479 /* FINISHME review and see if these are the bytes I need */
1480 static const unsigned addresses[] = {
1481 2, /* Type should be DDR SDRAM */
1482 3, /* *Row addresses */
1483 4, /* *Column addresses */
1484 5, /* *Physical Banks */
1485 6, /* *Module Data Width low */
1486 7, /* *Module Data Width high */
1487 9, /* *Cycle time at highest CAS Latency CL=X */
1488 11, /* *SDRAM Type */
1489 13, /* *SDRAM Width */
1490 17, /* *Logical Banks */
1491 18, /* *Supported CAS Latencies */
1492 21, /* *SDRAM Module Attributes */
1493 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */
1494 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */
1495 27, /* *tRP Row precharge time */
1496 28, /* *Minimum Row Active to Row Active Delay (tRRD) */
1497 29, /* *tRCD RAS to CAS */
1498 30, /* *tRAS Activate to Precharge */
1499 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */
1500 42, /* *Minimum Auto Refresh Command Time(Trfc) */
1502 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1503 if (!(nbcap & NBCAP_128Bit)) {
1506 for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1507 unsigned device0, device1;
1510 device0 = ctrl->channel0[i];
1511 device1 = ctrl->channel1[i];
1514 for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
1516 addr = addresses[j];
1517 value0 = spd_read_byte(device0, addr);
1521 value1 = spd_read_byte(device1, addr);
1525 if (value0 != value1) {
1530 print_debug("Enabling dual channel memory\r\n");
1532 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1533 dcl &= ~DCL_32ByteEn;
1534 dcl |= DCL_128BitEn;
1535 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1540 uint8_t divisor; /* In 1/2 ns increments */
1543 uint32_t dch_memclk;
1544 uint16_t dch_tref4k, dch_tref8k;
1549 static const struct mem_param *get_mem_param(unsigned min_cycle_time)
1551 static const struct mem_param speed[] = {
1553 .name = "100Mhz\r\n",
1555 .divisor = (10 <<1),
1558 .dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT,
1559 .dch_tref4k = DTH_TREF_100MHZ_4K,
1560 .dch_tref8k = DTH_TREF_100MHZ_8K,
1564 .name = "133Mhz\r\n",
1566 .divisor = (7<<1)+1,
1569 .dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,
1570 .dch_tref4k = DTH_TREF_133MHZ_4K,
1571 .dch_tref8k = DTH_TREF_133MHZ_8K,
1575 .name = "166Mhz\r\n",
1580 .dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,
1581 .dch_tref4k = DTH_TREF_166MHZ_4K,
1582 .dch_tref8k = DTH_TREF_166MHZ_8K,
1586 .name = "200Mhz\r\n",
1591 .dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,
1592 .dch_tref4k = DTH_TREF_200MHZ_4K,
1593 .dch_tref8k = DTH_TREF_200MHZ_8K,
1600 const struct mem_param *param;
1601 for(param = &speed[0]; param->cycle_time ; param++) {
1602 if (min_cycle_time > (param+1)->cycle_time) {
1606 if (!param->cycle_time) {
1607 die("min_cycle_time to low");
1610 print_debug(param->name);
1615 static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl)
1617 /* Compute the minimum cycle time for these dimms */
1618 const struct mem_param *param;
1619 unsigned min_cycle_time, min_latency;
1623 static const int latency_indicies[] = { 26, 23, 9 };
1624 static const unsigned char min_cycle_times[] = {
1625 [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
1626 [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
1627 [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
1628 [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
1632 value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1633 min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
1637 print_debug("min_cycle_time: ");
1638 print_debug_hex8(min_cycle_time);
1639 print_debug(" min_latency: ");
1640 print_debug_hex8(min_latency);
1641 print_debug("\r\n");
1644 /* Compute the least latency with the fastest clock supported
1645 * by both the memory controller and the dimms.
1647 for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1648 int new_cycle_time, new_latency;
1653 /* First find the supported CAS latencies
1654 * Byte 18 for DDR SDRAM is interpreted:
1655 * bit 0 == CAS Latency = 1.0
1656 * bit 1 == CAS Latency = 1.5
1657 * bit 2 == CAS Latency = 2.0
1658 * bit 3 == CAS Latency = 2.5
1659 * bit 4 == CAS Latency = 3.0
1660 * bit 5 == CAS Latency = 3.5
1664 new_cycle_time = 0xa0;
1667 latencies = spd_read_byte(ctrl->channel0[i], 18);
1668 if (latencies <= 0) continue;
1670 /* Compute the lowest cas latency supported */
1671 latency = log2(latencies) -2;
1673 /* Loop through and find a fast clock with a low latency */
1674 for(index = 0; index < 3; index++, latency++) {
1676 if ((latency < 2) || (latency > 4) ||
1677 (!(latencies & (1 << latency)))) {
1680 value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
1685 /* Only increase the latency if we decreas the clock */
1686 if ((value >= min_cycle_time) && (value < new_cycle_time)) {
1687 new_cycle_time = value;
1688 new_latency = latency;
1691 if (new_latency > 4){
1694 /* Does min_latency need to be increased? */
1695 if (new_cycle_time > min_cycle_time) {
1696 min_cycle_time = new_cycle_time;
1698 /* Does min_cycle_time need to be increased? */
1699 if (new_latency > min_latency) {
1700 min_latency = new_latency;
1704 print_debug_hex8(i);
1705 print_debug(" min_cycle_time: ");
1706 print_debug_hex8(min_cycle_time);
1707 print_debug(" min_latency: ");
1708 print_debug_hex8(min_latency);
1709 print_debug("\r\n");
1712 /* Make a second pass through the dimms and disable
1713 * any that cannot support the selected memclk and cas latency.
1716 for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1722 latencies = spd_read_byte(ctrl->channel0[i], 18);
1723 if (latencies <= 0) {
1727 /* Compute the lowest cas latency supported */
1728 latency = log2(latencies) -2;
1730 /* Walk through searching for the selected latency */
1731 for(index = 0; index < 3; index++, latency++) {
1732 if (!(latencies & (1 << latency))) {
1735 if (latency == min_latency)
1738 /* If I can't find the latency or my index is bad error */
1739 if ((latency != min_latency) || (index >= 3)) {
1743 /* Read the min_cycle_time for this latency */
1744 value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
1746 /* All is good if the selected clock speed
1747 * is what I need or slower.
1749 if (value <= min_cycle_time) {
1752 /* Otherwise I have an error, disable the dimm */
1754 disable_dimm(ctrl, i);
1757 print_debug("min_cycle_time: ");
1758 print_debug_hex8(min_cycle_time);
1759 print_debug(" min_latency: ");
1760 print_debug_hex8(min_latency);
1761 print_debug("\r\n");
1763 /* Now that I know the minimum cycle time lookup the memory parameters */
1764 param = get_mem_param(min_cycle_time);
1766 /* Update DRAM Config High with our selected memory speed */
1767 value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1768 value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
1769 value |= param->dch_memclk;
1770 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
1772 static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
1773 /* Update DRAM Timing Low with our selected cas latency */
1774 value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1775 value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
1776 value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
1777 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
1783 static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1785 unsigned clocks, old_clocks;
1788 value = spd_read_byte(ctrl->channel0[i], 41);
1789 if (value < 0) return -1;
1790 if ((value == 0) || (value == 0xff)) {
1793 clocks = ((value << 1) + param->divisor - 1)/param->divisor;
1794 if (clocks < DTL_TRC_MIN) {
1795 clocks = DTL_TRC_MIN;
1797 if (clocks > DTL_TRC_MAX) {
1801 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1802 old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
1803 if (old_clocks > clocks) {
1804 clocks = old_clocks;
1806 dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
1807 dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
1808 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1812 static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1814 unsigned clocks, old_clocks;
1817 value = spd_read_byte(ctrl->channel0[i], 42);
1818 if (value < 0) return -1;
1819 if ((value == 0) || (value == 0xff)) {
1820 value = param->tRFC;
1822 clocks = ((value << 1) + param->divisor - 1)/param->divisor;
1823 if (clocks < DTL_TRFC_MIN) {
1824 clocks = DTL_TRFC_MIN;
1826 if (clocks > DTL_TRFC_MAX) {
1829 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1830 old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
1831 if (old_clocks > clocks) {
1832 clocks = old_clocks;
1834 dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
1835 dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
1836 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1841 static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1843 unsigned clocks, old_clocks;
1846 value = spd_read_byte(ctrl->channel0[i], 29);
1847 if (value < 0) return -1;
1849 clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
1851 clocks = (value + ((param->divisor & 0xff) << 1) -1)/((param->divisor & 0xff) << 1);
1853 if (clocks < DTL_TRCD_MIN) {
1854 clocks = DTL_TRCD_MIN;
1856 if (clocks > DTL_TRCD_MAX) {
1859 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1860 old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
1861 if (old_clocks > clocks) {
1862 clocks = old_clocks;
1864 dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
1865 dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
1866 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1870 static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1872 unsigned clocks, old_clocks;
1875 value = spd_read_byte(ctrl->channel0[i], 28);
1876 if (value < 0) return -1;
1877 clocks = (value + ((param->divisor & 0xff) << 1) -1)/((param->divisor & 0xff) << 1);
1878 if (clocks < DTL_TRRD_MIN) {
1879 clocks = DTL_TRRD_MIN;
1881 if (clocks > DTL_TRRD_MAX) {
1884 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1885 old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
1886 if (old_clocks > clocks) {
1887 clocks = old_clocks;
1889 dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
1890 dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
1891 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1895 static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1897 unsigned clocks, old_clocks;
1900 value = spd_read_byte(ctrl->channel0[i], 30);
1901 if (value < 0) return -1;
1902 clocks = ((value << 1) + param->divisor - 1)/param->divisor;
1903 if (clocks < DTL_TRAS_MIN) {
1904 clocks = DTL_TRAS_MIN;
1906 if (clocks > DTL_TRAS_MAX) {
1909 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1910 old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
1911 if (old_clocks > clocks) {
1912 clocks = old_clocks;
1914 dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
1915 dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
1916 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1920 static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1922 unsigned clocks, old_clocks;
1925 value = spd_read_byte(ctrl->channel0[i], 27);
1926 if (value < 0) return -1;
1928 clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1);
1930 clocks = (value + ((param->divisor & 0xff) << 1) - 1)/((param->divisor & 0xff) << 1);
1933 print_debug("Trp: ");
1934 print_debug_hex8(clocks);
1935 print_debug(" spd value: ");
1936 print_debug_hex8(value);
1937 print_debug(" divisor: ");
1938 print_debug_hex8(param->divisor);
1939 print_debug("\r\n");
1941 if (clocks < DTL_TRP_MIN) {
1942 clocks = DTL_TRP_MIN;
1944 if (clocks > DTL_TRP_MAX) {
1947 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1948 old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
1949 if (old_clocks > clocks) {
1950 clocks = old_clocks;
1952 dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
1953 dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
1954 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1958 static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
1961 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1962 dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
1963 dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
1964 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1968 static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
1971 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
1972 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
1973 dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
1974 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
1977 static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1981 unsigned tref, old_tref;
1982 value = spd_read_byte(ctrl->channel0[i], 3);
1983 if (value < 0) return -1;
1986 tref = param->dch_tref8k;
1988 tref = param->dch_tref4k;
1991 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
1992 old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
1993 if ((value == 12) && (old_tref == param->dch_tref4k)) {
1994 tref = param->dch_tref4k;
1996 tref = param->dch_tref8k;
1998 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
1999 dth |= (tref << DTH_TREF_SHIFT);
2000 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2005 static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, int i)
2010 value = spd_read_byte(ctrl->channel0[i], 13);
2015 dimm += DCL_x4DIMM_SHIFT;
2016 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2017 dcl &= ~(1 << dimm);
2021 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2025 static int update_dimm_ecc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
2029 value = spd_read_byte(ctrl->channel0[i], 11);
2034 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2035 dcl &= ~DCL_DimmEccEn;
2036 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2041 static int count_dimms(const struct mem_controller *ctrl)
2046 for(index = 0; index < 8; index += 2) {
2048 csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + index << 2));
2056 static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param)
2060 clocks = 1; /* AMD says hard code this */
2061 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2062 dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
2063 dth |= ((clocks - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
2064 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2067 static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
2075 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
2076 latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
2077 divisor = param->divisor;
2079 if (is_opteron(ctrl)) {
2080 if (latency == DTL_CL_2) {
2081 if (divisor == ((6 << 0) + 0)) {
2085 else if (divisor > ((6 << 0)+0)) {
2086 /* 100Mhz && 133Mhz */
2090 else if (latency == DTL_CL_2_5) {
2093 else if (latency == DTL_CL_3) {
2094 if (divisor == ((6 << 0)+0)) {
2098 else if (divisor > ((6 << 0)+0)) {
2099 /* 100Mhz && 133Mhz */
2104 else /* Athlon64 */ {
2105 if (is_registered(ctrl)) {
2106 if (latency == DTL_CL_2) {
2109 else if (latency == DTL_CL_2_5) {
2112 else if (latency == DTL_CL_3) {
2116 else /* Unbuffered */{
2117 if (latency == DTL_CL_2) {
2120 else if (latency == DTL_CL_2_5) {
2123 else if (latency == DTL_CL_3) {
2128 if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
2129 die("Unknown Trwt");
2132 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2133 dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
2134 dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
2135 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2139 static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param)
2141 /* Memory Clocks after CAS# */
2144 if (is_registered(ctrl)) {
2149 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2150 dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
2151 dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
2152 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2156 static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param)
2160 unsigned rdpreamble;
2161 divisor = param->divisor;
2162 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2163 dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
2165 if (is_registered(ctrl)) {
2166 if (divisor == ((10 << 1)+0)) {
2168 rdpreamble = ((9 << 1)+ 0);
2170 else if (divisor == ((7 << 1)+1)) {
2172 rdpreamble = ((8 << 1)+0);
2174 else if (divisor == ((6 << 1)+0)) {
2176 rdpreamble = ((7 << 1)+1);
2178 else if (divisor == ((5 << 1)+0)) {
2180 rdpreamble = ((7 << 1)+0);
2187 for(i = 0; i < 4; i++) {
2188 if (ctrl->channel0[i]) {
2192 if (divisor == ((10 << 1)+0)) {
2196 rdpreamble = ((9 << 1)+0);
2199 rdpreamble = ((14 << 1)+0);
2202 else if (divisor == ((7 << 1)+1)) {
2206 rdpreamble = ((7 << 1)+0);
2209 rdpreamble = ((11 << 1)+0);
2212 else if (divisor == ((6 << 1)+0)) {
2216 rdpreamble = ((7 << 1)+0);
2219 rdpreamble = ((9 << 1)+0);
2222 else if (divisor == ((5 << 1)+0)) {
2226 rdpreamble = ((5 << 1)+0);
2229 rdpreamble = ((7 << 1)+0);
2233 if ((rdpreamble < DCH_RDPREAMBLE_MIN) || (rdpreamble > DCH_RDPREAMBLE_MAX)) {
2234 die("Unknown rdpreamble");
2236 dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
2237 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2240 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
2247 dimms = count_dimms(ctrl);
2249 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2250 dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
2252 if (is_registered(ctrl)) {
2264 die("Too many unbuffered dimms");
2266 else if (dimms == 3) {
2275 dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
2276 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2279 static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
2282 /* AMD says to Hardcode this */
2283 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2284 dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
2285 dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
2286 dch |= DCH_DYN_IDLE_CTR_EN;
2287 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2290 static void spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param)
2296 init_Tref(ctrl, param);
2297 for(i = 0; (i < 4) && ctrl->channel0[i]; i++) {
2299 /* DRAM Timing Low Register */
2300 if (update_dimm_Trc (ctrl, param, i) < 0) goto dimm_err;
2301 if (update_dimm_Trfc(ctrl, param, i) < 0) goto dimm_err;
2302 if (update_dimm_Trcd(ctrl, param, i) < 0) goto dimm_err;
2303 if (update_dimm_Trrd(ctrl, param, i) < 0) goto dimm_err;
2304 if (update_dimm_Tras(ctrl, param, i) < 0) goto dimm_err;
2305 if (update_dimm_Trp (ctrl, param, i) < 0) goto dimm_err;
2307 /* DRAM Timing High Register */
2308 if (update_dimm_Tref(ctrl, param, i) < 0) goto dimm_err;
2310 /* DRAM Config Low */
2311 if (update_dimm_x4 (ctrl, param, i) < 0) goto dimm_err;
2312 if (update_dimm_ecc(ctrl, param, i) < 0) goto dimm_err;
2315 disable_dimm(ctrl, i);
2318 /* DRAM Timing Low Register */
2319 set_Twr(ctrl, param);
2321 /* DRAM Timing High Register */
2322 set_Twtr(ctrl, param);
2323 set_Trwt(ctrl, param);
2324 set_Twcl(ctrl, param);
2326 /* DRAM Config High */
2327 set_read_preamble(ctrl, param);
2328 set_max_async_latency(ctrl, param);
2329 set_idle_cycle_limit(ctrl, param);
2332 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
2334 const struct mem_param *param;
2335 activate_spd_rom(ctrl);
2336 spd_enable_2channels(ctrl);
2337 spd_set_ram_size(ctrl);
2338 spd_handle_unbuffered_dimms(ctrl);
2339 param = spd_set_memclk(ctrl);
2340 spd_set_dram_timing(ctrl, param);
2344 #define TIMEOUT_LOOPS 300000
2345 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
2349 /* Before enabling memory start the memory clocks */
2350 for(i = 0; i < controllers; i++) {
2352 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
2353 dch |= DCH_MEMCLK_VALID;
2354 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
2357 /* And if necessary toggle the the reset on the dimms by hand */
2358 memreset(controllers, ctrl);
2360 for(i = 0; i < controllers; i++) {
2362 /* Toggle DisDqsHys to get it working */
2363 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
2365 print_debug("dcl: ");
2366 print_debug_hex32(dcl);
2367 print_debug("\r\n");
2369 if (dcl & DCL_DimmEccEn) {
2371 print_debug("ECC enabled\r\n");
2372 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
2374 if (dcl & DCL_128BitEn) {
2375 mnc |= MNC_CHIPKILL_EN;
2377 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
2379 dcl |= DCL_DisDqsHys;
2380 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
2381 dcl &= ~DCL_DisDqsHys;
2382 dcl &= ~DCL_DLL_Disable;
2385 dcl |= DCL_DramInit;
2386 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
2389 for(i = 0; i < controllers; i++) {
2391 print_debug("Initializing memory: ");
2394 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
2396 if ((loops & 1023) == 0) {
2399 } while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
2400 if (loops >= TIMEOUT_LOOPS) {
2401 print_debug(" failed\r\n");
2403 print_debug(" done\r\n");
2405 if (dcl & DCL_DimmEccEn) {
2406 print_debug("Clearing memory: ");
2407 if (!is_cpu_pre_c0()) {
2408 /* Wait until the automatic ram scrubber is finished */
2409 dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
2410 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
2412 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
2413 } while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
2415 uint32_t base, last_scrub_k, scrub_k;
2416 uint32_t cnt,zstart,zend;
2419 /* First make certain the scrubber is disabled */
2420 pci_write_config32(ctrl[i].f3, SCRUB_CONTROL,
2421 (SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
2423 /* load the start and end for the memory block to clear */
2424 msr_201 = rdmsr(0x201);
2425 zstart = pci_read_config32(ctrl[0].f1, 0x40 + (i*8));
2426 zend = pci_read_config32(ctrl[0].f1, 0x44 + (i*8));
2430 print_debug("addr ");
2431 print_debug_hex32(zstart);
2433 print_debug_hex32(zend);
2434 print_debug("\r\n");
2437 /* Disable fixed mtrrs */
2438 msr = rdmsr(MTRRdefType_MSR);
2440 wrmsr(MTRRdefType_MSR, msr);
2442 /* turn on the wrap 32 disable */
2443 msr = rdmsr(0xc0010015);
2445 wrmsr(0xc0010015,msr);
2447 for(;zstart<zend;zstart+=4) {
2449 /* test for the last 64 meg of 4 gig space */
2455 "movl %%cr0, %0\n\t"
2456 "orl $0x40000000, %0\n\t"
2457 "movl %0, %%cr0\n\t"
2461 /* Set the variable mtrrs to write combine */
2462 msr.lo = 1 + ((zstart&0x0ff)<<24);
2463 msr.hi = (zstart&0x0ff00)>>8;
2466 /* Set the limit to 64 meg of ram */
2467 msr.hi = 0x000000ff;
2468 msr.lo = 0xfc000800;
2473 "movl %%cr0, %0\n\t"
2474 "andl $0x9fffffff, %0\n\t"
2475 "movl %0, %%cr0\n\t"
2478 /* Set fs base address */
2479 msr.lo = (zstart&0xff) << 24;
2480 msr.hi = (zstart&0xff00) >> 8;
2481 wrmsr(0xc0000100,msr);
2483 print_debug_char((zstart > 0x0ff)?'+':'-');
2485 /* clear memory 64meg */
2488 "movl %0, %%fs:(%1)\n\t"
2493 : "a" (0), "D" (0), "c" (0x01000000)
2499 "movl %%cr0, %0\n\t"
2500 "orl $0x40000000, %0\n\t"
2501 "movl %0, %%cr0\n\t"
2505 /* restore msr registers */
2506 msr = rdmsr(MTRRdefType_MSR);
2508 wrmsr(MTRRdefType_MSR, msr);
2510 /* Restore the variable mtrrs */
2514 wrmsr(0x201,msr_201);
2516 /* Set fs base to 0 */
2519 wrmsr(0xc0000100,msr);
2523 "movl %%cr0, %0\n\t"
2524 "andl $0x9fffffff, %0\n\t"
2525 "movl %0, %%cr0\n\t"
2529 /* turn off the wrap 32 disable */
2530 msr = rdmsr(0xc0010015);
2532 wrmsr(0xc0010015,msr);
2534 /* Find the Srub base address for this cpu */
2535 base = pci_read_config32(ctrl[i].f1, 0x40 + (ctrl[i].node_id << 3));
2538 /* Set the scrub base address registers */
2539 pci_write_config32(ctrl[i].f3, SCRUB_ADDR_LOW, base << 8);
2540 pci_write_config32(ctrl[i].f3, SCRUB_ADDR_HIGH, base >> 24);
2542 /* Enable scrubbing at the lowest possible rate */
2543 pci_write_config32(ctrl[i].f3, SCRUB_CONTROL,
2544 (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
2546 print_debug("done\r\n");