1 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <device/pci_ids.h>
8 #include <device/hypertransport.h>
14 #include "northbridge.h"
17 #define DEVICE_MEM_HIGH 0xFEC00000ULL /* Reserve 20M for the system */
18 #define DEVICE_IO_START 0x1000
21 static device_t __f0_dev[FX_DEVS];
22 static device_t __f1_dev[FX_DEVS];
25 static void debug_fx_devs(void)
28 for(i = 0; i < FX_DEVS; i++) {
32 printk_debug("__f0_dev[%d]: %s bus: %p\n",
33 i, dev_path(dev), dev->bus);
37 printk_debug("__f1_dev[%d]: %s bus: %p\n",
38 i, dev_path(dev), dev->bus);
44 static void get_fx_devs(void)
50 for(i = 0; i < FX_DEVS; i++) {
51 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
52 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
55 die("Cannot find 0:0x18.1\n");
59 static uint32_t f1_read_config32(unsigned reg)
62 return pci_read_config32(__f1_dev[0], reg);
65 static void f1_write_config32(unsigned reg, uint32_t value)
69 for(i = 0; i < FX_DEVS; i++) {
72 if (dev && dev->enabled) {
73 pci_write_config32(dev, reg, value);
78 static unsigned int amdk8_nodeid(device_t dev)
80 return (dev->path.u.pci.devfn >> 3) - 0x18;
83 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
87 nodeid = amdk8_nodeid(dev);
89 printk_debug("%s amdk8_scan_chains max: %d starting...\n",
92 for(link = 0; link < dev->links; link++) {
94 uint32_t busses, config_busses;
95 unsigned free_reg, config_reg;
96 dev->link[link].cap = 0x80 + (link *0x20);
98 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
99 } while(link_type & ConnectionPending);
100 if (!(link_type & LinkConnected)) {
104 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
105 } while(!(link_type & InitComplete));
106 if (!(link_type & NonCoherent)) {
109 /* See if there is an available configuration space mapping register in function 1. */
111 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
113 config = f1_read_config32(config_reg);
114 if (!free_reg && ((config & 3) == 0)) {
115 free_reg = config_reg;
118 if (((config & 3) == 3) &&
119 (((config >> 4) & 7) == nodeid) &&
120 (((config >> 8) & 3) == link)) {
124 if (free_reg && (config_reg > 0xec)) {
125 config_reg = free_reg;
127 /* If we can't find an available configuration space mapping register skip this bus */
128 if (config_reg > 0xec) {
132 /* Set up the primary, secondary and subordinate bus numbers. We have
133 * no idea how many busses are behind this bridge yet, so we set the subordinate
134 * bus number to 0xff for the moment.
136 dev->link[link].secondary = ++max;
137 dev->link[link].subordinate = 0xff;
139 /* Read the existing primary/secondary/subordinate bus
140 * number configuration.
142 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
143 config_busses = f1_read_config32(config_reg);
145 /* Configure the bus numbers for this bridge: the configuration
146 * transactions will not be propagates by the bridge if it is not
147 * correctly configured
149 busses &= 0xff000000;
150 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
151 ((unsigned int)(dev->link[link].secondary) << 8) |
152 ((unsigned int)(dev->link[link].subordinate) << 16));
153 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
155 config_busses &= 0x000fc88;
157 (3 << 0) | /* rw enable, no device compare */
158 (( nodeid & 7) << 4) |
159 (( link & 3 ) << 8) |
160 ((dev->link[link].secondary) << 16) |
161 ((dev->link[link].subordinate) << 24);
162 f1_write_config32(config_reg, config_busses);
165 printk_debug("%s Hyper transport scan link: %d max: %d\n",
166 dev_path(dev), link, max);
168 /* Now we can scan all of the subordinate busses i.e. the chain on the hypertranport link */
169 max = hypertransport_scan_chain(&dev->link[link], max);
172 printk_debug("%s Hyper transport scan link: %d new max: %d\n",
173 dev_path(dev), link, max);
176 /* We know the number of busses behind this bridge. Set the subordinate
177 * bus number to it's real value
179 dev->link[link].subordinate = max;
180 busses = (busses & 0xff00ffff) |
181 ((unsigned int) (dev->link[link].subordinate) << 16);
182 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
184 config_busses = (config_busses & 0x00ffffff) | (dev->link[link].subordinate << 24);
185 f1_write_config32(config_reg, config_busses);
187 printk_debug("%s Hypertransport scan link: %d done\n",
188 dev_path(dev), link);
192 printk_debug("%s amdk8_scan_chains max: %d done\n",
198 static int reg_useable(unsigned reg,
199 device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
201 struct resource *res;
202 unsigned nodeid, link;
205 for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
207 dev = __f0_dev[nodeid];
208 for(link = 0; !res && (link < 3); link++) {
209 res = probe_resource(dev, 0x100 + (reg | link));
215 if ( (goal_link == (link - 1)) &&
216 (goal_nodeid == (nodeid - 1)) &&
222 printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
224 goal_nodeid, goal_link,
231 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
233 struct resource *resource;
234 unsigned free_reg, reg;
237 for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
239 result = reg_useable(reg, dev, nodeid, link);
241 /* I have been allocated this one */
244 else if (result > 1) {
245 /* I have a free register pair */
253 resource = new_resource(dev, 0x100 + (reg | link));
258 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
260 struct resource *resource;
261 unsigned free_reg, reg;
264 for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
266 result = reg_useable(reg, dev, nodeid, link);
268 /* I have been allocated this one */
271 else if (result > 1) {
272 /* I have a free register pair */
280 resource = new_resource(dev, 0x100 + (reg | link));
284 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
286 struct resource *resource;
288 /* Initialize the io space constraints on the current bus */
289 resource = amdk8_find_iopair(dev, nodeid, link);
293 resource->align = log2(HT_IO_HOST_ALIGN);
294 resource->gran = log2(HT_IO_HOST_ALIGN);
295 resource->limit = 0xffffUL;
296 resource->flags = IORESOURCE_IO;
297 compute_allocate_resource(&dev->link[link], resource,
298 IORESOURCE_IO, IORESOURCE_IO);
301 /* Initialize the prefetchable memory constraints on the current bus */
302 resource = amdk8_find_mempair(dev, nodeid, link);
306 resource->align = log2(HT_MEM_HOST_ALIGN);
307 resource->gran = log2(HT_MEM_HOST_ALIGN);
308 resource->limit = 0xffffffffffULL;
309 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
310 compute_allocate_resource(&dev->link[link], resource,
311 IORESOURCE_MEM | IORESOURCE_PREFETCH,
312 IORESOURCE_MEM | IORESOURCE_PREFETCH);
315 /* Initialize the memory constraints on the current bus */
316 resource = amdk8_find_mempair(dev, nodeid, link);
320 resource->align = log2(HT_MEM_HOST_ALIGN);
321 resource->gran = log2(HT_MEM_HOST_ALIGN);
322 resource->limit = 0xffffffffffULL;
323 resource->flags = IORESOURCE_MEM;
324 compute_allocate_resource(&dev->link[link], resource,
325 IORESOURCE_MEM | IORESOURCE_PREFETCH,
330 static void amdk8_read_resources(device_t dev)
332 unsigned nodeid, link;
333 nodeid = amdk8_nodeid(dev);
334 for(link = 0; link < dev->links; link++) {
335 if (dev->link[link].children) {
336 amdk8_link_read_bases(dev, nodeid, link);
341 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
343 resource_t rbase, rend;
347 /* Make certain the resource has actually been set */
348 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
352 /* If I have already stored this resource don't worry about it */
353 if (resource->flags & IORESOURCE_STORED) {
357 /* Only handle PCI memory and IO resources */
358 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
361 /* Ensure I am actually looking at a resource of function 1 */
362 if (resource->index < 0x100) {
365 /* Get the base address */
366 rbase = resource->base;
368 /* Get the limit (rounded up) */
369 rend = resource_end(resource);
371 /* Get the register and link */
372 reg = resource->index & 0xfc;
373 link = resource->index & 3;
375 if (resource->flags & IORESOURCE_IO) {
376 uint32_t base, limit;
377 compute_allocate_resource(&dev->link[link], resource,
378 IORESOURCE_IO, IORESOURCE_IO);
379 base = f1_read_config32(reg);
380 limit = f1_read_config32(reg + 0x4);
382 base |= rbase & 0x01fff000;
385 limit |= rend & 0x01fff000;
386 limit |= (link & 3) << 4;
387 limit |= (nodeid & 7);
389 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
390 base |= PCI_IO_BASE_VGA_EN;
392 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
393 base |= PCI_IO_BASE_NO_ISA;
396 f1_write_config32(reg + 0x4, limit);
397 f1_write_config32(reg, base);
399 else if (resource->flags & IORESOURCE_MEM) {
400 uint32_t base, limit;
401 compute_allocate_resource(&dev->link[link], resource,
402 IORESOURCE_MEM | IORESOURCE_PREFETCH,
403 resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
404 base = f1_read_config32(reg);
405 limit = f1_read_config32(reg + 0x4);
407 base |= (rbase >> 8) & 0xffffff00;
410 limit |= (rend >> 8) & 0xffffff00;
411 limit |= (link & 3) << 4;
412 limit |= (nodeid & 7);
413 f1_write_config32(reg + 0x4, limit);
414 f1_write_config32(reg, base);
416 resource->flags |= IORESOURCE_STORED;
417 sprintf(buf, " <node %d link %d>",
419 report_resource_stored(dev, resource, buf);
422 static void amdk8_set_resources(device_t dev)
424 unsigned nodeid, link;
427 /* Find the nodeid */
428 nodeid = amdk8_nodeid(dev);
430 /* Set each resource we have found */
431 for(i = 0; i < dev->resources; i++) {
432 amdk8_set_resource(dev, &dev->resource[i], nodeid);
435 for(link = 0; link < dev->links; link++) {
437 bus = &dev->link[link];
439 assign_resources(bus);
445 static void mcf0_control_init(struct device *dev)
450 printk_debug("NB: Function 0 Misc Control.. ");
453 /* improve latency and bandwith on HT */
454 cmd = pci_read_config32(dev, 0x68);
457 pci_write_config32(dev, 0x68, cmd );
461 /* over drive the ht port to 1000 Mhz */
462 cmd = pci_read_config32(dev, 0xa8);
465 pci_write_config32(dev, 0xdc, cmd );
467 printk_debug("done.\n");
470 static struct device_operations northbridge_operations = {
471 .read_resources = amdk8_read_resources,
472 .set_resources = amdk8_set_resources,
473 .enable_resources = pci_dev_enable_resources,
474 .init = mcf0_control_init,
475 .scan_bus = amdk8_scan_chains,
481 static struct pci_driver mcf0_driver __pci_driver = {
482 .ops = &northbridge_operations,
483 .vendor = PCI_VENDOR_ID_AMD,
488 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
490 static void pci_domain_read_resources(device_t dev)
492 struct resource *resource;
495 /* Find the already assigned resource pairs */
497 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
498 uint32_t base, limit;
499 base = f1_read_config32(reg);
500 limit = f1_read_config32(reg + 0x04);
501 /* Is this register allocated? */
502 if ((base & 3) != 0) {
503 unsigned nodeid, link;
506 link = (limit >> 4) & 3;
507 dev = __f0_dev[nodeid];
509 /* Reserve the resource */
510 struct resource *resource;
511 resource = new_resource(dev, 0x100 + (reg | link));
519 /* Initialize the system wide io space constraints */
520 resource = new_resource(dev, 0);
521 resource->base = 0x400;
522 resource->limit = 0xffffUL;
523 resource->flags = IORESOURCE_IO;
524 compute_allocate_resource(&dev->link[0], resource,
525 IORESOURCE_IO, IORESOURCE_IO);
527 /* Initialize the system wide prefetchable memory resources constraints */
528 resource = new_resource(dev, 1);
529 resource->limit = 0xfcffffffffULL;
530 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
531 compute_allocate_resource(&dev->link[0], resource,
532 IORESOURCE_MEM | IORESOURCE_PREFETCH,
533 IORESOURCE_MEM | IORESOURCE_PREFETCH);
535 /* Initialize the system wide memory resources constraints */
536 resource = new_resource(dev, 2);
537 resource->limit = 0xfcffffffffULL;
538 resource->flags = IORESOURCE_MEM;
539 compute_allocate_resource(&dev->link[0], resource,
540 IORESOURCE_MEM | IORESOURCE_PREFETCH,
544 static void ram_resource(device_t dev, unsigned long index,
545 unsigned long basek, unsigned long sizek)
547 struct resource *resource;
552 resource = new_resource(dev, index);
553 resource->base = ((resource_t)basek) << 10;
554 resource->size = ((resource_t)sizek) << 10;
555 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
556 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
559 static void pci_domain_set_resources(device_t dev)
561 struct resource *io, *mem1, *mem2;
562 struct resource *resource, *last;
563 unsigned long mmio_basek;
568 /* Place the IO devices somewhere safe */
569 io = find_resource(dev, 0);
570 io->base = DEVICE_IO_START;
573 /* Now reallocate the pci resources memory with the
574 * highest addresses I can manage.
576 mem1 = find_resource(dev, 1);
577 mem2 = find_resource(dev, 2);
578 /* See if both resources have roughly the same limits */
579 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
580 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
582 /* If so place the one with the most stringent alignment first
584 if (mem2->align > mem1->align) {
585 struct resource *tmp;
590 /* Now place the memory as high up as it will go */
591 mem2->base = resource_max(mem2);
592 mem1->limit = mem2->base - 1;
593 mem1->base = resource_max(mem2);
596 /* Place the resources as high up as they will go */
597 mem2->base = resource_max(mem2);
598 mem1->base = resource_max(mem1);
602 printk_debug("base1: 0x%08Lx limit1: 0x%08lx size: 0x%08Lx\n",
603 mem1->base, mem1->limit, mem1->size);
604 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx\n",
605 mem2->base, mem2->limit, mem2->size);
608 pci_tolm = 0xffffffffUL;
609 last = &dev->resource[dev->resources];
610 for(resource = &dev->resource[0]; resource < last; resource++)
613 resource->flags |= IORESOURCE_ASSIGNED;
614 resource->flags &= ~IORESOURCE_STORED;
616 compute_allocate_resource(&dev->link[0], resource,
617 BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
619 resource->flags |= IORESOURCE_STORED;
620 report_resource_stored(dev, resource, "");
622 if ((resource->flags & IORESOURCE_MEM) &&
623 (pci_tolm > resource->base))
625 pci_tolm = resource->base;
629 #warning "FIXME handle interleaved nodes"
630 mmio_basek = pci_tolm >> 10;
631 /* Round mmio_basek to something the processor can support */
632 mmio_basek &= ~((1 << 6) -1);
635 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
636 /* Round the mmio hold to 64M */
637 mmio_basek &= ~((64*1024) - 1);
641 for(i = 0; i < 8; i++) {
642 uint32_t base, limit;
643 unsigned basek, limitk, sizek;
644 base = f1_read_config32(0x40 + (i << 3));
645 limit = f1_read_config32(0x44 + (i << 3));
646 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
649 basek = (base & 0xffff0000) >> 2;
650 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
651 sizek = limitk - basek;
653 /* see if we need a hole from 0xa0000 to 0xbffff */
654 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
655 ram_resource(dev, idx++, basek, ((8*64)+(8*16)) - basek);
656 basek = (8*64)+(16*16);
657 sizek = limitk - ((8*64)+(16*16));
662 /* See if I need to split the region to accomodate pci memory space */
663 if ((basek < mmio_basek) && (limitk > mmio_basek)) {
664 if (basek < mmio_basek) {
666 pre_sizek = mmio_basek - basek;
667 ram_resource(dev, idx++, basek, pre_sizek);
671 if ((basek + sizek) <= 4*1024*1024) {
676 sizek -= (4*1024*1024 - mmio_basek);
679 ram_resource(dev, idx++, basek, sizek);
682 assign_resources(&dev->link[0]);
685 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
689 /* Unmap all of the HT chains */
690 for(reg = 0xe0; reg <= 0xec; reg += 4) {
691 f1_write_config32(reg, 0);
693 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
697 static struct device_operations pci_domain_ops = {
698 .read_resources = pci_domain_read_resources,
699 .set_resources = pci_domain_set_resources,
700 .enable_resources = enable_childrens_resources,
702 .scan_bus = pci_domain_scan_bus,
705 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
711 /* Find which cpus are present */
712 cpu_bus = &dev->link[0];
713 for(i = 0; i < 7; i++) {
715 struct device_path cpu_path;
717 /* Find the cpu's memory controller */
718 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
720 /* Build the cpu device path */
721 cpu_path.type = DEVICE_PATH_APIC;
722 cpu_path.u.apic.apic_id = i;
724 /* See if I can find the cpu */
725 cpu = find_dev_path(cpu_bus, &cpu_path);
727 /* Enable the cpu if I have the processor */
728 if (dev && dev->enabled) {
730 cpu = alloc_dev(cpu_bus, &cpu_path);
737 /* Disable the cpu if I don't have the processor */
738 if (cpu && (!dev || !dev->enabled)) {
742 /* Report what I have done */
744 printk_debug("CPU: %s %s\n",
745 dev_path(cpu), cpu->enabled?"enabled":"disabled");
751 static void cpu_bus_init(device_t dev)
753 initialize_cpus(&dev->link[0]);
756 static void cpu_bus_noop(device_t dev)
760 static struct device_operations cpu_bus_ops = {
761 .read_resources = cpu_bus_noop,
762 .set_resources = cpu_bus_noop,
763 .enable_resources = cpu_bus_noop,
764 .init = cpu_bus_init,
765 .scan_bus = cpu_bus_scan,
768 static void enable_dev(struct device *dev)
770 struct device_path path;
772 /* Set the operations if it is a special bus type */
773 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
774 dev->ops = &pci_domain_ops;
776 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
777 dev->ops = &cpu_bus_ops;
781 struct chip_operations northbridge_amd_amdk8_ops = {
782 .name = "AMD K8 Northbridge",
783 .enable_dev = enable_dev,