1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/hypertransport.h>
13 #include "root_complex/chip.h"
14 #include "northbridge.h"
18 static device_t __f0_dev[FX_DEVS];
19 static device_t __f1_dev[FX_DEVS];
22 static void debug_fx_devs(void)
25 for(i = 0; i < FX_DEVS; i++) {
29 printk_debug("__f0_dev[%d]: %s bus: %p\n",
30 i, dev_path(dev), dev->bus);
34 printk_debug("__f1_dev[%d]: %s bus: %p\n",
35 i, dev_path(dev), dev->bus);
41 static void get_fx_devs(void)
47 for(i = 0; i < FX_DEVS; i++) {
48 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
49 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
52 die("Cannot find 0:0x18.1\n");
56 static uint32_t f1_read_config32(unsigned reg)
59 return pci_read_config32(__f1_dev[0], reg);
62 static void f1_write_config32(unsigned reg, uint32_t value)
66 for(i = 0; i < FX_DEVS; i++) {
69 if (dev && dev->enabled) {
70 pci_write_config32(dev, reg, value);
75 static unsigned int amdk8_nodeid(device_t dev)
77 return (dev->path.u.pci.devfn >> 3) - 0x18;
80 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
84 nodeid = amdk8_nodeid(dev);
86 printk_debug("%s amdk8_scan_chains max: %d starting...\n",
89 for(link = 0; link < dev->links; link++) {
91 uint32_t busses, config_busses;
92 unsigned free_reg, config_reg;
93 dev->link[link].cap = 0x80 + (link *0x20);
95 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
96 } while(link_type & ConnectionPending);
97 if (!(link_type & LinkConnected)) {
101 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
102 } while(!(link_type & InitComplete));
103 if (!(link_type & NonCoherent)) {
106 /* See if there is an available configuration space mapping register in function 1. */
108 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
110 config = f1_read_config32(config_reg);
111 if (!free_reg && ((config & 3) == 0)) {
112 free_reg = config_reg;
115 if (((config & 3) == 3) &&
116 (((config >> 4) & 7) == nodeid) &&
117 (((config >> 8) & 3) == link)) {
121 if (free_reg && (config_reg > 0xec)) {
122 config_reg = free_reg;
124 /* If we can't find an available configuration space mapping register skip this bus */
125 if (config_reg > 0xec) {
129 /* Set up the primary, secondary and subordinate bus numbers. We have
130 * no idea how many busses are behind this bridge yet, so we set the subordinate
131 * bus number to 0xff for the moment.
133 dev->link[link].secondary = ++max;
134 dev->link[link].subordinate = 0xff;
136 /* Read the existing primary/secondary/subordinate bus
137 * number configuration.
139 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
140 config_busses = f1_read_config32(config_reg);
142 /* Configure the bus numbers for this bridge: the configuration
143 * transactions will not be propagates by the bridge if it is not
144 * correctly configured
146 busses &= 0xff000000;
147 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
148 ((unsigned int)(dev->link[link].secondary) << 8) |
149 ((unsigned int)(dev->link[link].subordinate) << 16));
150 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
152 config_busses &= 0x000fc88;
154 (3 << 0) | /* rw enable, no device compare */
155 (( nodeid & 7) << 4) |
156 (( link & 3 ) << 8) |
157 ((dev->link[link].secondary) << 16) |
158 ((dev->link[link].subordinate) << 24);
159 f1_write_config32(config_reg, config_busses);
162 printk_debug("%s Hyper transport scan link: %d max: %d\n",
163 dev_path(dev), link, max);
165 /* Now we can scan all of the subordinate busses i.e. the chain on the hypertranport link */
166 max = hypertransport_scan_chain(&dev->link[link], max);
169 printk_debug("%s Hyper transport scan link: %d new max: %d\n",
170 dev_path(dev), link, max);
173 /* We know the number of busses behind this bridge. Set the subordinate
174 * bus number to it's real value
176 dev->link[link].subordinate = max;
177 busses = (busses & 0xff00ffff) |
178 ((unsigned int) (dev->link[link].subordinate) << 16);
179 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
181 config_busses = (config_busses & 0x00ffffff) | (dev->link[link].subordinate << 24);
182 f1_write_config32(config_reg, config_busses);
184 printk_debug("%s Hypertransport scan link: %d done\n",
185 dev_path(dev), link);
189 printk_debug("%s amdk8_scan_chains max: %d done\n",
195 static int reg_useable(unsigned reg,
196 device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
198 struct resource *res;
199 unsigned nodeid, link;
202 for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
204 dev = __f0_dev[nodeid];
205 for(link = 0; !res && (link < 3); link++) {
206 res = probe_resource(dev, 0x100 + (reg | link));
212 if ( (goal_link == (link - 1)) &&
213 (goal_nodeid == (nodeid - 1)) &&
219 printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
221 goal_nodeid, goal_link,
228 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
230 struct resource *resource;
231 unsigned free_reg, reg;
234 for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
236 result = reg_useable(reg, dev, nodeid, link);
238 /* I have been allocated this one */
241 else if (result > 1) {
242 /* I have a free register pair */
250 resource = new_resource(dev, 0x100 + (reg | link));
255 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
257 struct resource *resource;
258 unsigned free_reg, reg;
261 for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
263 result = reg_useable(reg, dev, nodeid, link);
265 /* I have been allocated this one */
268 else if (result > 1) {
269 /* I have a free register pair */
277 resource = new_resource(dev, 0x100 + (reg | link));
281 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
283 struct resource *resource;
285 /* Initialize the io space constraints on the current bus */
286 resource = amdk8_find_iopair(dev, nodeid, link);
290 resource->align = log2(HT_IO_HOST_ALIGN);
291 resource->gran = log2(HT_IO_HOST_ALIGN);
292 resource->limit = 0xffffUL;
293 resource->flags = IORESOURCE_IO;
294 compute_allocate_resource(&dev->link[link], resource,
295 IORESOURCE_IO, IORESOURCE_IO);
298 /* Initialize the prefetchable memory constraints on the current bus */
299 resource = amdk8_find_mempair(dev, nodeid, link);
303 resource->align = log2(HT_MEM_HOST_ALIGN);
304 resource->gran = log2(HT_MEM_HOST_ALIGN);
305 resource->limit = 0xffffffffffULL;
306 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
307 compute_allocate_resource(&dev->link[link], resource,
308 IORESOURCE_MEM | IORESOURCE_PREFETCH,
309 IORESOURCE_MEM | IORESOURCE_PREFETCH);
312 /* Initialize the memory constraints on the current bus */
313 resource = amdk8_find_mempair(dev, nodeid, link);
317 resource->align = log2(HT_MEM_HOST_ALIGN);
318 resource->gran = log2(HT_MEM_HOST_ALIGN);
319 resource->limit = 0xffffffffffULL;
320 resource->flags = IORESOURCE_MEM;
321 compute_allocate_resource(&dev->link[link], resource,
322 IORESOURCE_MEM | IORESOURCE_PREFETCH,
327 static void amdk8_read_resources(device_t dev)
329 unsigned nodeid, link;
330 nodeid = amdk8_nodeid(dev);
331 for(link = 0; link < dev->links; link++) {
332 if (dev->link[link].children) {
333 amdk8_link_read_bases(dev, nodeid, link);
338 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
340 resource_t rbase, rend;
344 /* Make certain the resource has actually been set */
345 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
349 /* If I have already stored this resource don't worry about it */
350 if (resource->flags & IORESOURCE_STORED) {
354 /* Only handle PCI memory and IO resources */
355 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
358 /* Ensure I am actually looking at a resource of function 1 */
359 if (resource->index < 0x100) {
362 /* Get the base address */
363 rbase = resource->base;
365 /* Get the limit (rounded up) */
366 rend = resource_end(resource);
368 /* Get the register and link */
369 reg = resource->index & 0xfc;
370 link = resource->index & 3;
372 if (resource->flags & IORESOURCE_IO) {
373 uint32_t base, limit;
374 compute_allocate_resource(&dev->link[link], resource,
375 IORESOURCE_IO, IORESOURCE_IO);
376 base = f1_read_config32(reg);
377 limit = f1_read_config32(reg + 0x4);
379 base |= rbase & 0x01fff000;
382 limit |= rend & 0x01fff000;
383 limit |= (link & 3) << 4;
384 limit |= (nodeid & 7);
386 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
387 base |= PCI_IO_BASE_VGA_EN;
389 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
390 base |= PCI_IO_BASE_NO_ISA;
393 f1_write_config32(reg + 0x4, limit);
394 f1_write_config32(reg, base);
396 else if (resource->flags & IORESOURCE_MEM) {
397 uint32_t base, limit;
398 compute_allocate_resource(&dev->link[link], resource,
399 IORESOURCE_MEM | IORESOURCE_PREFETCH,
400 resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
401 base = f1_read_config32(reg);
402 limit = f1_read_config32(reg + 0x4);
404 base |= (rbase >> 8) & 0xffffff00;
407 limit |= (rend >> 8) & 0xffffff00;
408 limit |= (link & 3) << 4;
409 limit |= (nodeid & 7);
410 f1_write_config32(reg + 0x4, limit);
411 f1_write_config32(reg, base);
413 resource->flags |= IORESOURCE_STORED;
414 sprintf(buf, " <node %d link %d>",
416 report_resource_stored(dev, resource, buf);
419 static void amdk8_set_resources(device_t dev)
421 unsigned nodeid, link;
424 /* Find the nodeid */
425 nodeid = amdk8_nodeid(dev);
427 /* Set each resource we have found */
428 for(i = 0; i < dev->resources; i++) {
429 amdk8_set_resource(dev, &dev->resource[i], nodeid);
432 for(link = 0; link < dev->links; link++) {
434 bus = &dev->link[link];
436 assign_resources(bus);
441 static void amdk8_enable_resources(device_t dev)
443 pci_dev_enable_resources(dev);
444 enable_childrens_resources(dev);
447 static void mcf0_control_init(struct device *dev)
452 printk_debug("NB: Function 0 Misc Control.. ");
455 /* improve latency and bandwith on HT */
456 cmd = pci_read_config32(dev, 0x68);
459 pci_write_config32(dev, 0x68, cmd );
463 /* over drive the ht port to 1000 Mhz */
464 cmd = pci_read_config32(dev, 0xa8);
467 pci_write_config32(dev, 0xdc, cmd );
470 printk_debug("done.\n");
474 static struct device_operations northbridge_operations = {
475 .read_resources = amdk8_read_resources,
476 .set_resources = amdk8_set_resources,
477 .enable_resources = amdk8_enable_resources,
478 .init = mcf0_control_init,
479 .scan_bus = amdk8_scan_chains,
485 static struct pci_driver mcf0_driver __pci_driver = {
486 .ops = &northbridge_operations,
487 .vendor = PCI_VENDOR_ID_AMD,
492 struct chip_operations northbridge_amd_amdk8_ops = {
493 CHIP_NAME("AMD K8 Northbridge")
497 static void pci_domain_read_resources(device_t dev)
499 struct resource *resource;
502 /* Find the already assigned resource pairs */
504 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
505 uint32_t base, limit;
506 base = f1_read_config32(reg);
507 limit = f1_read_config32(reg + 0x04);
508 /* Is this register allocated? */
509 if ((base & 3) != 0) {
510 unsigned nodeid, link;
513 link = (limit >> 4) & 3;
514 dev = __f0_dev[nodeid];
516 /* Reserve the resource */
517 struct resource *resource;
518 resource = new_resource(dev, 0x100 + (reg | link));
526 /* Initialize the system wide io space constraints */
527 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
528 resource->base = 0x400;
529 resource->limit = 0xffffUL;
530 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
532 /* Initialize the system wide memory resources constraints */
533 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
534 resource->limit = 0xfcffffffffULL;
535 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
538 static void ram_resource(device_t dev, unsigned long index,
539 unsigned long basek, unsigned long sizek)
541 struct resource *resource;
546 resource = new_resource(dev, index);
547 resource->base = ((resource_t)basek) << 10;
548 resource->size = ((resource_t)sizek) << 10;
549 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
550 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
553 static void tolm_test(void *gp, struct device *dev, struct resource *new)
555 struct resource **best_p = gp;
556 struct resource *best;
558 if (!best || (best->base > new->base)) {
564 static uint32_t find_pci_tolm(struct bus *bus)
566 struct resource *min;
569 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
571 if (min && tolm > min->base) {
577 static void pci_domain_set_resources(device_t dev)
579 unsigned long mmio_basek;
583 pci_tolm = find_pci_tolm(&dev->link[0]);
585 #warning "FIXME handle interleaved nodes"
586 mmio_basek = pci_tolm >> 10;
587 /* Round mmio_basek to something the processor can support */
588 mmio_basek &= ~((1 << 6) -1);
591 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
592 /* Round the mmio hold to 64M */
593 mmio_basek &= ~((64*1024) - 1);
597 for(i = 0; i < 8; i++) {
598 uint32_t base, limit;
599 unsigned basek, limitk, sizek;
600 base = f1_read_config32(0x40 + (i << 3));
601 limit = f1_read_config32(0x44 + (i << 3));
602 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
605 basek = (base & 0xffff0000) >> 2;
606 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
607 sizek = limitk - basek;
609 /* see if we need a hole from 0xa0000 to 0xbffff */
610 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
611 ram_resource(dev, idx++, basek, ((8*64)+(8*16)) - basek);
612 basek = (8*64)+(16*16);
613 sizek = limitk - ((8*64)+(16*16));
618 /* See if I need to split the region to accomodate pci memory space */
619 if ((basek < mmio_basek) && (limitk > mmio_basek)) {
620 if (basek < mmio_basek) {
622 pre_sizek = mmio_basek - basek;
623 ram_resource(dev, idx++, basek, pre_sizek);
627 if ((basek + sizek) <= 4*1024*1024) {
632 sizek -= (4*1024*1024 - mmio_basek);
635 ram_resource(dev, idx++, basek, sizek);
637 assign_resources(&dev->link[0]);
640 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
643 /* Unmap all of the HT chains */
644 for(reg = 0xe0; reg <= 0xec; reg += 4) {
645 f1_write_config32(reg, 0);
647 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
651 static struct device_operations pci_domain_ops = {
652 .read_resources = pci_domain_read_resources,
653 .set_resources = pci_domain_set_resources,
654 .enable_resources = enable_childrens_resources,
656 .scan_bus = pci_domain_scan_bus,
659 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
664 /* Find which cpus are present */
665 cpu_bus = &dev->link[0];
666 for(i = 0; i < 8; i++) {
668 struct device_path cpu_path;
670 /* Find the cpu's memory controller */
671 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
673 /* Build the cpu device path */
674 cpu_path.type = DEVICE_PATH_APIC;
675 cpu_path.u.apic.apic_id = i;
677 /* See if I can find the cpu */
678 cpu = find_dev_path(cpu_bus, &cpu_path);
680 /* Enable the cpu if I have the processor */
681 if (dev && dev->enabled) {
683 cpu = alloc_dev(cpu_bus, &cpu_path);
690 /* Disable the cpu if I don't have the processor */
691 if (cpu && (!dev || !dev->enabled)) {
695 /* Report what I have done */
697 printk_debug("CPU: %s %s\n",
698 dev_path(cpu), cpu->enabled?"enabled":"disabled");
704 static void cpu_bus_init(device_t dev)
706 initialize_cpus(&dev->link[0]);
709 static void cpu_bus_noop(device_t dev)
713 static struct device_operations cpu_bus_ops = {
714 .read_resources = cpu_bus_noop,
715 .set_resources = cpu_bus_noop,
716 .enable_resources = cpu_bus_noop,
717 .init = cpu_bus_init,
718 .scan_bus = cpu_bus_scan,
721 static void root_complex_enable_dev(struct device *dev)
723 /* Set the operations if it is a special bus type */
724 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
725 dev->ops = &pci_domain_ops;
726 pci_set_method_conf1();
728 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
729 dev->ops = &cpu_bus_ops;
733 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
734 CHIP_NAME("AMD K8 Root Complex")
735 .enable_dev = root_complex_enable_dev,