1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/hypertransport.h>
13 #include "root_complex/chip.h"
14 #include "northbridge.h"
16 #include <cpu/x86/lapic.h>
19 static device_t __f0_dev[FX_DEVS];
20 static device_t __f1_dev[FX_DEVS];
23 static void debug_fx_devs(void)
26 for (i = 0; i < FX_DEVS; i++) {
30 printk_debug("__f0_dev[%d]: %s bus: %p\n",
31 i, dev_path(dev), dev->bus);
35 printk_debug("__f1_dev[%d]: %s bus: %p\n",
36 i, dev_path(dev), dev->bus);
42 static void get_fx_devs(void)
48 for (i = 0; i < FX_DEVS; i++) {
49 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
50 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
53 die("Cannot find 0:0x18.1\n");
57 static uint32_t f1_read_config32(unsigned reg)
60 return pci_read_config32(__f1_dev[0], reg);
63 static void f1_write_config32(unsigned reg, uint32_t value)
67 for (i = 0; i < FX_DEVS; i++) {
70 if (dev && dev->enabled) {
71 pci_write_config32(dev, reg, value);
76 static unsigned int amdk8_nodeid(device_t dev)
78 return (dev->path.u.pci.devfn >> 3) - 0x18;
81 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
85 nodeid = amdk8_nodeid(dev);
87 printk_debug("%s amdk8_scan_chains max: %d starting...\n",
90 for (link = 0; link < dev->links; link++) {
92 uint32_t busses, config_busses;
93 unsigned free_reg, config_reg;
94 dev->link[link].cap = 0x80 + (link *0x20);
96 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
97 } while(link_type & ConnectionPending);
98 if (!(link_type & LinkConnected)) {
102 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
103 } while(!(link_type & InitComplete));
104 if (!(link_type & NonCoherent)) {
107 /* See if there is an available configuration space mapping
108 * register in function 1. */
110 for (config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
112 config = f1_read_config32(config_reg);
113 if (!free_reg && ((config & 3) == 0)) {
114 free_reg = config_reg;
117 if (((config & 3) == 3) &&
118 (((config >> 4) & 7) == nodeid) &&
119 (((config >> 8) & 3) == link)) {
123 if (free_reg && (config_reg > 0xec)) {
124 config_reg = free_reg;
126 /* If we can't find an available configuration space mapping
127 * register skip this bus */
128 if (config_reg > 0xec) {
132 /* Set up the primary, secondary and subordinate bus numbers.
133 * We have no idea how many busses are behind this bridge yet,
134 * so we set the subordinate bus number to 0xff for the moment.
136 dev->link[link].secondary = ++max;
137 dev->link[link].subordinate = 0xff;
139 /* Read the existing primary/secondary/subordinate bus
140 * number configuration.
142 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
143 config_busses = f1_read_config32(config_reg);
145 /* Configure the bus numbers for this bridge: the configuration
146 * transactions will not be propagates by the bridge if it is
147 * not correctly configured
149 busses &= 0xff000000;
150 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
151 ((unsigned int)(dev->link[link].secondary) << 8) |
152 ((unsigned int)(dev->link[link].subordinate) << 16));
153 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
155 config_busses &= 0x000fc88;
157 (3 << 0) | /* rw enable, no device compare */
158 (( nodeid & 7) << 4) |
159 (( link & 3 ) << 8) |
160 ((dev->link[link].secondary) << 16) |
161 ((dev->link[link].subordinate) << 24);
162 f1_write_config32(config_reg, config_busses);
165 printk_debug("%s Hyper transport scan link: %d max: %d\n",
166 dev_path(dev), link, max);
168 /* Now we can scan all of the subordinate busses i.e. the
169 * chain on the hypertranport link */
170 max = hypertransport_scan_chain(&dev->link[link], max);
173 printk_debug("%s Hyper transport scan link: %d new max: %d\n",
174 dev_path(dev), link, max);
177 /* We know the number of busses behind this bridge. Set the
178 * subordinate bus number to it's real value
180 dev->link[link].subordinate = max;
181 busses = (busses & 0xff00ffff) |
182 ((unsigned int) (dev->link[link].subordinate) << 16);
183 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
185 config_busses = (config_busses & 0x00ffffff) |
186 (dev->link[link].subordinate << 24);
187 f1_write_config32(config_reg, config_busses);
189 printk_debug("%s Hypertransport scan link: %d done\n",
190 dev_path(dev), link);
194 printk_debug("%s amdk8_scan_chains max: %d done\n",
200 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
203 struct resource *res;
204 unsigned nodeid, link;
207 for (nodeid = 0; !res && (nodeid < 8); nodeid++) {
209 dev = __f0_dev[nodeid];
210 for (link = 0; !res && (link < 3); link++) {
211 res = probe_resource(dev, 0x100 + (reg | link));
217 if ((goal_link == (link - 1)) &&
218 (goal_nodeid == (nodeid - 1)) &&
224 printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
225 reg, result, goal_nodeid, goal_link, nodeid, link);
230 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
232 struct resource *resource;
233 unsigned free_reg, reg;
236 for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
238 result = reg_useable(reg, dev, nodeid, link);
240 /* I have been allocated this one */
243 else if (result > 1) {
244 /* I have a free register pair */
252 resource = new_resource(dev, 0x100 + (reg | link));
257 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
259 struct resource *resource;
260 unsigned free_reg, reg;
263 for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
265 result = reg_useable(reg, dev, nodeid, link);
267 /* I have been allocated this one */
270 else if (result > 1) {
271 /* I have a free register pair */
279 resource = new_resource(dev, 0x100 + (reg | link));
284 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
286 struct resource *resource;
288 /* Initialize the io space constraints on the current bus */
289 resource = amdk8_find_iopair(dev, nodeid, link);
293 resource->align = log2(HT_IO_HOST_ALIGN);
294 resource->gran = log2(HT_IO_HOST_ALIGN);
295 resource->limit = 0xffffUL;
296 resource->flags = IORESOURCE_IO;
297 compute_allocate_resource(&dev->link[link], resource,
298 IORESOURCE_IO, IORESOURCE_IO);
301 /* Initialize the prefetchable memory constraints on the current bus */
302 resource = amdk8_find_mempair(dev, nodeid, link);
306 resource->align = log2(HT_MEM_HOST_ALIGN);
307 resource->gran = log2(HT_MEM_HOST_ALIGN);
308 resource->limit = 0xffffffffffULL;
309 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
310 compute_allocate_resource(&dev->link[link], resource,
311 IORESOURCE_MEM | IORESOURCE_PREFETCH,
312 IORESOURCE_MEM | IORESOURCE_PREFETCH);
315 /* Initialize the memory constraints on the current bus */
316 resource = amdk8_find_mempair(dev, nodeid, link);
320 resource->align = log2(HT_MEM_HOST_ALIGN);
321 resource->gran = log2(HT_MEM_HOST_ALIGN);
322 resource->limit = 0xffffffffffULL;
323 resource->flags = IORESOURCE_MEM;
324 compute_allocate_resource(&dev->link[link], resource,
325 IORESOURCE_MEM | IORESOURCE_PREFETCH,
330 static void amdk8_read_resources(device_t dev)
332 unsigned nodeid, link;
333 nodeid = amdk8_nodeid(dev);
334 for (link = 0; link < dev->links; link++) {
335 if (dev->link[link].children) {
336 amdk8_link_read_bases(dev, nodeid, link);
341 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
343 resource_t rbase, rend;
347 /* Make certain the resource has actually been set */
348 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
352 /* If I have already stored this resource don't worry about it */
353 if (resource->flags & IORESOURCE_STORED) {
357 /* Only handle PCI memory and IO resources */
358 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
361 /* Ensure I am actually looking at a resource of function 1 */
362 if (resource->index < 0x100) {
365 /* Get the base address */
366 rbase = resource->base;
368 /* Get the limit (rounded up) */
369 rend = resource_end(resource);
371 /* Get the register and link */
372 reg = resource->index & 0xfc;
373 link = resource->index & 3;
375 if (resource->flags & IORESOURCE_IO) {
376 uint32_t base, limit;
377 compute_allocate_resource(&dev->link[link], resource,
378 IORESOURCE_IO, IORESOURCE_IO);
379 base = f1_read_config32(reg);
380 limit = f1_read_config32(reg + 0x4);
382 base |= rbase & 0x01fff000;
385 limit |= rend & 0x01fff000;
386 limit |= (link & 3) << 4;
387 limit |= (nodeid & 7);
389 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
390 printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
391 __func__, dev_path(dev), link);
392 base |= PCI_IO_BASE_VGA_EN;
394 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
395 base |= PCI_IO_BASE_NO_ISA;
398 f1_write_config32(reg + 0x4, limit);
399 f1_write_config32(reg, base);
401 else if (resource->flags & IORESOURCE_MEM) {
402 uint32_t base, limit;
403 compute_allocate_resource(&dev->link[link], resource,
404 IORESOURCE_MEM | IORESOURCE_PREFETCH,
405 resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
406 base = f1_read_config32(reg);
407 limit = f1_read_config32(reg + 0x4);
409 base |= (rbase >> 8) & 0xffffff00;
412 limit |= (rend >> 8) & 0xffffff00;
413 limit |= (link & 3) << 4;
414 limit |= (nodeid & 7);
415 f1_write_config32(reg + 0x4, limit);
416 f1_write_config32(reg, base);
418 resource->flags |= IORESOURCE_STORED;
419 sprintf(buf, " <node %d link %d>",
421 report_resource_stored(dev, resource, buf);
426 * I tried to reuse the resource allocation code in amdk8_set_resource()
427 * but it is too diffcult to deal with the resource allocation magic.
429 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
431 struct resource *resource;
433 uint32_t base, limit;
436 /* find out which link the VGA card is connected,
437 * we only deal with the 'first' vga card */
438 for (link = 0; link < dev->links; link++) {
439 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
444 printk_spew("%s: link %d has VGA device\n", __func__, link);
446 /* no VGA card installed */
447 if (link == dev->links)
450 /* allocate a temp resrouce for legacy VGA buffer */
451 resource = amdk8_find_mempair(dev, nodeid, link);
452 resource->base = 0xa0000;
453 resource->size = 0x20000;
455 /* write the resource to the hardware */
456 reg = resource->index & 0xfc;
457 base = f1_read_config32(reg);
458 limit = f1_read_config32(reg + 0x4);
460 base |= (resource->base >> 8) & 0xffffff00;
463 limit |= ((resource->base + resource->size) >> 8) & 0xffffff00;
464 limit |= (resource->index & 3) << 4;
465 limit |= (nodeid & 7);
466 f1_write_config32(reg + 0x4, limit);
467 f1_write_config32(reg, base);
469 /* release the temp resource */
473 static void amdk8_set_resources(device_t dev)
475 unsigned nodeid, link;
478 /* Find the nodeid */
479 nodeid = amdk8_nodeid(dev);
481 amdk8_create_vga_resource(dev, nodeid);
483 /* Set each resource we have found */
484 for (i = 0; i < dev->resources; i++) {
485 amdk8_set_resource(dev, &dev->resource[i], nodeid);
488 for (link = 0; link < dev->links; link++) {
490 bus = &dev->link[link];
492 assign_resources(bus);
497 static void amdk8_enable_resources(device_t dev)
499 pci_dev_enable_resources(dev);
500 enable_childrens_resources(dev);
503 static void mcf0_control_init(struct device *dev)
508 printk_debug("NB: Function 0 Misc Control.. ");
511 /* improve latency and bandwith on HT */
512 cmd = pci_read_config32(dev, 0x68);
515 pci_write_config32(dev, 0x68, cmd );
519 /* over drive the ht port to 1000 Mhz */
520 cmd = pci_read_config32(dev, 0xa8);
523 pci_write_config32(dev, 0xdc, cmd );
526 printk_debug("done.\n");
530 static struct device_operations northbridge_operations = {
531 .read_resources = amdk8_read_resources,
532 .set_resources = amdk8_set_resources,
533 .enable_resources = amdk8_enable_resources,
534 .init = mcf0_control_init,
535 .scan_bus = amdk8_scan_chains,
541 static struct pci_driver mcf0_driver __pci_driver = {
542 .ops = &northbridge_operations,
543 .vendor = PCI_VENDOR_ID_AMD,
547 #if CONFIG_CHIP_NAME == 1
549 struct chip_operations northbridge_amd_amdk8_ops = {
550 CHIP_NAME("AMD K8 Northbridge")
556 static void pci_domain_read_resources(device_t dev)
558 struct resource *resource;
561 /* Find the already assigned resource pairs */
563 for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
564 uint32_t base, limit;
565 base = f1_read_config32(reg);
566 limit = f1_read_config32(reg + 0x04);
567 /* Is this register allocated? */
568 if ((base & 3) != 0) {
569 unsigned nodeid, link;
572 link = (limit >> 4) & 3;
573 dev = __f0_dev[nodeid];
575 /* Reserve the resource */
576 struct resource *resource;
577 resource = new_resource(dev, 0x100 + (reg | link));
585 /* Initialize the system wide io space constraints */
586 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
587 resource->base = 0x400;
588 resource->limit = 0xffffUL;
589 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
591 /* Initialize the system wide memory resources constraints */
592 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
593 resource->limit = 0xfcffffffffULL;
594 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
597 static void ram_resource(device_t dev, unsigned long index,
598 unsigned long basek, unsigned long sizek)
600 struct resource *resource;
605 resource = new_resource(dev, index);
606 resource->base = ((resource_t)basek) << 10;
607 resource->size = ((resource_t)sizek) << 10;
608 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
609 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
612 static void tolm_test(void *gp, struct device *dev, struct resource *new)
614 struct resource **best_p = gp;
615 struct resource *best;
617 if (!best || (best->base > new->base)) {
623 static uint32_t find_pci_tolm(struct bus *bus)
625 struct resource *min;
628 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
630 if (min && tolm > min->base) {
636 static void pci_domain_set_resources(device_t dev)
638 unsigned long mmio_basek;
642 pci_tolm = find_pci_tolm(&dev->link[0]);
644 #warning "FIXME handle interleaved nodes"
645 mmio_basek = pci_tolm >> 10;
646 /* Round mmio_basek to something the processor can support */
647 mmio_basek &= ~((1 << 6) -1);
650 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
651 /* Round the mmio hold to 64M */
652 mmio_basek &= ~((64*1024) - 1);
656 for (i = 0; i < 8; i++) {
657 uint32_t base, limit;
658 unsigned basek, limitk, sizek;
659 base = f1_read_config32(0x40 + (i << 3));
660 limit = f1_read_config32(0x44 + (i << 3));
661 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
664 basek = (base & 0xffff0000) >> 2;
665 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
666 sizek = limitk - basek;
668 /* see if we need a hole from 0xa0000 to 0xbffff */
669 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
670 ram_resource(dev, idx++, basek, ((8*64)+(8*16)) - basek);
671 basek = (8*64)+(16*16);
672 sizek = limitk - ((8*64)+(16*16));
676 /* See if I need to split the region to accomodate pci memory space */
677 if ((basek < mmio_basek) && (limitk > mmio_basek)) {
678 if (basek < mmio_basek) {
680 pre_sizek = mmio_basek - basek;
681 ram_resource(dev, idx++, basek, pre_sizek);
685 if ((basek + sizek) <= 4*1024*1024) {
690 sizek -= (4*1024*1024 - mmio_basek);
693 ram_resource(dev, idx++, basek, sizek);
695 assign_resources(&dev->link[0]);
698 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
701 /* Unmap all of the HT chains */
702 for (reg = 0xe0; reg <= 0xec; reg += 4) {
703 f1_write_config32(reg, 0);
705 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
709 static struct device_operations pci_domain_ops = {
710 .read_resources = pci_domain_read_resources,
711 .set_resources = pci_domain_set_resources,
712 .enable_resources = enable_childrens_resources,
714 .scan_bus = pci_domain_scan_bus,
715 .ops_pci_bus = &pci_cf8_conf1,
718 #define APIC_ID_OFFSET 0x10
720 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
725 int enable_apic_ext_id = 0;
726 int bsp_apic_id = lapicid(); // bsp apicid
727 int apic_id_offset = bsp_apic_id;
729 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
730 if (pci_read_config32(dev_mc, 0x68) & ( HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST)) {
731 enable_apic_ext_id = 1;
732 if (apic_id_offset==0) {
733 //bsp apic id is not changed
734 apic_id_offset = APIC_ID_OFFSET;
738 /* Find which cpus are present */
739 cpu_bus = &dev->link[0];
740 for (i = 0; i < 8; i++) {
742 struct device_path cpu_path;
744 /* Find the cpu's memory controller */
745 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
747 // in case in mb Config.lb we move apic cluster before pci_domain and not set that for second CPU
750 dummy.bus = dev_mc->bus;
751 dummy.path.type = DEVICE_PATH_PCI;
752 dummy.path.u.pci.devfn = PCI_DEVFN(0x18 + i, 3);
753 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
754 if (id != 0xffffffff && id != 0x00000000 &&
755 id != 0x0000ffff && id != 0xffff0000) {
757 dev = alloc_dev(dev_mc->bus, &dummy.path);
761 /* Build the cpu device path */
762 cpu_path.type = DEVICE_PATH_APIC;
763 cpu_path.u.apic.apic_id = i;
765 /* See if I can find the cpu */
766 cpu = find_dev_path(cpu_bus, &cpu_path);
768 /* Enable the cpu if I have the processor */
769 if (dev && dev->enabled) {
771 cpu = alloc_dev(cpu_bus, &cpu_path);
778 /* Disable the cpu if I don't have the processor */
779 if (cpu && (!dev || !dev->enabled)) {
783 /* Report what I have done */
785 if(enable_apic_ext_id) {
786 if(cpu->path.u.apic.apic_id<apic_id_offset) {
787 //all add offset except bsp cores
788 if( (cpu->path.u.apic.apic_id > 0) || (bsp_apic_id!=0) )
789 cpu->path.u.apic.apic_id += apic_id_offset;
792 printk_debug("CPU: %s %s\n", dev_path(cpu),
793 cpu->enabled?"enabled":"disabled");
799 static void cpu_bus_init(device_t dev)
801 initialize_cpus(&dev->link[0]);
804 static void cpu_bus_noop(device_t dev)
808 static struct device_operations cpu_bus_ops = {
809 .read_resources = cpu_bus_noop,
810 .set_resources = cpu_bus_noop,
811 .enable_resources = cpu_bus_noop,
812 .init = cpu_bus_init,
813 .scan_bus = cpu_bus_scan,
816 static void root_complex_enable_dev(struct device *dev)
818 /* Set the operations if it is a special bus type */
819 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
820 dev->ops = &pci_domain_ops;
822 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
823 dev->ops = &cpu_bus_ops;
827 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
828 CHIP_NAME("AMD K8 Root Complex")
829 .enable_dev = root_complex_enable_dev,