1 /* This should be done by Eric
2 2004.12 yhlu add dual core support
3 2005.01 yhlu add support move apic before pci_domain in MB Config.lb
4 2005.02 yhlu add e0 memory hole support
5 2005.11 yhlu add put sb ht chain on bus 0
8 #include <console/console.h>
11 #include <device/device.h>
12 #include <device/pci.h>
13 #include <device/pci_ids.h>
14 #include <device/hypertransport.h>
20 #include <cpu/x86/lapic.h>
22 #if CONFIG_LOGICAL_CPUS==1
23 #include <cpu/amd/dualcore.h>
24 #include <pc80/mc146818rtc.h>
28 #include "root_complex/chip.h"
29 #include "northbridge.h"
33 #if K8_HW_MEM_HOLE_SIZEK != 0
34 #include <cpu/amd/model_fxx_rev.h>
38 static device_t __f0_dev[FX_DEVS];
39 static device_t __f1_dev[FX_DEVS];
42 static void debug_fx_devs(void)
45 for(i = 0; i < FX_DEVS; i++) {
49 printk_debug("__f0_dev[%d]: %s bus: %p\n",
50 i, dev_path(dev), dev->bus);
54 printk_debug("__f1_dev[%d]: %s bus: %p\n",
55 i, dev_path(dev), dev->bus);
61 static void get_fx_devs(void)
67 for(i = 0; i < FX_DEVS; i++) {
68 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
69 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
72 die("Cannot find 0:0x18.1\n");
76 static uint32_t f1_read_config32(unsigned reg)
79 return pci_read_config32(__f1_dev[0], reg);
82 static void f1_write_config32(unsigned reg, uint32_t value)
86 for(i = 0; i < FX_DEVS; i++) {
89 if (dev && dev->enabled) {
90 pci_write_config32(dev, reg, value);
95 static unsigned int amdk8_nodeid(device_t dev)
97 return (dev->path.u.pci.devfn >> 3) - 0x18;
100 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
103 printk_debug("%s amdk8_scan_chains max: %d starting...\n",
106 // I want to put sb chain in bus 0 can I?
110 uint32_t busses, config_busses;
111 unsigned free_reg, config_reg;
112 dev->link[link].cap = 0x80 + (link *0x20);
114 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
115 } while(link_type & ConnectionPending);
116 if (!(link_type & LinkConnected)) {
120 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
121 } while(!(link_type & InitComplete));
122 if (!(link_type & NonCoherent)) {
125 /* See if there is an available configuration space mapping
126 * register in function 1.
129 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
131 config = f1_read_config32(config_reg);
132 if (!free_reg && ((config & 3) == 0)) {
133 free_reg = config_reg;
136 if (((config & 3) == 3) &&
137 (((config >> 4) & 7) == nodeid) &&
138 (((config >> 8) & 3) == link)) {
142 if (free_reg && (config_reg > 0xec)) {
143 config_reg = free_reg;
145 /* If we can't find an available configuration space mapping
146 * register skip this bus
148 if (config_reg > 0xec) {
152 /* Set up the primary, secondary and subordinate bus numbers.
153 * We have no idea how many busses are behind this bridge yet,
154 * so we set the subordinate bus number to 0xff for the moment.
156 #if K8_SB_HT_CHAIN_ON_BUS0 == 1
157 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
158 dev->link[link].secondary = max;
162 dev->link[link].secondary = ++max;
164 dev->link[link].subordinate = 0xff;
166 /* Read the existing primary/secondary/subordinate bus
167 * number configuration.
169 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
170 config_busses = f1_read_config32(config_reg);
172 /* Configure the bus numbers for this bridge: the configuration
173 * transactions will not be propagates by the bridge if it is
174 * not correctly configured
176 busses &= 0xff000000;
177 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
178 ((unsigned int)(dev->link[link].secondary) << 8) |
179 ((unsigned int)(dev->link[link].subordinate) << 16));
180 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
182 config_busses &= 0x000fc88;
184 (3 << 0) | /* rw enable, no device compare */
185 (( nodeid & 7) << 4) |
186 (( link & 3 ) << 8) |
187 ((dev->link[link].secondary) << 16) |
188 ((dev->link[link].subordinate) << 24);
189 f1_write_config32(config_reg, config_busses);
192 printk_debug("%s Hyper transport scan link: %d max: %d\n",
193 dev_path(dev), link, max);
195 /* Now we can scan all of the subordinate busses i.e. the
196 * chain on the hypertranport link
198 max = hypertransport_scan_chain(&dev->link[link], 0, 0xbf, max, offset_unitid);
201 printk_debug("%s Hyper transport scan link: %d new max: %d\n",
202 dev_path(dev), link, max);
205 /* We know the number of busses behind this bridge. Set the
206 * subordinate bus number to it's real value
208 dev->link[link].subordinate = max;
209 busses = (busses & 0xff00ffff) |
210 ((unsigned int) (dev->link[link].subordinate) << 16);
211 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
213 config_busses = (config_busses & 0x00ffffff) |
214 (dev->link[link].subordinate << 24);
215 f1_write_config32(config_reg, config_busses);
218 printk_debug("%s Hypertransport scan link: %d done\n",
219 dev_path(dev), link);
225 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
230 unsigned offset_unitid = 0;
231 nodeid = amdk8_nodeid(dev);
235 printk_debug("%s amdk8_scan_chains max: %d starting...\n",
238 // I want to put sb chain in bus 0
241 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
242 #if K8_SB_HT_CHAIN_ON_BUS0 == 1
243 #if HT_CHAIN_UNITID_BASE != 1
246 max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
250 for(link = 0; link < dev->links; link++) {
251 #if K8_SB_HT_CHAIN_ON_BUS0 == 1
252 if( (nodeid == 0) && (sblink == link) ) continue; //already done
255 #if HT_CHAIN_UNITID_BASE != 1
256 #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
257 if((nodeid == 0) && (sblink == link))
262 max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
265 printk_debug("%s amdk8_scan_chains max: %d done\n",
272 static int reg_useable(unsigned reg,
273 device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
275 struct resource *res;
276 unsigned nodeid, link;
279 for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
281 dev = __f0_dev[nodeid];
282 for(link = 0; !res && (link < 3); link++) {
283 res = probe_resource(dev, 0x100 + (reg | link));
289 if ( (goal_link == (link - 1)) &&
290 (goal_nodeid == (nodeid - 1)) &&
296 printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
298 goal_nodeid, goal_link,
304 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
306 struct resource *resource;
307 unsigned free_reg, reg;
310 for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
312 result = reg_useable(reg, dev, nodeid, link);
314 /* I have been allocated this one */
317 else if (result > 1) {
318 /* I have a free register pair */
326 resource = new_resource(dev, 0x100 + (reg | link));
331 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
333 struct resource *resource;
334 unsigned free_reg, reg;
337 for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
339 result = reg_useable(reg, dev, nodeid, link);
341 /* I have been allocated this one */
344 else if (result > 1) {
345 /* I have a free register pair */
353 resource = new_resource(dev, 0x100 + (reg | link));
358 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
360 struct resource *resource;
362 /* Initialize the io space constraints on the current bus */
363 resource = amdk8_find_iopair(dev, nodeid, link);
367 resource->align = log2(HT_IO_HOST_ALIGN);
368 resource->gran = log2(HT_IO_HOST_ALIGN);
369 resource->limit = 0xffffUL;
370 resource->flags = IORESOURCE_IO;
371 compute_allocate_resource(&dev->link[link], resource,
372 IORESOURCE_IO, IORESOURCE_IO);
375 /* Initialize the prefetchable memory constraints on the current bus */
376 resource = amdk8_find_mempair(dev, nodeid, link);
380 resource->align = log2(HT_MEM_HOST_ALIGN);
381 resource->gran = log2(HT_MEM_HOST_ALIGN);
382 resource->limit = 0xffffffffffULL;
383 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
384 compute_allocate_resource(&dev->link[link], resource,
385 IORESOURCE_MEM | IORESOURCE_PREFETCH,
386 IORESOURCE_MEM | IORESOURCE_PREFETCH);
389 /* Initialize the memory constraints on the current bus */
390 resource = amdk8_find_mempair(dev, nodeid, link);
394 resource->align = log2(HT_MEM_HOST_ALIGN);
395 resource->gran = log2(HT_MEM_HOST_ALIGN);
396 resource->limit = 0xffffffffffULL;
397 resource->flags = IORESOURCE_MEM;
398 compute_allocate_resource(&dev->link[link], resource,
399 IORESOURCE_MEM | IORESOURCE_PREFETCH,
404 static void amdk8_read_resources(device_t dev)
406 unsigned nodeid, link;
407 nodeid = amdk8_nodeid(dev);
408 for(link = 0; link < dev->links; link++) {
409 if (dev->link[link].children) {
410 amdk8_link_read_bases(dev, nodeid, link);
415 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
417 resource_t rbase, rend;
421 /* Make certain the resource has actually been set */
422 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
426 /* If I have already stored this resource don't worry about it */
427 if (resource->flags & IORESOURCE_STORED) {
431 /* Only handle PCI memory and IO resources */
432 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
435 /* Ensure I am actually looking at a resource of function 1 */
436 if (resource->index < 0x100) {
439 /* Get the base address */
440 rbase = resource->base;
442 /* Get the limit (rounded up) */
443 rend = resource_end(resource);
445 /* Get the register and link */
446 reg = resource->index & 0xfc;
447 link = resource->index & 3;
449 if (resource->flags & IORESOURCE_IO) {
450 uint32_t base, limit;
451 compute_allocate_resource(&dev->link[link], resource,
452 IORESOURCE_IO, IORESOURCE_IO);
453 base = f1_read_config32(reg);
454 limit = f1_read_config32(reg + 0x4);
456 base |= rbase & 0x01fff000;
459 limit |= rend & 0x01fff000;
460 limit |= (link & 3) << 4;
461 limit |= (nodeid & 7);
463 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
464 printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
465 __func__, dev_path(dev), link);
466 base |= PCI_IO_BASE_VGA_EN;
468 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
469 base |= PCI_IO_BASE_NO_ISA;
472 f1_write_config32(reg + 0x4, limit);
473 f1_write_config32(reg, base);
475 else if (resource->flags & IORESOURCE_MEM) {
476 uint32_t base, limit;
477 compute_allocate_resource(&dev->link[link], resource,
478 IORESOURCE_MEM | IORESOURCE_PREFETCH,
479 resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
480 base = f1_read_config32(reg);
481 limit = f1_read_config32(reg + 0x4);
483 base |= (rbase >> 8) & 0xffffff00;
486 limit |= (rend >> 8) & 0xffffff00;
487 limit |= (link & 3) << 4;
488 limit |= (nodeid & 7);
489 f1_write_config32(reg + 0x4, limit);
490 f1_write_config32(reg, base);
492 resource->flags |= IORESOURCE_STORED;
493 sprintf(buf, " <node %d link %d>",
495 report_resource_stored(dev, resource, buf);
500 * I tried to reuse the resource allocation code in amdk8_set_resource()
501 * but it is too diffcult to deal with the resource allocation magic.
503 #if CONFIG_CONSOLE_VGA_MULTI == 1
504 extern device_t vga_pri; // the primary vga device, defined in device.c
507 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
509 struct resource *resource;
511 uint32_t base, limit;
514 /* find out which link the VGA card is connected,
515 * we only deal with the 'first' vga card */
516 for (link = 0; link < dev->links; link++) {
517 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
518 #if CONFIG_CONSOLE_VGA_MULTI == 1
519 printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
520 dev->link[link].secondary,dev->link[link].subordinate);
521 /* We need to make sure the vga_pri is under the link */
522 if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
523 (vga_pri->bus->secondary <= dev->link[link].subordinate )
530 /* no VGA card installed */
531 if (link == dev->links)
534 printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
536 /* allocate a temp resrouce for legacy VGA buffer */
537 resource = amdk8_find_mempair(dev, nodeid, link);
539 printk_debug("VGA: Can not find free mmio reg for legacy VGA buffer\n");
542 resource->base = 0xa0000;
543 resource->size = 0x20000;
545 /* write the resource to the hardware */
546 reg = resource->index & 0xfc;
547 base = f1_read_config32(reg);
548 limit = f1_read_config32(reg + 0x4);
550 base |= (resource->base >> 8) & 0xffffff00;
553 limit |= ((resource->base + resource->size) >> 8) & 0xffffff00;
554 limit |= (resource->index & 3) << 4;
555 limit |= (nodeid & 7);
556 f1_write_config32(reg + 0x4, limit);
557 f1_write_config32(reg, base);
559 /* release the temp resource */
563 static void amdk8_set_resources(device_t dev)
565 unsigned nodeid, link;
568 /* Find the nodeid */
569 nodeid = amdk8_nodeid(dev);
571 amdk8_create_vga_resource(dev, nodeid);
573 /* Set each resource we have found */
574 for(i = 0; i < dev->resources; i++) {
575 amdk8_set_resource(dev, &dev->resource[i], nodeid);
578 for(link = 0; link < dev->links; link++) {
580 bus = &dev->link[link];
582 assign_resources(bus);
587 static void amdk8_enable_resources(device_t dev)
589 pci_dev_enable_resources(dev);
590 enable_childrens_resources(dev);
593 static void mcf0_control_init(struct device *dev)
596 printk_debug("NB: Function 0 Misc Control.. ");
599 printk_debug("done.\n");
603 static struct device_operations northbridge_operations = {
604 .read_resources = amdk8_read_resources,
605 .set_resources = amdk8_set_resources,
606 .enable_resources = amdk8_enable_resources,
607 .init = mcf0_control_init,
608 .scan_bus = amdk8_scan_chains,
614 static struct pci_driver mcf0_driver __pci_driver = {
615 .ops = &northbridge_operations,
616 .vendor = PCI_VENDOR_ID_AMD,
620 #if CONFIG_CHIP_NAME == 1
622 struct chip_operations northbridge_amd_amdk8_ops = {
623 CHIP_NAME("AMD K8 Northbridge")
629 static void pci_domain_read_resources(device_t dev)
631 struct resource *resource;
634 /* Find the already assigned resource pairs */
636 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
637 uint32_t base, limit;
638 base = f1_read_config32(reg);
639 limit = f1_read_config32(reg + 0x04);
640 /* Is this register allocated? */
641 if ((base & 3) != 0) {
642 unsigned nodeid, link;
645 link = (limit >> 4) & 3;
646 dev = __f0_dev[nodeid];
648 /* Reserve the resource */
649 struct resource *resource;
650 resource = new_resource(dev, 0x100 + (reg | link));
657 #if CONFIG_PCI_64BIT_PREF_MEM == 0
658 /* Initialize the system wide io space constraints */
659 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
660 resource->base = 0x400;
661 resource->limit = 0xffffUL;
662 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
664 /* Initialize the system wide memory resources constraints */
665 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
666 resource->limit = 0xfcffffffffULL;
667 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
669 /* Initialize the system wide io space constraints */
670 resource = new_resource(dev, 0);
671 resource->base = 0x400;
672 resource->limit = 0xffffUL;
673 resource->flags = IORESOURCE_IO;
674 compute_allocate_resource(&dev->link[0], resource,
675 IORESOURCE_IO, IORESOURCE_IO);
677 /* Initialize the system wide prefetchable memory resources constraints */
678 resource = new_resource(dev, 1);
679 resource->limit = 0xfcffffffffULL;
680 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
681 compute_allocate_resource(&dev->link[0], resource,
682 IORESOURCE_MEM | IORESOURCE_PREFETCH,
683 IORESOURCE_MEM | IORESOURCE_PREFETCH);
685 /* Initialize the system wide memory resources constraints */
686 resource = new_resource(dev, 2);
687 resource->limit = 0xfcffffffffULL;
688 resource->flags = IORESOURCE_MEM;
689 compute_allocate_resource(&dev->link[0], resource,
690 IORESOURCE_MEM | IORESOURCE_PREFETCH,
695 static void ram_resource(device_t dev, unsigned long index,
696 unsigned long basek, unsigned long sizek)
698 struct resource *resource;
703 resource = new_resource(dev, index);
704 resource->base = ((resource_t)basek) << 10;
705 resource->size = ((resource_t)sizek) << 10;
706 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
707 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
710 static void tolm_test(void *gp, struct device *dev, struct resource *new)
712 struct resource **best_p = gp;
713 struct resource *best;
715 if (!best || (best->base > new->base)) {
721 static uint32_t find_pci_tolm(struct bus *bus)
723 struct resource *min;
726 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
728 if (min && tolm > min->base) {
734 #if CONFIG_PCI_64BIT_PREF_MEM == 1
735 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
738 #if K8_HW_MEM_HOLE_SIZEK != 0
740 struct hw_mem_hole_info {
741 unsigned hole_startk;
745 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
747 struct hw_mem_hole_info mem_hole;
750 mem_hole.hole_startk = K8_HW_MEM_HOLE_SIZEK;
751 mem_hole.node_id = -1;
753 for (i = 0; i < 8; i++) {
756 base = f1_read_config32(0x40 + (i << 3));
757 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
761 hole = pci_read_config32(__f1_dev[i], 0xf0);
762 if(hole & 1) { // we find the hole
763 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
764 mem_hole.node_id = i; // record the node No with hole
765 break; // only one hole
769 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
770 if(mem_hole.node_id!=-1) {
771 uint32_t limitk_pri = 0;
773 uint32_t base, limit;
774 unsigned base_k, limit_k;
775 base = f1_read_config32(0x40 + (i << 3));
776 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
780 base_k = (base & 0xffff0000) >> 2;
781 if(limitk_pri != base_k) { // we find the hole
782 mem_hole.hole_startk = limitk_pri;
783 mem_hole.node_id = i;
784 break; //only one hole
787 limit = f1_read_config32(0x44 + (i << 3));
788 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
789 limitk_pri = limit_k;
796 static void disable_hoist_memory(unsigned long hole_startk, int i)
800 uint32_t base, limit;
805 //1. find which node has hole
806 //2. change limit in that node.
807 //3. change base and limit in later node
808 //4. clear that node f0
810 //if there is not mem hole enabled, we need to change it's base instead
812 hole_sizek = (4*1024*1024) - hole_startk;
814 for(ii=7;ii>i;ii--) {
816 base = f1_read_config32(0x40 + (ii << 3));
817 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
820 limit = f1_read_config32(0x44 + (ii << 3));
821 f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
822 f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
824 limit = f1_read_config32(0x44 + (i << 3));
825 f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
827 hoist = pci_read_config32(dev, 0xf0);
829 pci_write_config32(dev, 0xf0, 0);
832 base = pci_read_config32(dev, 0x40 + (i << 3));
833 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
838 static uint32_t hoist_memory(unsigned long hole_startk, int i)
843 uint32_t base, limit;
847 carry_over = (4*1024*1024) - hole_startk;
849 for(ii=7;ii>i;ii--) {
851 base = f1_read_config32(0x40 + (ii << 3));
852 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
855 limit = f1_read_config32(0x44 + (ii << 3));
856 f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
857 f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
859 limit = f1_read_config32(0x44 + (i << 3));
860 f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
862 base = pci_read_config32(dev, 0x40 + (i << 3));
863 basek = (base & 0xffff0000) >> 2;
864 if(basek == hole_startk) {
865 //don't need set memhole here, because hole off set will be 0, overflow
866 //so need to change base reg instead, new basek will be 4*1024*1024
868 base |= (4*1024*1024)<<2;
869 f1_write_config32(0x40 + (i<<3), base);
873 hoist = /* hole start address */
874 ((hole_startk << 10) & 0xff000000) +
875 /* hole address to memory controller address */
876 (((basek + carry_over) >> 6) & 0x0000ff00) +
880 pci_write_config32(dev, 0xf0, hoist);
887 static void pci_domain_set_resources(device_t dev)
889 #if CONFIG_PCI_64BIT_PREF_MEM == 1
890 struct resource *io, *mem1, *mem2;
891 struct resource *resource, *last;
893 unsigned long mmio_basek;
896 #if K8_HW_MEM_HOLE_SIZEK != 0
897 struct hw_mem_hole_info mem_hole;
898 unsigned reset_memhole = 1;
902 /* Place the IO devices somewhere safe */
903 io = find_resource(dev, 0);
904 io->base = DEVICE_IO_START;
906 #if CONFIG_PCI_64BIT_PREF_MEM == 1
907 /* Now reallocate the pci resources memory with the
908 * highest addresses I can manage.
910 mem1 = find_resource(dev, 1);
911 mem2 = find_resource(dev, 2);
914 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
915 mem1->base, mem1->limit, mem1->size, mem1->align);
916 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
917 mem2->base, mem2->limit, mem2->size, mem2->align);
920 /* See if both resources have roughly the same limits */
921 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
922 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
924 /* If so place the one with the most stringent alignment first
926 if (mem2->align > mem1->align) {
927 struct resource *tmp;
932 /* Now place the memory as high up as it will go */
933 mem2->base = resource_max(mem2);
934 mem1->limit = mem2->base - 1;
935 mem1->base = resource_max(mem1);
938 /* Place the resources as high up as they will go */
939 mem2->base = resource_max(mem2);
940 mem1->base = resource_max(mem1);
944 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
945 mem1->base, mem1->limit, mem1->size, mem1->align);
946 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
947 mem2->base, mem2->limit, mem2->size, mem2->align);
950 last = &dev->resource[dev->resources];
951 for(resource = &dev->resource[0]; resource < last; resource++)
954 resource->flags |= IORESOURCE_ASSIGNED;
955 resource->flags &= ~IORESOURCE_STORED;
957 compute_allocate_resource(&dev->link[0], resource,
958 BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
960 resource->flags |= IORESOURCE_STORED;
961 report_resource_stored(dev, resource, "");
967 pci_tolm = find_pci_tolm(&dev->link[0]);
969 #warning "FIXME handle interleaved nodes"
970 mmio_basek = pci_tolm >> 10;
971 /* Round mmio_basek to something the processor can support */
972 mmio_basek &= ~((1 << 6) -1);
975 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
976 /* Round the mmio hold to 64M */
977 mmio_basek &= ~((64*1024) - 1);
980 #if K8_HW_MEM_HOLE_SIZEK != 0
981 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
982 * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
983 * otherwise We reset the hole to the mmio_basek
985 if (!is_cpu_pre_e0()) {
987 mem_hole = get_hw_mem_hole_info();
989 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
990 mmio_basek = mem_hole.hole_startk;
994 //mmio_basek = 3*1024*1024; // for debug to meet boundary
997 if(mem_hole.node_id!=-1) { // We need to select K8_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
998 // We need to reset our Mem Hole, because We want more big HOLE than we already set
999 //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
1000 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
1003 #if K8_HW_MEM_HOLE_SIZE_AUTO_INC == 1
1004 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
1006 for (i = 0; i < 8; i++) {
1009 base = f1_read_config32(0x40 + (i << 3));
1010 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1014 basek = (base & 0xffff0000) >> 2;
1015 if(mmio_basek == basek) {
1016 mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
1029 for(i = 0; i < 8; i++) {
1030 uint32_t base, limit;
1031 unsigned basek, limitk, sizek;
1032 base = f1_read_config32(0x40 + (i << 3));
1033 limit = f1_read_config32(0x44 + (i << 3));
1034 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1037 basek = (base & 0xffff0000) >> 2;
1038 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
1039 sizek = limitk - basek;
1041 /* see if we need a hole from 0xa0000 to 0xbffff */
1042 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
1043 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1045 basek = (8*64)+(16*16);
1046 sizek = limitk - ((8*64)+(16*16));
1051 // printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1053 /* See if I need to split the region to accomodate pci memory space */
1054 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1055 if (basek <= mmio_basek) {
1057 pre_sizek = mmio_basek - basek;
1059 ram_resource(dev, (idx | i), basek, pre_sizek);
1063 #if K8_HW_MEM_HOLE_SIZEK != 0
1065 if(!is_cpu_pre_e0() )
1066 sizek += hoist_memory(mmio_basek,i);
1071 if ((basek + sizek) <= 4*1024*1024) {
1075 basek = 4*1024*1024;
1076 sizek -= (4*1024*1024 - mmio_basek);
1079 ram_resource(dev, (idx | i), basek, sizek);
1082 assign_resources(&dev->link[0]);
1085 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1089 /* Unmap all of the HT chains */
1090 for(reg = 0xe0; reg <= 0xec; reg += 4) {
1091 f1_write_config32(reg, 0);
1093 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
1095 /* Tune the hypertransport transaction for best performance.
1096 * Including enabling relaxed ordering if it is safe.
1099 for(i = 0; i < FX_DEVS; i++) {
1101 f0_dev = __f0_dev[i];
1102 if (f0_dev && f0_dev->enabled) {
1105 httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1106 httc &= ~HTTC_RSP_PASS_PW;
1107 if (!dev->link[0].disable_relaxed_ordering) {
1108 httc |= HTTC_RSP_PASS_PW;
1110 printk_spew("%s passpw: %s\n",
1112 (!dev->link[0].disable_relaxed_ordering)?
1113 "enabled":"disabled");
1114 pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1120 static struct device_operations pci_domain_ops = {
1121 .read_resources = pci_domain_read_resources,
1122 .set_resources = pci_domain_set_resources,
1123 .enable_resources = enable_childrens_resources,
1125 .scan_bus = pci_domain_scan_bus,
1126 .ops_pci_bus = &pci_cf8_conf1,
1129 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
1131 struct bus *cpu_bus;
1138 int enable_apic_ext_id;
1140 int e0_later_single_core;
1141 int disable_siblings;
1142 unsigned lift_bsp_apicid;
1145 enable_apic_ext_id = 0;
1146 lift_bsp_apicid = 0;
1149 /* Find the bootstrap processors apicid */
1150 bsp_apicid = lapicid();
1151 apicid_offset = bsp_apicid;
1153 disable_siblings = !CONFIG_LOGICAL_CPUS;
1154 #if CONFIG_LOGICAL_CPUS == 1
1155 get_option(&disable_siblings, "dual_core");
1158 // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
1159 // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
1161 nb_cfg_54 = read_nb_cfg_54();
1163 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1165 die("0:18.0 not found?");
1168 nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1170 if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1172 enable_apic_ext_id = 1;
1173 if(bsp_apicid == 0) {
1174 /* bsp apic id is not changed */
1175 apicid_offset = APIC_ID_OFFSET;
1178 lift_bsp_apicid = 1;
1183 /* Find which cpus are present */
1184 cpu_bus = &dev->link[0];
1185 for(i = 0; i < nodes; i++) {
1187 struct device_path cpu_path;
1189 /* Find the cpu's pci device */
1190 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1192 /* If I am probing things in a weird order
1193 * ensure all of the cpu's pci devices are found.
1197 for(j = 0; j <= 3; j++) {
1198 dev = pci_probe_dev(NULL, dev_mc->bus,
1199 PCI_DEVFN(0x18 + i, j));
1201 /* Ok, We need to set the links for that device.
1202 * otherwise the device under it will not be scanned
1204 dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1208 dev_f0->link[j].link = j;
1209 dev_f0->link[j].dev = dev_f0;
1215 e0_later_single_core = 0;
1216 if (dev && dev->enabled) {
1217 j = pci_read_config32(dev, 0xe8);
1218 j = (j >> 12) & 3; // dev is func 3
1219 printk_debug(" %s siblings=%d\r\n", dev_path(dev), j);
1222 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1223 // ----> you can mixed single core e0 and dual core e0 at any sequence
1224 // That is the typical case
1227 e0_later_single_core = is_e0_later_in_bsp(i); // single core
1229 e0_later_single_core = 0;
1231 if(e0_later_single_core) {
1232 printk_debug("\tFound Rev E or Rev F later single core\r\n");
1248 if(e0_later_single_core || disable_siblings) {
1255 jj = 0; // if create cpu core1 path in amd_siblings by core0
1258 for (j = 0; j <=jj; j++ ) {
1260 /* Build the cpu device path */
1261 cpu_path.type = DEVICE_PATH_APIC;
1262 cpu_path.u.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1264 /* See if I can find the cpu */
1265 cpu = find_dev_path(cpu_bus, &cpu_path);
1267 /* Enable the cpu if I have the processor */
1268 if (dev && dev->enabled) {
1270 cpu = alloc_dev(cpu_bus, &cpu_path);
1277 /* Disable the cpu if I don't have the processor */
1278 if (cpu && (!dev || !dev->enabled)) {
1282 /* Report what I have done */
1284 cpu->path.u.apic.node_id = i;
1285 cpu->path.u.apic.core_id = j;
1286 if(enable_apic_ext_id) {
1287 if(lift_bsp_apicid) {
1288 cpu->path.u.apic.apic_id += apicid_offset;
1291 if (cpu->path.u.apic.apic_id != 0)
1292 cpu->path.u.apic.apic_id += apicid_offset;
1295 printk_debug("CPU: %s %s\n",
1296 dev_path(cpu), cpu->enabled?"enabled":"disabled");
1304 static void cpu_bus_init(device_t dev)
1306 initialize_cpus(&dev->link[0]);
1309 static void cpu_bus_noop(device_t dev)
1313 static struct device_operations cpu_bus_ops = {
1314 .read_resources = cpu_bus_noop,
1315 .set_resources = cpu_bus_noop,
1316 .enable_resources = cpu_bus_noop,
1317 .init = cpu_bus_init,
1318 .scan_bus = cpu_bus_scan,
1321 static void root_complex_enable_dev(struct device *dev)
1323 /* Set the operations if it is a special bus type */
1324 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1325 dev->ops = &pci_domain_ops;
1327 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1328 dev->ops = &cpu_bus_ops;
1332 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1333 CHIP_NAME("AMD K8 Root Complex")
1334 .enable_dev = root_complex_enable_dev,