src/northbridge/amd/amdk8/northbridge.c

   1 /* This should be done by Eric
   2         2004.12 yhlu add dual core support
   3         2005.01 yhlu add support move apic before pci_domain in MB Config.lb
   4         2005.02 yhlu add e0 memory hole support
   5         2005.11 yhlu add put sb ht chain on bus 0
   6 */
   7
   8 #include <console/console.h>
   9 #include <arch/io.h>
  10 #include <stdint.h>
  11 #include <device/device.h>
  12 #include <device/pci.h>
  13 #include <device/pci_ids.h>
  14 #include <device/hypertransport.h>
  15 #include <stdlib.h>
  16 #include <string.h>
  17 #include <bitops.h>
  18 #include <cpu/cpu.h>
  19
  20 #include <cpu/x86/lapic.h>
  21
  22 #if CONFIG_LOGICAL_CPUS==1
  23 #include <cpu/amd/dualcore.h>
  24 #include <pc80/mc146818rtc.h>
  25 #endif
  26
  27 #include "chip.h"
  28 #include "root_complex/chip.h"
  29 #include "northbridge.h"
  30
  31 #include "amdk8.h"
  32
  33 #if HW_MEM_HOLE_SIZEK != 0
  34 #include <cpu/amd/model_fxx_rev.h>
  35 #endif
  36
  37 #include <cpu/amd/amdk8_sysconf.h>
  38
  39 struct amdk8_sysconf_t sysconf;
  40
  41 #define FX_DEVS 8
  42 static device_t __f0_dev[FX_DEVS];
  43 static device_t __f1_dev[FX_DEVS];
  44
  45 #if 0
  46 static void debug_fx_devs(void)
  47 {
  48         int i;
  49         for(i = 0; i < FX_DEVS; i++) {
  50                 device_t dev;
  51                 dev = __f0_dev[i];
  52                 if (dev) {
  53                         printk_debug("__f0_dev[%d]: %s bus: %p\n",
  54                                 i, dev_path(dev), dev->bus);
  55                 }
  56                 dev = __f1_dev[i];
  57                 if (dev) {
  58                         printk_debug("__f1_dev[%d]: %s bus: %p\n",
  59                                 i, dev_path(dev), dev->bus);
  60                 }
  61         }
  62 }
  63 #endif
  64
  65 static void get_fx_devs(void)
  66 {
  67         int i;
  68         if (__f1_dev[0]) {
  69                 return;
  70         }
  71         for(i = 0; i < FX_DEVS; i++) {
  72                 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
  73                 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
  74         }
  75         if (!__f1_dev[0]) {
  76                 die("Cannot find 0:0x18.1\n");
  77         }
  78 }
  79
  80 static uint32_t f1_read_config32(unsigned reg)
  81 {
  82         get_fx_devs();
  83         return pci_read_config32(__f1_dev[0], reg);
  84 }
  85
  86 static void f1_write_config32(unsigned reg, uint32_t value)
  87 {
  88         int i;
  89         get_fx_devs();
  90         for(i = 0; i < FX_DEVS; i++) {
  91                 device_t dev;
  92                 dev = __f1_dev[i];
  93                 if (dev && dev->enabled) {
  94                         pci_write_config32(dev, reg, value);
  95                 }
  96         }
  97 }
  98
  99 static unsigned int amdk8_nodeid(device_t dev)
 100 {
 101         return (dev->path.u.pci.devfn >> 3) - 0x18;
 102 }
 103
 104 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
 105 {
 106
 107                 uint32_t link_type;
 108                 int i;
 109                 uint32_t busses, config_busses;
 110                 unsigned free_reg, config_reg;
 111                 unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
 112                 unsigned max_bus;
 113                 unsigned min_bus;
 114                 unsigned max_devfn;
 115
 116                 dev->link[link].cap = 0x80 + (link *0x20);
 117                 do {
 118                         link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 119                 } while(link_type & ConnectionPending);
 120                 if (!(link_type & LinkConnected)) {
 121                         return max;
 122                 }
 123                 do {
 124                         link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 125                 } while(!(link_type & InitComplete));
 126                 if (!(link_type & NonCoherent)) {
 127                         return max;
 128                 }
 129                 /* See if there is an available configuration space mapping
 130                  * register in function 1.
 131                  */
 132                 free_reg = 0;
 133                 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
 134                         uint32_t config;
 135                         config = f1_read_config32(config_reg);
 136                         if (!free_reg && ((config & 3) == 0)) {
 137                                 free_reg = config_reg;
 138                                 continue;
 139                         }
 140                         if (((config & 3) == 3) &&
 141                                 (((config >> 4) & 7) == nodeid) &&
 142                                 (((config >> 8) & 3) == link)) {
 143                                 break;
 144                         }
 145                 }
 146                 if (free_reg && (config_reg > 0xec)) {
 147                         config_reg = free_reg;
 148                 }
 149                 /* If we can't find an available configuration space mapping
 150                  * register skip this bus
 151                  */
 152                 if (config_reg > 0xec) {
 153                         return max;
 154                 }
 155
 156                 /* Set up the primary, secondary and subordinate bus numbers.
 157                  * We have no idea how many busses are behind this bridge yet,
 158                  * so we set the subordinate bus number to 0xff for the moment.
 159                  */
 160 #if SB_HT_CHAIN_ON_BUS0 > 0
 161                 // first chain will on bus 0
 162                 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
 163                         min_bus = max;
 164                 }
 165         #if SB_HT_CHAIN_ON_BUS0 > 1
 166                 // second chain will be on 0x40, third 0x80, forth 0xc0
 167                 else {
 168                         min_bus = ((max>>6) + 1) * 0x40;
 169                 }
 170                 max = min_bus;
 171         #else
 172                 //other ...
 173                 else  {
 174                         min_bus = ++max;
 175                 }
 176         #endif
 177 #else
 178                 min_bus = ++max;
 179 #endif
 180                 max_bus = 0xff;
 181
 182                 dev->link[link].secondary = min_bus;
 183                 dev->link[link].subordinate = max_bus;
 184
 185                 /* Read the existing primary/secondary/subordinate bus
 186                  * number configuration.
 187                  */
 188                 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
 189                 config_busses = f1_read_config32(config_reg);
 190
 191                 /* Configure the bus numbers for this bridge: the configuration
 192                  * transactions will not be propagates by the bridge if it is
 193                  * not correctly configured
 194                  */
 195                 busses &= 0xff000000;
 196                 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
 197                         ((unsigned int)(dev->link[link].secondary) << 8) |
 198                         ((unsigned int)(dev->link[link].subordinate) << 16));
 199                 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 200
 201                 config_busses &= 0x000fc88;
 202                 config_busses |=
 203                         (3 << 0) |  /* rw enable, no device compare */
 204                         (( nodeid & 7) << 4) |
 205                         (( link & 3 ) << 8) |
 206                         ((dev->link[link].secondary) << 16) |
 207                         ((dev->link[link].subordinate) << 24);
 208                 f1_write_config32(config_reg, config_busses);
 209
 210                 /* Now we can scan all of the subordinate busses i.e. the
 211                  * chain on the hypertranport link
 212                  */
 213                 for(i=0;i<4;i++) {
 214                         ht_unitid_base[i] = 0x20;
 215                 }
 216
 217                 if (min_bus == 0)
 218                         max_devfn = (0x17<<3) | 7;
 219                 else
 220                         max_devfn = (0x1f<<3) | 7;
 221
 222                 max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
 223
 224                 /* We know the number of busses behind this bridge.  Set the
 225                  * subordinate bus number to it's real value
 226                  */
 227                 dev->link[link].subordinate = max;
 228                 busses = (busses & 0xff00ffff) |
 229                         ((unsigned int) (dev->link[link].subordinate) << 16);
 230                 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 231
 232                 config_busses = (config_busses & 0x00ffffff) |
 233                         (dev->link[link].subordinate << 24);
 234                 f1_write_config32(config_reg, config_busses);
 235
 236                 {
 237                         // config config_reg, and ht_unitid_base to update hcdn_reg;
 238                         int index;
 239                         unsigned temp = 0;
 240                         index = (config_reg-0xe0) >> 2;
 241                         for(i=0;i<4;i++) {
 242                                 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
 243                         }
 244
 245                         sysconf.hcdn_reg[index] = temp;
 246
 247                 }
 248
 249         return max;
 250 }
 251
 252 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
 253 {
 254         unsigned nodeid;
 255         unsigned link;
 256         unsigned sblink = 0;
 257         unsigned offset_unitid = 0;
 258         nodeid = amdk8_nodeid(dev);
 259
 260         if(nodeid==0) {
 261                 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
 262 #if SB_HT_CHAIN_ON_BUS0 > 0
 263         #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
 264                 offset_unitid = 1;
 265         #endif
 266                 max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
 267 #endif
 268         }
 269
 270         for(link = 0; link < dev->links; link++) {
 271 #if SB_HT_CHAIN_ON_BUS0 > 0
 272                 if( (nodeid == 0) && (sblink == link) ) continue; //already done
 273 #endif
 274                 offset_unitid = 0;
 275                 #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
 276                         #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 277                         if((nodeid == 0) && (sblink == link))
 278                         #endif
 279                                 offset_unitid = 1;
 280                 #endif
 281
 282                 max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
 283         }
 284
 285         return max;
 286 }
 287
 288
 289 static int reg_useable(unsigned reg,
 290         device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
 291 {
 292         struct resource *res;
 293         unsigned nodeid, link;
 294         int result;
 295         res = 0;
 296         for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
 297                 device_t dev;
 298                 dev = __f0_dev[nodeid];
 299                 for(link = 0; !res && (link < 3); link++) {
 300                         res = probe_resource(dev, 0x100 + (reg | link));
 301                 }
 302         }
 303         result = 2;
 304         if (res) {
 305                 result = 0;
 306                 if (    (goal_link == (link - 1)) &&
 307                         (goal_nodeid == (nodeid - 1)) &&
 308                         (res->flags <= 1)) {
 309                         result = 1;
 310                 }
 311         }
 312
 313         return result;
 314 }
 315
 316 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
 317 {
 318         struct resource *resource;
 319         unsigned free_reg, reg;
 320         resource = 0;
 321         free_reg = 0;
 322         for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
 323                 int result;
 324                 result = reg_useable(reg, dev, nodeid, link);
 325                 if (result == 1) {
 326                         /* I have been allocated this one */
 327                         break;
 328                 }
 329                 else if (result > 1) {
 330                         /* I have a free register pair */
 331                         free_reg = reg;
 332                 }
 333         }
 334         if (reg > 0xd8) {
 335                 reg = free_reg;
 336         }
 337         if (reg > 0) {
 338                 resource = new_resource(dev, 0x100 + (reg | link));
 339         }
 340         return resource;
 341 }
 342
 343 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
 344 {
 345         struct resource *resource;
 346         unsigned free_reg, reg;
 347         resource = 0;
 348         free_reg = 0;
 349         for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
 350                 int result;
 351                 result = reg_useable(reg, dev, nodeid, link);
 352                 if (result == 1) {
 353                         /* I have been allocated this one */
 354                         break;
 355                 }
 356                 else if (result > 1) {
 357                         /* I have a free register pair */
 358                         free_reg = reg;
 359                 }
 360         }
 361         if (reg > 0xb8) {
 362                 reg = free_reg;
 363         }
 364         if (reg > 0) {
 365                 resource = new_resource(dev, 0x100 + (reg | link));
 366         }
 367         return resource;
 368 }
 369
 370 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
 371 {
 372         struct resource *resource;
 373
 374         /* Initialize the io space constraints on the current bus */
 375         resource =  amdk8_find_iopair(dev, nodeid, link);
 376         if (resource) {
 377                 resource->base  = 0;
 378                 resource->size  = 0;
 379                 resource->align = log2(HT_IO_HOST_ALIGN);
 380                 resource->gran  = log2(HT_IO_HOST_ALIGN);
 381                 resource->limit = 0xffffUL;
 382                 resource->flags = IORESOURCE_IO;
 383                 compute_allocate_resource(&dev->link[link], resource,
 384                         IORESOURCE_IO, IORESOURCE_IO);
 385         }
 386
 387         /* Initialize the prefetchable memory constraints on the current bus */
 388         resource = amdk8_find_mempair(dev, nodeid, link);
 389         if (resource) {
 390                 resource->base  = 0;
 391                 resource->size  = 0;
 392                 resource->align = log2(HT_MEM_HOST_ALIGN);
 393                 resource->gran  = log2(HT_MEM_HOST_ALIGN);
 394                 resource->limit = 0xffffffffffULL;
 395                 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 396                 compute_allocate_resource(&dev->link[link], resource,
 397                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 398                         IORESOURCE_MEM | IORESOURCE_PREFETCH);
 399         }
 400
 401         /* Initialize the memory constraints on the current bus */
 402         resource = amdk8_find_mempair(dev, nodeid, link);
 403         if (resource) {
 404                 resource->base  = 0;
 405                 resource->size  = 0;
 406                 resource->align = log2(HT_MEM_HOST_ALIGN);
 407                 resource->gran  = log2(HT_MEM_HOST_ALIGN);
 408                 resource->limit = 0xffffffffffULL;
 409                 resource->flags = IORESOURCE_MEM;
 410                 compute_allocate_resource(&dev->link[link], resource,
 411                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 412                         IORESOURCE_MEM);
 413         }
 414 }
 415
 416 static void amdk8_read_resources(device_t dev)
 417 {
 418         unsigned nodeid, link;
 419         nodeid = amdk8_nodeid(dev);
 420         for(link = 0; link < dev->links; link++) {
 421                 if (dev->link[link].children) {
 422                         amdk8_link_read_bases(dev, nodeid, link);
 423                 }
 424         }
 425 }
 426
 427 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
 428 {
 429         resource_t rbase, rend;
 430         unsigned reg, link;
 431         char buf[50];
 432
 433         /* Make certain the resource has actually been set */
 434         if (!(resource->flags & IORESOURCE_ASSIGNED)) {
 435                 return;
 436         }
 437
 438         /* If I have already stored this resource don't worry about it */
 439         if (resource->flags & IORESOURCE_STORED) {
 440                 return;
 441         }
 442
 443         /* Only handle PCI memory and IO resources */
 444         if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 445                 return;
 446
 447         /* Ensure I am actually looking at a resource of function 1 */
 448         if (resource->index < 0x100) {
 449                 return;
 450         }
 451         /* Get the base address */
 452         rbase = resource->base;
 453
 454         /* Get the limit (rounded up) */
 455         rend  = resource_end(resource);
 456
 457         /* Get the register and link */
 458         reg  = resource->index & 0xfc;
 459         link = resource->index & 3;
 460
 461         if (resource->flags & IORESOURCE_IO) {
 462                 uint32_t base, limit;
 463                 compute_allocate_resource(&dev->link[link], resource,
 464                         IORESOURCE_IO, IORESOURCE_IO);
 465                 base  = f1_read_config32(reg);
 466                 limit = f1_read_config32(reg + 0x4);
 467                 base  &= 0xfe000fcc;
 468                 base  |= rbase  & 0x01fff000;
 469                 base  |= 3;
 470                 limit &= 0xfe000fc8;
 471                 limit |= rend & 0x01fff000;
 472                 limit |= (link & 3) << 4;
 473                 limit |= (nodeid & 7);
 474
 475                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 476                         printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
 477                                     __func__, dev_path(dev), link);
 478                         base |= PCI_IO_BASE_VGA_EN;
 479                 }
 480                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
 481                         base |= PCI_IO_BASE_NO_ISA;
 482                 }
 483
 484                 f1_write_config32(reg + 0x4, limit);
 485                 f1_write_config32(reg, base);
 486         }
 487         else if (resource->flags & IORESOURCE_MEM) {
 488                 uint32_t base, limit;
 489                 compute_allocate_resource(&dev->link[link], resource,
 490                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 491                         resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
 492                 base  = f1_read_config32(reg);
 493                 limit = f1_read_config32(reg + 0x4);
 494                 base  &= 0x000000f0;
 495                 base  |= (rbase >> 8) & 0xffffff00;
 496                 base  |= 3;
 497                 limit &= 0x00000048;
 498                 limit |= (rend >> 8) & 0xffffff00;
 499                 limit |= (link & 3) << 4;
 500                 limit |= (nodeid & 7);
 501                 f1_write_config32(reg + 0x4, limit);
 502                 f1_write_config32(reg, base);
 503         }
 504         resource->flags |= IORESOURCE_STORED;
 505         sprintf(buf, " <node %d link %d>",
 506                 nodeid, link);
 507         report_resource_stored(dev, resource, buf);
 508 }
 509
 510 /**
 511  *
 512  * I tried to reuse the resource allocation code in amdk8_set_resource()
 513  * but it is too diffcult to deal with the resource allocation magic.
 514  */
 515 #if CONFIG_CONSOLE_VGA_MULTI == 1
 516 extern device_t vga_pri;        // the primary vga device, defined in device.c
 517 #endif
 518
 519 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
 520 {
 521         struct resource *resource;
 522         unsigned link;
 523         uint32_t base, limit;
 524         unsigned reg;
 525
 526         /* find out which link the VGA card is connected,
 527          * we only deal with the 'first' vga card */
 528         for (link = 0; link < dev->links; link++) {
 529                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 530 #if CONFIG_CONSOLE_VGA_MULTI == 1
 531                         printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 532                                 dev->link[link].secondary,dev->link[link].subordinate);
 533                         /* We need to make sure the vga_pri is under the link */
 534                         if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
 535                                 (vga_pri->bus->secondary <= dev->link[link].subordinate )
 536                         )
 537 #endif
 538                         break;
 539                 }
 540         }
 541
 542         /* no VGA card installed */
 543         if (link == dev->links)
 544                 return;
 545
 546         printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 547
 548         /* allocate a temp resrouce for legacy VGA buffer */
 549         resource = amdk8_find_mempair(dev, nodeid, link);
 550         if(!resource){
 551                 printk_debug("VGA: Can not find free mmio reg for legacy VGA buffer\n");
 552                 return;
 553         }
 554         resource->base = 0xa0000;
 555         resource->size = 0x20000;
 556
 557         /* write the resource to the hardware */
 558         reg  = resource->index & 0xfc;
 559         base  = f1_read_config32(reg);
 560         limit = f1_read_config32(reg + 0x4);
 561         base  &= 0x000000f0;
 562         base  |= (resource->base >> 8) & 0xffffff00;
 563         base  |= 3;
 564         limit &= 0x00000048;
 565         limit |= (resource_end(resource) >> 8) & 0xffffff00;
 566         limit |= (resource->index & 3) << 4;
 567         limit |= (nodeid & 7);
 568         f1_write_config32(reg + 0x4, limit);
 569         f1_write_config32(reg, base);
 570
 571         /* release the temp resource */
 572         resource->flags = 0;
 573 }
 574
 575 static void amdk8_set_resources(device_t dev)
 576 {
 577         unsigned nodeid, link;
 578         int i;
 579
 580         /* Find the nodeid */
 581         nodeid = amdk8_nodeid(dev);
 582
 583         amdk8_create_vga_resource(dev, nodeid);
 584
 585         /* Set each resource we have found */
 586         for(i = 0; i < dev->resources; i++) {
 587                 amdk8_set_resource(dev, &dev->resource[i], nodeid);
 588         }
 589
 590         for(link = 0; link < dev->links; link++) {
 591                 struct bus *bus;
 592                 bus = &dev->link[link];
 593                 if (bus->children) {
 594                         assign_resources(bus);
 595                 }
 596         }
 597 }
 598
 599 static void amdk8_enable_resources(device_t dev)
 600 {
 601         pci_dev_enable_resources(dev);
 602         enable_childrens_resources(dev);
 603 }
 604
 605 static void mcf0_control_init(struct device *dev)
 606 {
 607 #if 0
 608         printk_debug("NB: Function 0 Misc Control.. ");
 609 #endif
 610 #if 0
 611         printk_debug("done.\n");
 612 #endif
 613 }
 614
 615 static struct device_operations northbridge_operations = {
 616         .read_resources   = amdk8_read_resources,
 617         .set_resources    = amdk8_set_resources,
 618         .enable_resources = amdk8_enable_resources,
 619         .init             = mcf0_control_init,
 620         .scan_bus         = amdk8_scan_chains,
 621         .enable           = 0,
 622         .ops_pci          = 0,
 623 };
 624
 625
 626 static struct pci_driver mcf0_driver __pci_driver = {
 627         .ops    = &northbridge_operations,
 628         .vendor = PCI_VENDOR_ID_AMD,
 629         .device = 0x1100,
 630 };
 631
 632 #if CONFIG_CHIP_NAME == 1
 633
 634 struct chip_operations northbridge_amd_amdk8_ops = {
 635         CHIP_NAME("AMD K8 Northbridge")
 636         .enable_dev = 0,
 637 };
 638
 639 #endif
 640
 641 static void pci_domain_read_resources(device_t dev)
 642 {
 643         struct resource *resource;
 644         unsigned reg;
 645
 646         /* Find the already assigned resource pairs */
 647         get_fx_devs();
 648         for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
 649                 uint32_t base, limit;
 650                 base  = f1_read_config32(reg);
 651                 limit = f1_read_config32(reg + 0x04);
 652                 /* Is this register allocated? */
 653                 if ((base & 3) != 0) {
 654                         unsigned nodeid, link;
 655                         device_t dev;
 656                         nodeid = limit & 7;
 657                         link   = (limit >> 4) & 3;
 658                         dev = __f0_dev[nodeid];
 659                         if (dev) {
 660                                 /* Reserve the resource  */
 661                                 struct resource *resource;
 662                                 resource = new_resource(dev, 0x100 + (reg | link));
 663                                 if (resource) {
 664                                         resource->flags = 1;
 665                                 }
 666                         }
 667                 }
 668         }
 669 #if CONFIG_PCI_64BIT_PREF_MEM == 0
 670         /* Initialize the system wide io space constraints */
 671         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 672         resource->base  = 0x400;
 673         resource->limit = 0xffffUL;
 674         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 675
 676         /* Initialize the system wide memory resources constraints */
 677         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 678         resource->limit = 0xfcffffffffULL;
 679         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 680 #else
 681         /* Initialize the system wide io space constraints */
 682         resource = new_resource(dev, 0);
 683         resource->base  = 0x400;
 684         resource->limit = 0xffffUL;
 685         resource->flags = IORESOURCE_IO;
 686         compute_allocate_resource(&dev->link[0], resource,
 687                 IORESOURCE_IO, IORESOURCE_IO);
 688
 689         /* Initialize the system wide prefetchable memory resources constraints */
 690         resource = new_resource(dev, 1);
 691         resource->limit = 0xfcffffffffULL;
 692         resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 693         compute_allocate_resource(&dev->link[0], resource,
 694                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 695                 IORESOURCE_MEM | IORESOURCE_PREFETCH);
 696
 697         /* Initialize the system wide memory resources constraints */
 698         resource = new_resource(dev, 2);
 699         resource->limit = 0xfcffffffffULL;
 700         resource->flags = IORESOURCE_MEM;
 701         compute_allocate_resource(&dev->link[0], resource,
 702                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 703                 IORESOURCE_MEM);
 704 #endif
 705 }
 706
 707 static void ram_resource(device_t dev, unsigned long index,
 708         unsigned long basek, unsigned long sizek)
 709 {
 710         struct resource *resource;
 711
 712         if (!sizek) {
 713                 return;
 714         }
 715         resource = new_resource(dev, index);
 716         resource->base  = ((resource_t)basek) << 10;
 717         resource->size  = ((resource_t)sizek) << 10;
 718         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 719                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 720 }
 721
 722 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 723 {
 724         struct resource **best_p = gp;
 725         struct resource *best;
 726         best = *best_p;
 727         if (!best || (best->base > new->base)) {
 728                 best = new;
 729         }
 730         *best_p = best;
 731 }
 732
 733 static uint32_t find_pci_tolm(struct bus *bus)
 734 {
 735         struct resource *min;
 736         uint32_t tolm;
 737         min = 0;
 738         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 739         tolm = 0xffffffffUL;
 740         if (min && tolm > min->base) {
 741                 tolm = min->base;
 742         }
 743         return tolm;
 744 }
 745
 746 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 747 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
 748 #endif
 749
 750 #if HW_MEM_HOLE_SIZEK != 0
 751
 752 struct hw_mem_hole_info {
 753         unsigned hole_startk;
 754         int node_id;
 755 };
 756
 757 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 758 {
 759                 struct hw_mem_hole_info mem_hole;
 760                 int i;
 761
 762                 mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
 763                 mem_hole.node_id = -1;
 764
 765                 for (i = 0; i < 8; i++) {
 766                         uint32_t base;
 767                         uint32_t hole;
 768                         base  = f1_read_config32(0x40 + (i << 3));
 769                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 770                                 continue;
 771                         }
 772
 773                         hole = pci_read_config32(__f1_dev[i], 0xf0);
 774                         if(hole & 1) { // we find the hole
 775                                 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
 776                                 mem_hole.node_id = i; // record the node No with hole
 777                                 break; // only one hole
 778                         }
 779                 }
 780
 781                 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
 782                 if(mem_hole.node_id==-1) {
 783                         uint32_t limitk_pri = 0;
 784                         for(i=0; i<8; i++) {
 785                                 uint32_t base, limit;
 786                                 unsigned base_k, limit_k;
 787                                 base  = f1_read_config32(0x40 + (i << 3));
 788                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 789                                         continue;
 790                                 }
 791
 792                                 base_k = (base & 0xffff0000) >> 2;
 793                                 if(limitk_pri != base_k) { // we find the hole
 794                                         mem_hole.hole_startk = limitk_pri;
 795                                         mem_hole.node_id = i;
 796                                         break; //only one hole
 797                                 }
 798
 799                                 limit = f1_read_config32(0x44 + (i << 3));
 800                                 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 801                                 limitk_pri = limit_k;
 802                         }
 803                 }
 804
 805                 return mem_hole;
 806
 807 }
 808 static void disable_hoist_memory(unsigned long hole_startk, int i)
 809 {
 810         int ii;
 811         device_t dev;
 812         uint32_t base, limit;
 813         uint32_t hoist;
 814         uint32_t hole_sizek;
 815
 816
 817         //1. find which node has hole
 818         //2. change limit in that node.
 819         //3. change base and limit in later node
 820         //4. clear that node f0
 821
 822         //if there is not mem hole enabled, we need to change it's base instead
 823
 824         hole_sizek = (4*1024*1024) - hole_startk;
 825
 826         for(ii=7;ii>i;ii--) {
 827
 828                 base  = f1_read_config32(0x40 + (ii << 3));
 829                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 830                         continue;
 831                 }
 832                 limit = f1_read_config32(0x44 + (ii << 3));
 833                 f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
 834                 f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
 835         }
 836         limit = f1_read_config32(0x44 + (i << 3));
 837         f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
 838         dev = __f1_dev[i];
 839         hoist = pci_read_config32(dev, 0xf0);
 840         if(hoist & 1) {
 841                 pci_write_config32(dev, 0xf0, 0);
 842         }
 843         else {
 844                 base = pci_read_config32(dev, 0x40 + (i << 3));
 845                 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
 846         }
 847
 848 }
 849
 850 static uint32_t hoist_memory(unsigned long hole_startk, int i)
 851 {
 852         int ii;
 853         uint32_t carry_over;
 854         device_t dev;
 855         uint32_t base, limit;
 856         uint32_t basek;
 857         uint32_t hoist;
 858
 859         carry_over = (4*1024*1024) - hole_startk;
 860
 861         for(ii=7;ii>i;ii--) {
 862
 863                 base  = f1_read_config32(0x40 + (ii << 3));
 864                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 865                         continue;
 866                 }
 867                 limit = f1_read_config32(0x44 + (ii << 3));
 868                 f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
 869                 f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
 870         }
 871         limit = f1_read_config32(0x44 + (i << 3));
 872         f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
 873         dev = __f1_dev[i];
 874         base  = pci_read_config32(dev, 0x40 + (i << 3));
 875         basek  = (base & 0xffff0000) >> 2;
 876         if(basek == hole_startk) {
 877                 //don't need set memhole here, because hole off set will be 0, overflow
 878                 //so need to change base reg instead, new basek will be 4*1024*1024
 879                 base &= 0x0000ffff;
 880                 base |= (4*1024*1024)<<2;
 881                 f1_write_config32(0x40 + (i<<3), base);
 882         }
 883         else
 884         {
 885                 hoist = /* hole start address */
 886                         ((hole_startk << 10) & 0xff000000) +
 887                         /* hole address to memory controller address */
 888                         (((basek + carry_over) >> 6) & 0x0000ff00) +
 889                         /* enable */
 890                         1;
 891
 892                 pci_write_config32(dev, 0xf0, hoist);
 893         }
 894
 895         return carry_over;
 896 }
 897 #endif
 898
 899 static void pci_domain_set_resources(device_t dev)
 900 {
 901 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 902         struct resource *io, *mem1, *mem2;
 903         struct resource *resource, *last;
 904 #endif
 905         unsigned long mmio_basek;
 906         uint32_t pci_tolm;
 907         int i, idx;
 908 #if HW_MEM_HOLE_SIZEK != 0
 909         struct hw_mem_hole_info mem_hole;
 910         unsigned reset_memhole = 1;
 911 #endif
 912
 913 #if 0
 914         /* Place the IO devices somewhere safe */
 915         io = find_resource(dev, 0);
 916         io->base = DEVICE_IO_START;
 917 #endif
 918 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 919         /* Now reallocate the pci resources memory with the
 920          * highest addresses I can manage.
 921          */
 922         mem1 = find_resource(dev, 1);
 923         mem2 = find_resource(dev, 2);
 924
 925 #if 1
 926                 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 927                         mem1->base, mem1->limit, mem1->size, mem1->align);
 928                 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 929                         mem2->base, mem2->limit, mem2->size, mem2->align);
 930 #endif
 931
 932         /* See if both resources have roughly the same limits */
 933         if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
 934                 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
 935         {
 936                 /* If so place the one with the most stringent alignment first
 937                  */
 938                 if (mem2->align > mem1->align) {
 939                         struct resource *tmp;
 940                         tmp = mem1;
 941                         mem1 = mem2;
 942                         mem2 = tmp;
 943                 }
 944                 /* Now place the memory as high up as it will go */
 945                 mem2->base = resource_max(mem2);
 946                 mem1->limit = mem2->base - 1;
 947                 mem1->base = resource_max(mem1);
 948         }
 949         else {
 950                 /* Place the resources as high up as they will go */
 951                 mem2->base = resource_max(mem2);
 952                 mem1->base = resource_max(mem1);
 953         }
 954
 955 #if 1
 956                 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 957                         mem1->base, mem1->limit, mem1->size, mem1->align);
 958                 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 959                         mem2->base, mem2->limit, mem2->size, mem2->align);
 960 #endif
 961
 962         last = &dev->resource[dev->resources];
 963         for(resource = &dev->resource[0]; resource < last; resource++)
 964         {
 965 #if 1
 966                 resource->flags |= IORESOURCE_ASSIGNED;
 967                 resource->flags &= ~IORESOURCE_STORED;
 968 #endif
 969                 compute_allocate_resource(&dev->link[0], resource,
 970                         BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
 971
 972                 resource->flags |= IORESOURCE_STORED;
 973                 report_resource_stored(dev, resource, "");
 974
 975         }
 976 #endif
 977
 978
 979         pci_tolm = find_pci_tolm(&dev->link[0]);
 980
 981 #warning "FIXME handle interleaved nodes"
 982         mmio_basek = pci_tolm >> 10;
 983         /* Round mmio_basek to something the processor can support */
 984         mmio_basek &= ~((1 << 6) -1);
 985
 986 #if 1
 987 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
 988         /* Round the mmio hold to 64M */
 989         mmio_basek &= ~((64*1024) - 1);
 990 #endif
 991
 992 #if HW_MEM_HOLE_SIZEK != 0
 993     /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
 994      * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
 995      * otherwise We reset the hole to the mmio_basek
 996      */
 997     #if K8_REV_F_SUPPORT == 0
 998         if (!is_cpu_pre_e0()) {
 999     #endif
1000
1001                 mem_hole = get_hw_mem_hole_info();
1002
1003                 if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
1004                         mmio_basek = mem_hole.hole_startk;
1005                         reset_memhole = 0;
1006                 }
1007
1008                 //mmio_basek = 3*1024*1024; // for debug to meet boundary
1009
1010                 if(reset_memhole) {
1011                         if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
1012                                // We need to reset our Mem Hole, because We want more big HOLE than we already set
1013                                //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
1014                                 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
1015                         }
1016
1017                 #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
1018                         //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
1019                         uint32_t basek_pri;
1020                         for (i = 0; i < 8; i++) {
1021                                 uint32_t base;
1022                                 uint32_t basek;
1023                                 base  = f1_read_config32(0x40 + (i << 3));
1024                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1025                                         continue;
1026                                 }
1027
1028                                 basek = (base & 0xffff0000) >> 2;
1029                                 if(mmio_basek == basek) {
1030                                         mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
1031                                         break;
1032                                 }
1033                                 basek_pri = basek;
1034                         }
1035                 #endif
1036                 }
1037
1038 #if K8_REV_F_SUPPORT == 0
1039         } // is_cpu_pre_e0
1040 #endif
1041
1042 #endif
1043
1044         idx = 0x10;
1045         for(i = 0; i < 8; i++) {
1046                 uint32_t base, limit;
1047                 unsigned basek, limitk, sizek;
1048                 base  = f1_read_config32(0x40 + (i << 3));
1049                 limit = f1_read_config32(0x44 + (i << 3));
1050                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1051                         continue;
1052                 }
1053                 basek = (base & 0xffff0000) >> 2;
1054                 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
1055                 sizek = limitk - basek;
1056
1057                 /* see if we need a hole from 0xa0000 to 0xbffff */
1058                 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
1059                         ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1060                         idx += 0x10;
1061                         basek = (8*64)+(16*16);
1062                         sizek = limitk - ((8*64)+(16*16));
1063
1064                 }
1065
1066
1067 //              printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1068
1069                 /* See if I need to split the region to accomodate pci memory space */
1070                 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1071                         if (basek <= mmio_basek) {
1072                                 unsigned pre_sizek;
1073                                 pre_sizek = mmio_basek - basek;
1074                                 if(pre_sizek>0) {
1075                                         ram_resource(dev, (idx | i), basek, pre_sizek);
1076                                         idx += 0x10;
1077                                         sizek -= pre_sizek;
1078                                 }
1079                                 #if HW_MEM_HOLE_SIZEK != 0
1080                                 if(reset_memhole)
1081                                         #if K8_REV_F_SUPPORT == 0
1082                                         if(!is_cpu_pre_e0() )
1083                                         #endif
1084                                                  sizek += hoist_memory(mmio_basek,i);
1085                                 #endif
1086
1087                                 basek = mmio_basek;
1088                         }
1089                         if ((basek + sizek) <= 4*1024*1024) {
1090                                 sizek = 0;
1091                         }
1092                         else {
1093                                 basek = 4*1024*1024;
1094                                 sizek -= (4*1024*1024 - mmio_basek);
1095                         }
1096                 }
1097                 ram_resource(dev, (idx | i), basek, sizek);
1098                 idx += 0x10;
1099         }
1100         assign_resources(&dev->link[0]);
1101 }
1102
1103 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1104 {
1105         unsigned reg;
1106         int i;
1107         /* Unmap all of the HT chains */
1108         for(reg = 0xe0; reg <= 0xec; reg += 4) {
1109                 f1_write_config32(reg, 0);
1110         }
1111         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
1112
1113         /* Tune the hypertransport transaction for best performance.
1114          * Including enabling relaxed ordering if it is safe.
1115          */
1116         get_fx_devs();
1117         for(i = 0; i < FX_DEVS; i++) {
1118                 device_t f0_dev;
1119                 f0_dev = __f0_dev[i];
1120                 if (f0_dev && f0_dev->enabled) {
1121                         uint32_t httc;
1122                         httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1123                         httc &= ~HTTC_RSP_PASS_PW;
1124                         if (!dev->link[0].disable_relaxed_ordering) {
1125                                 httc |= HTTC_RSP_PASS_PW;
1126                         }
1127                         printk_spew("%s passpw: %s\n",
1128                                 dev_path(dev),
1129                                 (!dev->link[0].disable_relaxed_ordering)?
1130                                 "enabled":"disabled");
1131                         pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1132                 }
1133         }
1134         return max;
1135 }
1136
1137 static struct device_operations pci_domain_ops = {
1138         .read_resources   = pci_domain_read_resources,
1139         .set_resources    = pci_domain_set_resources,
1140         .enable_resources = enable_childrens_resources,
1141         .init             = 0,
1142         .scan_bus         = pci_domain_scan_bus,
1143         .ops_pci_bus      = &pci_cf8_conf1,
1144 };
1145
1146 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
1147 {
1148         struct bus *cpu_bus;
1149         device_t dev_mc;
1150         int bsp_apicid;
1151         int i,j;
1152         unsigned nb_cfg_54;
1153         unsigned siblings;
1154         int e0_later_single_core;
1155         int disable_siblings;
1156
1157         nb_cfg_54 = 0;
1158         sysconf.enabled_apic_ext_id = 0;
1159         sysconf.lift_bsp_apicid = 0;
1160         siblings = 0;
1161
1162         /* Find the bootstrap processors apicid */
1163         bsp_apicid = lapicid();
1164         sysconf.apicid_offset = bsp_apicid;
1165
1166         disable_siblings = !CONFIG_LOGICAL_CPUS;
1167 #if CONFIG_LOGICAL_CPUS == 1
1168         get_option(&disable_siblings, "dual_core");
1169 #endif
1170
1171         // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
1172         // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
1173
1174         nb_cfg_54 = read_nb_cfg_54();
1175
1176         dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1177         if (!dev_mc) {
1178                 die("0:18.0 not found?");
1179         }
1180
1181         sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1182
1183
1184         if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1185         {
1186                 sysconf.enabled_apic_ext_id = 1;
1187                 if(bsp_apicid == 0) {
1188                         /* bsp apic id is not changed */
1189                         sysconf.apicid_offset = APIC_ID_OFFSET;
1190                 } else
1191                 {
1192                         sysconf.lift_bsp_apicid = 1;
1193                 }
1194
1195         }
1196
1197         /* Find which cpus are present */
1198         cpu_bus = &dev->link[0];
1199         for(i = 0; i < sysconf.nodes; i++) {
1200                 device_t dev, cpu;
1201                 struct device_path cpu_path;
1202
1203                 /* Find the cpu's pci device */
1204                 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1205                 if (!dev) {
1206                         /* If I am probing things in a weird order
1207                          * ensure all of the cpu's pci devices are found.
1208                          */
1209                         int j;
1210                         device_t dev_f0;
1211                         for(j = 0; j <= 3; j++) {
1212                                 dev = pci_probe_dev(NULL, dev_mc->bus,
1213                                         PCI_DEVFN(0x18 + i, j));
1214                         }
1215                         /* Ok, We need to set the links for that device.
1216                          * otherwise the device under it will not be scanned
1217                          */
1218                         dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1219                         if(dev_f0) {
1220                                 dev_f0->links = 3;
1221                                 for(j=0;j<3;j++) {
1222                                         dev_f0->link[j].link = j;
1223                                         dev_f0->link[j].dev = dev_f0;
1224                                 }
1225                         }
1226
1227                 }
1228
1229                 e0_later_single_core = 0;
1230                 if (dev && dev->enabled) {
1231                         j = pci_read_config32(dev, 0xe8);
1232                         j = (j >> 12) & 3; // dev is func 3
1233                         printk_debug("  %s siblings=%d\n", dev_path(dev), j);
1234
1235                         if(nb_cfg_54) {
1236                                 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1237                                 //  ----> you can mixed single core e0 and dual core e0 at any sequence
1238                                 // That is the typical case
1239
1240                                 if(j == 0 ){
1241                                        #if K8_REV_F_SUPPORT == 0
1242                                         e0_later_single_core = is_e0_later_in_bsp(i);  // single core
1243                                        #else
1244                                         e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
1245                                        #endif
1246                                 } else {
1247                                        e0_later_single_core = 0;
1248                                 }
1249                                 if(e0_later_single_core) {
1250                                         printk_debug("\tFound Rev E or Rev F later single core\r\n");
1251
1252                                         j=1;
1253                                 }
1254
1255                                 if(siblings > j ) {
1256                                 }
1257                                 else {
1258                                         siblings = j;
1259                                 }
1260                         } else {
1261                                 siblings = j;
1262                         }
1263                 }
1264
1265                 unsigned jj;
1266                 if(e0_later_single_core || disable_siblings) {
1267                         jj = 0;
1268                 } else
1269                 {
1270                         jj = siblings;
1271                 }
1272 #if 0
1273                 jj = 0; // if create cpu core1 path in amd_siblings by core0
1274 #endif
1275
1276                 for (j = 0; j <=jj; j++ ) {
1277
1278                         /* Build the cpu device path */
1279                         cpu_path.type = DEVICE_PATH_APIC;
1280                         cpu_path.u.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1281
1282                         /* See if I can find the cpu */
1283                         cpu = find_dev_path(cpu_bus, &cpu_path);
1284
1285                         /* Enable the cpu if I have the processor */
1286                         if (dev && dev->enabled) {
1287                                 if (!cpu) {
1288                                         cpu = alloc_dev(cpu_bus, &cpu_path);
1289                                 }
1290                                 if (cpu) {
1291                                         cpu->enabled = 1;
1292                                 }
1293                         }
1294
1295                         /* Disable the cpu if I don't have the processor */
1296                         if (cpu && (!dev || !dev->enabled)) {
1297                                 cpu->enabled = 0;
1298                         }
1299
1300                         /* Report what I have done */
1301                         if (cpu) {
1302                                 cpu->path.u.apic.node_id = i;
1303                                 cpu->path.u.apic.core_id = j;
1304                                 if(sysconf.enabled_apic_ext_id) {
1305                                         if(sysconf.lift_bsp_apicid) {
1306                                                 cpu->path.u.apic.apic_id += sysconf.apicid_offset;
1307                                         } else
1308                                         {
1309                                                if (cpu->path.u.apic.apic_id != 0)
1310                                                        cpu->path.u.apic.apic_id += sysconf.apicid_offset;
1311                                         }
1312                                 }
1313                                 printk_debug("CPU: %s %s\n",
1314                                         dev_path(cpu), cpu->enabled?"enabled":"disabled");
1315                         }
1316
1317                 } //j
1318         }
1319         return max;
1320 }
1321
1322 static void cpu_bus_init(device_t dev)
1323 {
1324         initialize_cpus(&dev->link[0]);
1325 }
1326
1327 static void cpu_bus_noop(device_t dev)
1328 {
1329 }
1330
1331 static struct device_operations cpu_bus_ops = {
1332         .read_resources   = cpu_bus_noop,
1333         .set_resources    = cpu_bus_noop,
1334         .enable_resources = cpu_bus_noop,
1335         .init             = cpu_bus_init,
1336         .scan_bus         = cpu_bus_scan,
1337 };
1338
1339 static void root_complex_enable_dev(struct device *dev)
1340 {
1341         /* Set the operations if it is a special bus type */
1342         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1343                 dev->ops = &pci_domain_ops;
1344         }
1345         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1346                 dev->ops = &cpu_bus_ops;
1347         }
1348 }
1349
1350 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1351         CHIP_NAME("AMD K8 Root Complex")
1352         .enable_dev = root_complex_enable_dev,
1353 };