src/northbridge/amd/amdk8/northbridge.c

   1 /* This should be done by Eric
   2         2004.12 yhlu add dual core support
   3         2005.01 yhlu add support move apic before pci_domain in MB Config.lb
   4         2005.02 yhlu add e0 memory hole support
   5         2005.11 yhlu add put sb ht chain on bus 0
   6 */
   7
   8 #include <console/console.h>
   9 #include <arch/io.h>
  10 #include <stdint.h>
  11 #include <device/device.h>
  12 #include <device/pci.h>
  13 #include <device/pci_ids.h>
  14 #include <device/hypertransport.h>
  15 #include <stdlib.h>
  16 #include <string.h>
  17 #include <bitops.h>
  18 #include <cpu/cpu.h>
  19
  20 #include <cpu/x86/lapic.h>
  21
  22 #if CONFIG_LOGICAL_CPUS==1
  23 #include <cpu/amd/dualcore.h>
  24 #include <pc80/mc146818rtc.h>
  25 #endif
  26
  27 #include "chip.h"
  28 #include "root_complex/chip.h"
  29 #include "northbridge.h"
  30
  31 #include "amdk8.h"
  32
  33 #if K8_HW_MEM_HOLE_SIZEK != 0
  34 #include <cpu/amd/model_fxx_rev.h>
  35 #endif
  36
  37 #define FX_DEVS 8
  38 static device_t __f0_dev[FX_DEVS];
  39 static device_t __f1_dev[FX_DEVS];
  40
  41 #if 0
  42 static void debug_fx_devs(void)
  43 {
  44         int i;
  45         for(i = 0; i < FX_DEVS; i++) {
  46                 device_t dev;
  47                 dev = __f0_dev[i];
  48                 if (dev) {
  49                         printk_debug("__f0_dev[%d]: %s bus: %p\n",
  50                                 i, dev_path(dev), dev->bus);
  51                 }
  52                 dev = __f1_dev[i];
  53                 if (dev) {
  54                         printk_debug("__f1_dev[%d]: %s bus: %p\n",
  55                                 i, dev_path(dev), dev->bus);
  56                 }
  57         }
  58 }
  59 #endif
  60
  61 static void get_fx_devs(void)
  62 {
  63         int i;
  64         if (__f1_dev[0]) {
  65                 return;
  66         }
  67         for(i = 0; i < FX_DEVS; i++) {
  68                 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
  69                 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
  70         }
  71         if (!__f1_dev[0]) {
  72                 die("Cannot find 0:0x18.1\n");
  73         }
  74 }
  75
  76 static uint32_t f1_read_config32(unsigned reg)
  77 {
  78         get_fx_devs();
  79         return pci_read_config32(__f1_dev[0], reg);
  80 }
  81
  82 static void f1_write_config32(unsigned reg, uint32_t value)
  83 {
  84         int i;
  85         get_fx_devs();
  86         for(i = 0; i < FX_DEVS; i++) {
  87                 device_t dev;
  88                 dev = __f1_dev[i];
  89                 if (dev && dev->enabled) {
  90                         pci_write_config32(dev, reg, value);
  91                 }
  92         }
  93 }
  94
  95 static unsigned int amdk8_nodeid(device_t dev)
  96 {
  97         return (dev->path.u.pci.devfn >> 3) - 0x18;
  98 }
  99
 100 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
 101 {
 102 #if 0
 103         printk_debug("%s amdk8_scan_chains max: %d starting...\n",
 104                 dev_path(dev), max);
 105 #endif
 106 //      I want to put sb chain in bus 0 can I?
 107
 108
 109                 uint32_t link_type;
 110                 uint32_t busses, config_busses;
 111                 unsigned free_reg, config_reg;
 112                 dev->link[link].cap = 0x80 + (link *0x20);
 113                 do {
 114                         link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 115                 } while(link_type & ConnectionPending);
 116                 if (!(link_type & LinkConnected)) {
 117                         return max;
 118                 }
 119                 do {
 120                         link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 121                 } while(!(link_type & InitComplete));
 122                 if (!(link_type & NonCoherent)) {
 123                         return max;
 124                 }
 125                 /* See if there is an available configuration space mapping
 126                  * register in function 1.
 127                  */
 128                 free_reg = 0;
 129                 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
 130                         uint32_t config;
 131                         config = f1_read_config32(config_reg);
 132                         if (!free_reg && ((config & 3) == 0)) {
 133                                 free_reg = config_reg;
 134                                 continue;
 135                         }
 136                         if (((config & 3) == 3) &&
 137                                 (((config >> 4) & 7) == nodeid) &&
 138                                 (((config >> 8) & 3) == link)) {
 139                                 break;
 140                         }
 141                 }
 142                 if (free_reg && (config_reg > 0xec)) {
 143                         config_reg = free_reg;
 144                 }
 145                 /* If we can't find an available configuration space mapping
 146                  * register skip this bus
 147                  */
 148                 if (config_reg > 0xec) {
 149                         return max;
 150                 }
 151
 152                 /* Set up the primary, secondary and subordinate bus numbers.
 153                  * We have no idea how many busses are behind this bridge yet,
 154                  * so we set the subordinate bus number to 0xff for the moment.
 155                  */
 156 #if K8_SB_HT_CHAIN_ON_BUS0 == 1
 157                 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
 158                         dev->link[link].secondary = max;
 159                 }
 160                 else
 161 #endif
 162                         dev->link[link].secondary = ++max;
 163
 164                 dev->link[link].subordinate = 0xff;
 165
 166                 /* Read the existing primary/secondary/subordinate bus
 167                  * number configuration.
 168                  */
 169                 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
 170                 config_busses = f1_read_config32(config_reg);
 171
 172                 /* Configure the bus numbers for this bridge: the configuration
 173                  * transactions will not be propagates by the bridge if it is
 174                  * not correctly configured
 175                  */
 176                 busses &= 0xff000000;
 177                 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
 178                         ((unsigned int)(dev->link[link].secondary) << 8) |
 179                         ((unsigned int)(dev->link[link].subordinate) << 16));
 180                 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 181
 182                 config_busses &= 0x000fc88;
 183                 config_busses |=
 184                         (3 << 0) |  /* rw enable, no device compare */
 185                         (( nodeid & 7) << 4) |
 186                         (( link & 3 ) << 8) |
 187                         ((dev->link[link].secondary) << 16) |
 188                         ((dev->link[link].subordinate) << 24);
 189                 f1_write_config32(config_reg, config_busses);
 190
 191 #if 0
 192                 printk_debug("%s Hyper transport scan link: %d max: %d\n",
 193                         dev_path(dev), link, max);
 194 #endif
 195                 /* Now we can scan all of the subordinate busses i.e. the
 196                  * chain on the hypertranport link
 197                  */
 198                 max = hypertransport_scan_chain(&dev->link[link], 0, 0xbf, max, offset_unitid);
 199
 200 #if 0
 201                 printk_debug("%s Hyper transport scan link: %d new max: %d\n",
 202                         dev_path(dev), link, max);
 203 #endif
 204
 205                 /* We know the number of busses behind this bridge.  Set the
 206                  * subordinate bus number to it's real value
 207                  */
 208                 dev->link[link].subordinate = max;
 209                 busses = (busses & 0xff00ffff) |
 210                         ((unsigned int) (dev->link[link].subordinate) << 16);
 211                 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 212
 213                 config_busses = (config_busses & 0x00ffffff) |
 214                         (dev->link[link].subordinate << 24);
 215                 f1_write_config32(config_reg, config_busses);
 216
 217 #if 0
 218                 printk_debug("%s Hypertransport scan link: %d done\n",
 219                         dev_path(dev), link);
 220 #endif
 221
 222         return max;
 223 }
 224
 225 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
 226 {
 227         unsigned nodeid;
 228         unsigned link;
 229         unsigned sblink = 0;
 230         unsigned offset_unitid = 0;
 231         nodeid = amdk8_nodeid(dev);
 232
 233
 234 #if 0
 235         printk_debug("%s amdk8_scan_chains max: %d starting...\n",
 236                 dev_path(dev), max);
 237 #endif
 238 //      I want to put sb chain in bus 0
 239
 240         if(nodeid==0) {
 241                 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
 242 #if K8_SB_HT_CHAIN_ON_BUS0 == 1
 243         #if HT_CHAIN_UNITID_BASE != 1
 244                 offset_unitid = 1;
 245         #endif
 246                 max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
 247 #endif
 248         }
 249
 250         for(link = 0; link < dev->links; link++) {
 251 #if K8_SB_HT_CHAIN_ON_BUS0 == 1
 252                 if( (nodeid == 0) && (sblink == link) ) continue; //already done
 253 #endif
 254                 offset_unitid = 0;
 255                 #if HT_CHAIN_UNITID_BASE != 1
 256                         #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 257                         if((nodeid == 0) && (sblink == link))
 258                         #endif
 259                                 offset_unitid = 1;
 260                 #endif
 261
 262                 max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
 263         }
 264 #if 0
 265         printk_debug("%s amdk8_scan_chains max: %d done\n",
 266                 dev_path(dev), max);
 267 #endif
 268         return max;
 269 }
 270
 271
 272 static int reg_useable(unsigned reg,
 273         device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
 274 {
 275         struct resource *res;
 276         unsigned nodeid, link;
 277         int result;
 278         res = 0;
 279         for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
 280                 device_t dev;
 281                 dev = __f0_dev[nodeid];
 282                 for(link = 0; !res && (link < 3); link++) {
 283                         res = probe_resource(dev, 0x100 + (reg | link));
 284                 }
 285         }
 286         result = 2;
 287         if (res) {
 288                 result = 0;
 289                 if (    (goal_link == (link - 1)) &&
 290                         (goal_nodeid == (nodeid - 1)) &&
 291                         (res->flags <= 1)) {
 292                         result = 1;
 293                 }
 294         }
 295 #if 0
 296         printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
 297                 reg, result,
 298                 goal_nodeid, goal_link,
 299                 nodeid, link);
 300 #endif
 301         return result;
 302 }
 303
 304 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
 305 {
 306         struct resource *resource;
 307         unsigned free_reg, reg;
 308         resource = 0;
 309         free_reg = 0;
 310         for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
 311                 int result;
 312                 result = reg_useable(reg, dev, nodeid, link);
 313                 if (result == 1) {
 314                         /* I have been allocated this one */
 315                         break;
 316                 }
 317                 else if (result > 1) {
 318                         /* I have a free register pair */
 319                         free_reg = reg;
 320                 }
 321         }
 322         if (reg > 0xd8) {
 323                 reg = free_reg;
 324         }
 325         if (reg > 0) {
 326                 resource = new_resource(dev, 0x100 + (reg | link));
 327         }
 328         return resource;
 329 }
 330
 331 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
 332 {
 333         struct resource *resource;
 334         unsigned free_reg, reg;
 335         resource = 0;
 336         free_reg = 0;
 337         for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
 338                 int result;
 339                 result = reg_useable(reg, dev, nodeid, link);
 340                 if (result == 1) {
 341                         /* I have been allocated this one */
 342                         break;
 343                 }
 344                 else if (result > 1) {
 345                         /* I have a free register pair */
 346                         free_reg = reg;
 347                 }
 348         }
 349         if (reg > 0xb8) {
 350                 reg = free_reg;
 351         }
 352         if (reg > 0) {
 353                 resource = new_resource(dev, 0x100 + (reg | link));
 354         }
 355         return resource;
 356 }
 357
 358 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
 359 {
 360         struct resource *resource;
 361
 362         /* Initialize the io space constraints on the current bus */
 363         resource =  amdk8_find_iopair(dev, nodeid, link);
 364         if (resource) {
 365                 resource->base  = 0;
 366                 resource->size  = 0;
 367                 resource->align = log2(HT_IO_HOST_ALIGN);
 368                 resource->gran  = log2(HT_IO_HOST_ALIGN);
 369                 resource->limit = 0xffffUL;
 370                 resource->flags = IORESOURCE_IO;
 371                 compute_allocate_resource(&dev->link[link], resource,
 372                         IORESOURCE_IO, IORESOURCE_IO);
 373         }
 374
 375         /* Initialize the prefetchable memory constraints on the current bus */
 376         resource = amdk8_find_mempair(dev, nodeid, link);
 377         if (resource) {
 378                 resource->base  = 0;
 379                 resource->size  = 0;
 380                 resource->align = log2(HT_MEM_HOST_ALIGN);
 381                 resource->gran  = log2(HT_MEM_HOST_ALIGN);
 382                 resource->limit = 0xffffffffffULL;
 383                 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 384                 compute_allocate_resource(&dev->link[link], resource,
 385                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 386                         IORESOURCE_MEM | IORESOURCE_PREFETCH);
 387         }
 388
 389         /* Initialize the memory constraints on the current bus */
 390         resource = amdk8_find_mempair(dev, nodeid, link);
 391         if (resource) {
 392                 resource->base  = 0;
 393                 resource->size  = 0;
 394                 resource->align = log2(HT_MEM_HOST_ALIGN);
 395                 resource->gran  = log2(HT_MEM_HOST_ALIGN);
 396                 resource->limit = 0xffffffffffULL;
 397                 resource->flags = IORESOURCE_MEM;
 398                 compute_allocate_resource(&dev->link[link], resource,
 399                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 400                         IORESOURCE_MEM);
 401         }
 402 }
 403
 404 static void amdk8_read_resources(device_t dev)
 405 {
 406         unsigned nodeid, link;
 407         nodeid = amdk8_nodeid(dev);
 408         for(link = 0; link < dev->links; link++) {
 409                 if (dev->link[link].children) {
 410                         amdk8_link_read_bases(dev, nodeid, link);
 411                 }
 412         }
 413 }
 414
 415 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
 416 {
 417         resource_t rbase, rend;
 418         unsigned reg, link;
 419         char buf[50];
 420
 421         /* Make certain the resource has actually been set */
 422         if (!(resource->flags & IORESOURCE_ASSIGNED)) {
 423                 return;
 424         }
 425
 426         /* If I have already stored this resource don't worry about it */
 427         if (resource->flags & IORESOURCE_STORED) {
 428                 return;
 429         }
 430
 431         /* Only handle PCI memory and IO resources */
 432         if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 433                 return;
 434
 435         /* Ensure I am actually looking at a resource of function 1 */
 436         if (resource->index < 0x100) {
 437                 return;
 438         }
 439         /* Get the base address */
 440         rbase = resource->base;
 441
 442         /* Get the limit (rounded up) */
 443         rend  = resource_end(resource);
 444
 445         /* Get the register and link */
 446         reg  = resource->index & 0xfc;
 447         link = resource->index & 3;
 448
 449         if (resource->flags & IORESOURCE_IO) {
 450                 uint32_t base, limit;
 451                 compute_allocate_resource(&dev->link[link], resource,
 452                         IORESOURCE_IO, IORESOURCE_IO);
 453                 base  = f1_read_config32(reg);
 454                 limit = f1_read_config32(reg + 0x4);
 455                 base  &= 0xfe000fcc;
 456                 base  |= rbase  & 0x01fff000;
 457                 base  |= 3;
 458                 limit &= 0xfe000fc8;
 459                 limit |= rend & 0x01fff000;
 460                 limit |= (link & 3) << 4;
 461                 limit |= (nodeid & 7);
 462
 463                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 464                         printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
 465                                     __func__, dev_path(dev), link);
 466                         base |= PCI_IO_BASE_VGA_EN;
 467                 }
 468                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
 469                         base |= PCI_IO_BASE_NO_ISA;
 470                 }
 471
 472                 f1_write_config32(reg + 0x4, limit);
 473                 f1_write_config32(reg, base);
 474         }
 475         else if (resource->flags & IORESOURCE_MEM) {
 476                 uint32_t base, limit;
 477                 compute_allocate_resource(&dev->link[link], resource,
 478                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 479                         resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
 480                 base  = f1_read_config32(reg);
 481                 limit = f1_read_config32(reg + 0x4);
 482                 base  &= 0x000000f0;
 483                 base  |= (rbase >> 8) & 0xffffff00;
 484                 base  |= 3;
 485                 limit &= 0x00000048;
 486                 limit |= (rend >> 8) & 0xffffff00;
 487                 limit |= (link & 3) << 4;
 488                 limit |= (nodeid & 7);
 489                 f1_write_config32(reg + 0x4, limit);
 490                 f1_write_config32(reg, base);
 491         }
 492         resource->flags |= IORESOURCE_STORED;
 493         sprintf(buf, " <node %d link %d>",
 494                 nodeid, link);
 495         report_resource_stored(dev, resource, buf);
 496 }
 497
 498 /**
 499  *
 500  * I tried to reuse the resource allocation code in amdk8_set_resource()
 501  * but it is too diffcult to deal with the resource allocation magic.
 502  */
 503 #if CONFIG_CONSOLE_VGA_MULTI == 1
 504 extern device_t vga_pri;        // the primary vga device, defined in device.c
 505 #endif
 506
 507 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
 508 {
 509         struct resource *resource;
 510         unsigned link;
 511         uint32_t base, limit;
 512         unsigned reg;
 513
 514         /* find out which link the VGA card is connected,
 515          * we only deal with the 'first' vga card */
 516         for (link = 0; link < dev->links; link++) {
 517                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 518 #if CONFIG_CONSOLE_VGA_MULTI == 1
 519                         printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 520                                 dev->link[link].secondary,dev->link[link].subordinate);
 521                         /* We need to make sure the vga_pri is under the link */
 522                         if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
 523                                 (vga_pri->bus->secondary <= dev->link[link].subordinate )
 524                         )
 525 #endif
 526                         break;
 527                 }
 528         }
 529
 530         /* no VGA card installed */
 531         if (link == dev->links)
 532                 return;
 533
 534         printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 535
 536         /* allocate a temp resrouce for legacy VGA buffer */
 537         resource = amdk8_find_mempair(dev, nodeid, link);
 538         if(!resource){
 539                 printk_debug("VGA: Can not find free mmio reg for legacy VGA buffer\n");
 540                 return;
 541         }
 542         resource->base = 0xa0000;
 543         resource->size = 0x20000;
 544
 545         /* write the resource to the hardware */
 546         reg  = resource->index & 0xfc;
 547         base  = f1_read_config32(reg);
 548         limit = f1_read_config32(reg + 0x4);
 549         base  &= 0x000000f0;
 550         base  |= (resource->base >> 8) & 0xffffff00;
 551         base  |= 3;
 552         limit &= 0x00000048;
 553         limit |= ((resource->base + resource->size) >> 8) & 0xffffff00;
 554         limit |= (resource->index & 3) << 4;
 555         limit |= (nodeid & 7);
 556         f1_write_config32(reg + 0x4, limit);
 557         f1_write_config32(reg, base);
 558
 559         /* release the temp resource */
 560         resource->flags = 0;
 561 }
 562
 563 static void amdk8_set_resources(device_t dev)
 564 {
 565         unsigned nodeid, link;
 566         int i;
 567
 568         /* Find the nodeid */
 569         nodeid = amdk8_nodeid(dev);
 570
 571         amdk8_create_vga_resource(dev, nodeid);
 572
 573         /* Set each resource we have found */
 574         for(i = 0; i < dev->resources; i++) {
 575                 amdk8_set_resource(dev, &dev->resource[i], nodeid);
 576         }
 577
 578         for(link = 0; link < dev->links; link++) {
 579                 struct bus *bus;
 580                 bus = &dev->link[link];
 581                 if (bus->children) {
 582                         assign_resources(bus);
 583                 }
 584         }
 585 }
 586
 587 static void amdk8_enable_resources(device_t dev)
 588 {
 589         pci_dev_enable_resources(dev);
 590         enable_childrens_resources(dev);
 591 }
 592
 593 static void mcf0_control_init(struct device *dev)
 594 {
 595 #if 0
 596         printk_debug("NB: Function 0 Misc Control.. ");
 597 #endif
 598 #if 0
 599         printk_debug("done.\n");
 600 #endif
 601 }
 602
 603 static struct device_operations northbridge_operations = {
 604         .read_resources   = amdk8_read_resources,
 605         .set_resources    = amdk8_set_resources,
 606         .enable_resources = amdk8_enable_resources,
 607         .init             = mcf0_control_init,
 608         .scan_bus         = amdk8_scan_chains,
 609         .enable           = 0,
 610         .ops_pci          = 0,
 611 };
 612
 613
 614 static struct pci_driver mcf0_driver __pci_driver = {
 615         .ops    = &northbridge_operations,
 616         .vendor = PCI_VENDOR_ID_AMD,
 617         .device = 0x1100,
 618 };
 619
 620 #if CONFIG_CHIP_NAME == 1
 621
 622 struct chip_operations northbridge_amd_amdk8_ops = {
 623         CHIP_NAME("AMD K8 Northbridge")
 624         .enable_dev = 0,
 625 };
 626
 627 #endif
 628
 629 static void pci_domain_read_resources(device_t dev)
 630 {
 631         struct resource *resource;
 632         unsigned reg;
 633
 634         /* Find the already assigned resource pairs */
 635         get_fx_devs();
 636         for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
 637                 uint32_t base, limit;
 638                 base  = f1_read_config32(reg);
 639                 limit = f1_read_config32(reg + 0x04);
 640                 /* Is this register allocated? */
 641                 if ((base & 3) != 0) {
 642                         unsigned nodeid, link;
 643                         device_t dev;
 644                         nodeid = limit & 7;
 645                         link   = (limit >> 4) & 3;
 646                         dev = __f0_dev[nodeid];
 647                         if (dev) {
 648                                 /* Reserve the resource  */
 649                                 struct resource *resource;
 650                                 resource = new_resource(dev, 0x100 + (reg | link));
 651                                 if (resource) {
 652                                         resource->flags = 1;
 653                                 }
 654                         }
 655                 }
 656         }
 657 #if CONFIG_PCI_64BIT_PREF_MEM == 0
 658         /* Initialize the system wide io space constraints */
 659         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 660         resource->base  = 0x400;
 661         resource->limit = 0xffffUL;
 662         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 663
 664         /* Initialize the system wide memory resources constraints */
 665         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 666         resource->limit = 0xfcffffffffULL;
 667         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 668 #else
 669         /* Initialize the system wide io space constraints */
 670         resource = new_resource(dev, 0);
 671         resource->base  = 0x400;
 672         resource->limit = 0xffffUL;
 673         resource->flags = IORESOURCE_IO;
 674         compute_allocate_resource(&dev->link[0], resource,
 675                 IORESOURCE_IO, IORESOURCE_IO);
 676
 677         /* Initialize the system wide prefetchable memory resources constraints */
 678         resource = new_resource(dev, 1);
 679         resource->limit = 0xfcffffffffULL;
 680         resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 681         compute_allocate_resource(&dev->link[0], resource,
 682                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 683                 IORESOURCE_MEM | IORESOURCE_PREFETCH);
 684
 685         /* Initialize the system wide memory resources constraints */
 686         resource = new_resource(dev, 2);
 687         resource->limit = 0xfcffffffffULL;
 688         resource->flags = IORESOURCE_MEM;
 689         compute_allocate_resource(&dev->link[0], resource,
 690                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 691                 IORESOURCE_MEM);
 692 #endif
 693 }
 694
 695 static void ram_resource(device_t dev, unsigned long index,
 696         unsigned long basek, unsigned long sizek)
 697 {
 698         struct resource *resource;
 699
 700         if (!sizek) {
 701                 return;
 702         }
 703         resource = new_resource(dev, index);
 704         resource->base  = ((resource_t)basek) << 10;
 705         resource->size  = ((resource_t)sizek) << 10;
 706         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 707                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 708 }
 709
 710 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 711 {
 712         struct resource **best_p = gp;
 713         struct resource *best;
 714         best = *best_p;
 715         if (!best || (best->base > new->base)) {
 716                 best = new;
 717         }
 718         *best_p = best;
 719 }
 720
 721 static uint32_t find_pci_tolm(struct bus *bus)
 722 {
 723         struct resource *min;
 724         uint32_t tolm;
 725         min = 0;
 726         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 727         tolm = 0xffffffffUL;
 728         if (min && tolm > min->base) {
 729                 tolm = min->base;
 730         }
 731         return tolm;
 732 }
 733
 734 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 735 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
 736 #endif
 737
 738 #if K8_HW_MEM_HOLE_SIZEK != 0
 739
 740 struct hw_mem_hole_info {
 741         unsigned hole_startk;
 742         int node_id;
 743 };
 744
 745 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 746 {
 747                 struct hw_mem_hole_info mem_hole;
 748                 int i;
 749
 750                 mem_hole.hole_startk = K8_HW_MEM_HOLE_SIZEK;
 751                 mem_hole.node_id = -1;
 752
 753                 for (i = 0; i < 8; i++) {
 754                         uint32_t base;
 755                         uint32_t hole;
 756                         base  = f1_read_config32(0x40 + (i << 3));
 757                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 758                                 continue;
 759                         }
 760
 761                         hole = pci_read_config32(__f1_dev[i], 0xf0);
 762                         if(hole & 1) { // we find the hole
 763                                 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
 764                                 mem_hole.node_id = i; // record the node No with hole
 765                                 break; // only one hole
 766                         }
 767                 }
 768
 769                 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
 770                 if(mem_hole.node_id!=-1) {
 771                         uint32_t limitk_pri = 0;
 772                         for(i=0; i<8; i++) {
 773                                 uint32_t base, limit;
 774                                 unsigned base_k, limit_k;
 775                                 base  = f1_read_config32(0x40 + (i << 3));
 776                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 777                                         continue;
 778                                 }
 779
 780                                 base_k = (base & 0xffff0000) >> 2;
 781                                 if(limitk_pri != base_k) { // we find the hole
 782                                         mem_hole.hole_startk = limitk_pri;
 783                                         mem_hole.node_id = i;
 784                                         break; //only one hole
 785                                 }
 786
 787                                 limit = f1_read_config32(0x44 + (i << 3));
 788                                 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 789                                 limitk_pri = limit_k;
 790                         }
 791                 }
 792
 793                 return mem_hole;
 794
 795 }
 796 static void disable_hoist_memory(unsigned long hole_startk, int i)
 797 {
 798         int ii;
 799         device_t dev;
 800         uint32_t base, limit;
 801         uint32_t hoist;
 802         uint32_t hole_sizek;
 803
 804
 805         //1. find which node has hole
 806         //2. change limit in that node.
 807         //3. change base and limit in later node
 808         //4. clear that node f0
 809
 810         //if there is not mem hole enabled, we need to change it's base instead
 811
 812         hole_sizek = (4*1024*1024) - hole_startk;
 813
 814         for(ii=7;ii>i;ii--) {
 815
 816                 base  = f1_read_config32(0x40 + (ii << 3));
 817                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 818                         continue;
 819                 }
 820                 limit = f1_read_config32(0x44 + (ii << 3));
 821                 f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
 822                 f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
 823         }
 824         limit = f1_read_config32(0x44 + (i << 3));
 825         f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
 826         dev = __f1_dev[i];
 827         hoist = pci_read_config32(dev, 0xf0);
 828         if(hoist & 1) {
 829                 pci_write_config32(dev, 0xf0, 0);
 830         }
 831         else {
 832                 base = pci_read_config32(dev, 0x40 + (i << 3));
 833                 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
 834         }
 835
 836 }
 837
 838 static uint32_t hoist_memory(unsigned long hole_startk, int i)
 839 {
 840         int ii;
 841         uint32_t carry_over;
 842         device_t dev;
 843         uint32_t base, limit;
 844         uint32_t basek;
 845         uint32_t hoist;
 846
 847         carry_over = (4*1024*1024) - hole_startk;
 848
 849         for(ii=7;ii>i;ii--) {
 850
 851                 base  = f1_read_config32(0x40 + (ii << 3));
 852                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 853                         continue;
 854                 }
 855                 limit = f1_read_config32(0x44 + (ii << 3));
 856                 f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
 857                 f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
 858         }
 859         limit = f1_read_config32(0x44 + (i << 3));
 860         f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
 861         dev = __f1_dev[i];
 862         base  = pci_read_config32(dev, 0x40 + (i << 3));
 863         basek  = (base & 0xffff0000) >> 2;
 864         if(basek == hole_startk) {
 865                 //don't need set memhole here, because hole off set will be 0, overflow
 866                 //so need to change base reg instead, new basek will be 4*1024*1024
 867                 base &= 0x0000ffff;
 868                 base |= (4*1024*1024)<<2;
 869                 f1_write_config32(0x40 + (i<<3), base);
 870         }
 871         else
 872         {
 873                 hoist = /* hole start address */
 874                         ((hole_startk << 10) & 0xff000000) +
 875                         /* hole address to memory controller address */
 876                         (((basek + carry_over) >> 6) & 0x0000ff00) +
 877                         /* enable */
 878                         1;
 879
 880                 pci_write_config32(dev, 0xf0, hoist);
 881         }
 882
 883         return carry_over;
 884 }
 885 #endif
 886
 887 static void pci_domain_set_resources(device_t dev)
 888 {
 889 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 890         struct resource *io, *mem1, *mem2;
 891         struct resource *resource, *last;
 892 #endif
 893         unsigned long mmio_basek;
 894         uint32_t pci_tolm;
 895         int i, idx;
 896 #if K8_HW_MEM_HOLE_SIZEK != 0
 897         struct hw_mem_hole_info mem_hole;
 898         unsigned reset_memhole = 1;
 899 #endif
 900
 901 #if 0
 902         /* Place the IO devices somewhere safe */
 903         io = find_resource(dev, 0);
 904         io->base = DEVICE_IO_START;
 905 #endif
 906 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 907         /* Now reallocate the pci resources memory with the
 908          * highest addresses I can manage.
 909          */
 910         mem1 = find_resource(dev, 1);
 911         mem2 = find_resource(dev, 2);
 912
 913 #if 1
 914                 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 915                         mem1->base, mem1->limit, mem1->size, mem1->align);
 916                 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 917                         mem2->base, mem2->limit, mem2->size, mem2->align);
 918 #endif
 919
 920         /* See if both resources have roughly the same limits */
 921         if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
 922                 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
 923         {
 924                 /* If so place the one with the most stringent alignment first
 925                  */
 926                 if (mem2->align > mem1->align) {
 927                         struct resource *tmp;
 928                         tmp = mem1;
 929                         mem1 = mem2;
 930                         mem2 = tmp;
 931                 }
 932                 /* Now place the memory as high up as it will go */
 933                 mem2->base = resource_max(mem2);
 934                 mem1->limit = mem2->base - 1;
 935                 mem1->base = resource_max(mem1);
 936         }
 937         else {
 938                 /* Place the resources as high up as they will go */
 939                 mem2->base = resource_max(mem2);
 940                 mem1->base = resource_max(mem1);
 941         }
 942
 943 #if 1
 944                 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 945                         mem1->base, mem1->limit, mem1->size, mem1->align);
 946                 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 947                         mem2->base, mem2->limit, mem2->size, mem2->align);
 948 #endif
 949
 950         last = &dev->resource[dev->resources];
 951         for(resource = &dev->resource[0]; resource < last; resource++)
 952         {
 953 #if 1
 954                 resource->flags |= IORESOURCE_ASSIGNED;
 955                 resource->flags &= ~IORESOURCE_STORED;
 956 #endif
 957                 compute_allocate_resource(&dev->link[0], resource,
 958                         BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
 959
 960                 resource->flags |= IORESOURCE_STORED;
 961                 report_resource_stored(dev, resource, "");
 962
 963         }
 964 #endif
 965
 966
 967         pci_tolm = find_pci_tolm(&dev->link[0]);
 968
 969 #warning "FIXME handle interleaved nodes"
 970         mmio_basek = pci_tolm >> 10;
 971         /* Round mmio_basek to something the processor can support */
 972         mmio_basek &= ~((1 << 6) -1);
 973
 974 #if 1
 975 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
 976         /* Round the mmio hold to 64M */
 977         mmio_basek &= ~((64*1024) - 1);
 978 #endif
 979
 980 #if K8_HW_MEM_HOLE_SIZEK != 0
 981     /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
 982      * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
 983      * otherwise We reset the hole to the mmio_basek
 984      */
 985         if (!is_cpu_pre_e0()) {
 986
 987                 mem_hole = get_hw_mem_hole_info();
 988
 989                 if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
 990                         mmio_basek = mem_hole.hole_startk;
 991                         reset_memhole = 0;
 992                 }
 993
 994                 //mmio_basek = 3*1024*1024; // for debug to meet boundary
 995
 996                 if(reset_memhole) {
 997                         if(mem_hole.node_id!=-1) { // We need to select K8_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
 998                                // We need to reset our Mem Hole, because We want more big HOLE than we already set
 999                                //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
1000                                 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
1001                         }
1002
1003                 #if K8_HW_MEM_HOLE_SIZE_AUTO_INC == 1
1004                         //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
1005                         uint32_t basek_pri;
1006                         for (i = 0; i < 8; i++) {
1007                                 uint32_t base;
1008                                 uint32_t basek;
1009                                 base  = f1_read_config32(0x40 + (i << 3));
1010                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1011                                         continue;
1012                                 }
1013
1014                                 basek = (base & 0xffff0000) >> 2;
1015                                 if(mmio_basek == basek) {
1016                                         mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
1017                                         break;
1018                                 }
1019                                 basek_pri = basek;
1020                         }
1021                 #endif
1022                 }
1023
1024         } // is_cpu_pre_e0
1025
1026 #endif
1027
1028         idx = 0x10;
1029         for(i = 0; i < 8; i++) {
1030                 uint32_t base, limit;
1031                 unsigned basek, limitk, sizek;
1032                 base  = f1_read_config32(0x40 + (i << 3));
1033                 limit = f1_read_config32(0x44 + (i << 3));
1034                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1035                         continue;
1036                 }
1037                 basek = (base & 0xffff0000) >> 2;
1038                 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
1039                 sizek = limitk - basek;
1040
1041                 /* see if we need a hole from 0xa0000 to 0xbffff */
1042                 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
1043                         ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1044                         idx += 0x10;
1045                         basek = (8*64)+(16*16);
1046                         sizek = limitk - ((8*64)+(16*16));
1047
1048                 }
1049
1050
1051 //              printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1052
1053                 /* See if I need to split the region to accomodate pci memory space */
1054                 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1055                         if (basek <= mmio_basek) {
1056                                 unsigned pre_sizek;
1057                                 pre_sizek = mmio_basek - basek;
1058                                 if(pre_sizek>0) {
1059                                         ram_resource(dev, (idx | i), basek, pre_sizek);
1060                                         idx += 0x10;
1061                                         sizek -= pre_sizek;
1062                                 }
1063                                 #if K8_HW_MEM_HOLE_SIZEK != 0
1064                                 if(reset_memhole)
1065                                         if(!is_cpu_pre_e0() )
1066                                                  sizek += hoist_memory(mmio_basek,i);
1067                                 #endif
1068
1069                                 basek = mmio_basek;
1070                         }
1071                         if ((basek + sizek) <= 4*1024*1024) {
1072                                 sizek = 0;
1073                         }
1074                         else {
1075                                 basek = 4*1024*1024;
1076                                 sizek -= (4*1024*1024 - mmio_basek);
1077                         }
1078                 }
1079                 ram_resource(dev, (idx | i), basek, sizek);
1080                 idx += 0x10;
1081         }
1082         assign_resources(&dev->link[0]);
1083 }
1084
1085 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1086 {
1087         unsigned reg;
1088         int i;
1089         /* Unmap all of the HT chains */
1090         for(reg = 0xe0; reg <= 0xec; reg += 4) {
1091                 f1_write_config32(reg, 0);
1092         }
1093         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
1094
1095         /* Tune the hypertransport transaction for best performance.
1096          * Including enabling relaxed ordering if it is safe.
1097          */
1098         get_fx_devs();
1099         for(i = 0; i < FX_DEVS; i++) {
1100                 device_t f0_dev;
1101                 f0_dev = __f0_dev[i];
1102                 if (f0_dev && f0_dev->enabled) {
1103                         uint32_t httc;
1104                         int j;
1105                         httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1106                         httc &= ~HTTC_RSP_PASS_PW;
1107                         if (!dev->link[0].disable_relaxed_ordering) {
1108                                 httc |= HTTC_RSP_PASS_PW;
1109                         }
1110                         printk_spew("%s passpw: %s\n",
1111                                 dev_path(dev),
1112                                 (!dev->link[0].disable_relaxed_ordering)?
1113                                 "enabled":"disabled");
1114                         pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1115                 }
1116         }
1117         return max;
1118 }
1119
1120 static struct device_operations pci_domain_ops = {
1121         .read_resources   = pci_domain_read_resources,
1122         .set_resources    = pci_domain_set_resources,
1123         .enable_resources = enable_childrens_resources,
1124         .init             = 0,
1125         .scan_bus         = pci_domain_scan_bus,
1126         .ops_pci_bus      = &pci_cf8_conf1,
1127 };
1128
1129 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
1130 {
1131         struct bus *cpu_bus;
1132         device_t dev_mc;
1133         int bsp_apicid;
1134         int apicid_offset;
1135         int i,j;
1136         int nodes;
1137         unsigned nb_cfg_54;
1138         int enable_apic_ext_id;
1139         unsigned siblings;
1140         int e0_later_single_core;
1141         int disable_siblings;
1142         unsigned lift_bsp_apicid;
1143
1144         nb_cfg_54 = 0;
1145         enable_apic_ext_id = 0;
1146         lift_bsp_apicid = 0;
1147         siblings = 0;
1148
1149         /* Find the bootstrap processors apicid */
1150         bsp_apicid = lapicid();
1151         apicid_offset = bsp_apicid;
1152
1153         disable_siblings = !CONFIG_LOGICAL_CPUS;
1154 #if CONFIG_LOGICAL_CPUS == 1
1155         get_option(&disable_siblings, "dual_core");
1156 #endif
1157
1158         // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
1159         // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
1160
1161         nb_cfg_54 = read_nb_cfg_54();
1162
1163         dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1164         if (!dev_mc) {
1165                 die("0:18.0 not found?");
1166         }
1167
1168         nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1169
1170         if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1171         {
1172                 enable_apic_ext_id = 1;
1173                 if(bsp_apicid == 0) {
1174                         /* bsp apic id is not changed */
1175                         apicid_offset = APIC_ID_OFFSET;
1176                 } else
1177                 {
1178                         lift_bsp_apicid = 1;
1179                 }
1180
1181         }
1182
1183         /* Find which cpus are present */
1184         cpu_bus = &dev->link[0];
1185         for(i = 0; i < nodes; i++) {
1186                 device_t dev, cpu;
1187                 struct device_path cpu_path;
1188
1189                 /* Find the cpu's pci device */
1190                 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1191                 if (!dev) {
1192                         /* If I am probing things in a weird order
1193                          * ensure all of the cpu's pci devices are found.
1194                          */
1195                         int j;
1196                         device_t dev_f0;
1197                         for(j = 0; j <= 3; j++) {
1198                                 dev = pci_probe_dev(NULL, dev_mc->bus,
1199                                         PCI_DEVFN(0x18 + i, j));
1200                         }
1201                         /* Ok, We need to set the links for that device.
1202                          * otherwise the device under it will not be scanned
1203                          */
1204                         dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1205                         if(dev_f0) {
1206                                 dev_f0->links = 3;
1207                                 for(j=0;j<3;j++) {
1208                                         dev_f0->link[j].link = j;
1209                                         dev_f0->link[j].dev = dev_f0;
1210                                 }
1211                         }
1212
1213                 }
1214
1215                 e0_later_single_core = 0;
1216                 if (dev && dev->enabled) {
1217                         j = pci_read_config32(dev, 0xe8);
1218                         j = (j >> 12) & 3; // dev is func 3
1219                         printk_debug("  %s siblings=%d\r\n", dev_path(dev), j);
1220
1221                         if(nb_cfg_54) {
1222                                 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1223                                 //  ----> you can mixed single core e0 and dual core e0 at any sequence
1224                                 // That is the typical case
1225
1226                                 if(j == 0 ){
1227                                         e0_later_single_core = is_e0_later_in_bsp(i);  // single core
1228                                 } else {
1229                                        e0_later_single_core = 0;
1230                                 }
1231                                 if(e0_later_single_core) {
1232                                         printk_debug("\tFound Rev E or Rev F later single core\r\n");
1233
1234                                         j=1;
1235                                 }
1236
1237                                 if(siblings > j ) {
1238                                 }
1239                                 else {
1240                                         siblings = j;
1241                                 }
1242                         } else {
1243                                 siblings = j;
1244                         }
1245                 }
1246
1247                 unsigned jj;
1248                 if(e0_later_single_core || disable_siblings) {
1249                         jj = 0;
1250                 } else
1251                 {
1252                         jj = siblings;
1253                 }
1254 #if 0
1255                 jj = 0; // if create cpu core1 path in amd_siblings by core0
1256 #endif
1257
1258                 for (j = 0; j <=jj; j++ ) {
1259
1260                         /* Build the cpu device path */
1261                         cpu_path.type = DEVICE_PATH_APIC;
1262                         cpu_path.u.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1263
1264                         /* See if I can find the cpu */
1265                         cpu = find_dev_path(cpu_bus, &cpu_path);
1266
1267                         /* Enable the cpu if I have the processor */
1268                         if (dev && dev->enabled) {
1269                                 if (!cpu) {
1270                                         cpu = alloc_dev(cpu_bus, &cpu_path);
1271                                 }
1272                                 if (cpu) {
1273                                         cpu->enabled = 1;
1274                                 }
1275                         }
1276
1277                         /* Disable the cpu if I don't have the processor */
1278                         if (cpu && (!dev || !dev->enabled)) {
1279                                 cpu->enabled = 0;
1280                         }
1281
1282                         /* Report what I have done */
1283                         if (cpu) {
1284                                 cpu->path.u.apic.node_id = i;
1285                                 cpu->path.u.apic.core_id = j;
1286                                 if(enable_apic_ext_id) {
1287                                         if(lift_bsp_apicid) {
1288                                                 cpu->path.u.apic.apic_id += apicid_offset;
1289                                         } else
1290                                         {
1291                                                if (cpu->path.u.apic.apic_id != 0)
1292                                                        cpu->path.u.apic.apic_id += apicid_offset;
1293                                         }
1294                                 }
1295                                 printk_debug("CPU: %s %s\n",
1296                                         dev_path(cpu), cpu->enabled?"enabled":"disabled");
1297                         }
1298
1299                 } //j
1300         }
1301         return max;
1302 }
1303
1304 static void cpu_bus_init(device_t dev)
1305 {
1306         initialize_cpus(&dev->link[0]);
1307 }
1308
1309 static void cpu_bus_noop(device_t dev)
1310 {
1311 }
1312
1313 static struct device_operations cpu_bus_ops = {
1314         .read_resources   = cpu_bus_noop,
1315         .set_resources    = cpu_bus_noop,
1316         .enable_resources = cpu_bus_noop,
1317         .init             = cpu_bus_init,
1318         .scan_bus         = cpu_bus_scan,
1319 };
1320
1321 static void root_complex_enable_dev(struct device *dev)
1322 {
1323         /* Set the operations if it is a special bus type */
1324         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1325                 dev->ops = &pci_domain_ops;
1326         }
1327         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1328                 dev->ops = &cpu_bus_ops;
1329         }
1330 }
1331
1332 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1333         CHIP_NAME("AMD K8 Root Complex")
1334         .enable_dev = root_complex_enable_dev,
1335 };