1 #include <console/console.h>
5 #include <part/sizeram.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/hypertransport.h>
9 #include <device/chip.h>
14 #include "northbridge.h"
17 struct mem_range *sizeram(void)
19 unsigned long mmio_basek;
20 static struct mem_range mem[10];
24 #warning "FIXME handle interleaved nodes"
25 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
27 printk_err("Cannot find PCI: 0:18.1\n");
30 mmio_basek = (dev_root.resource[1].base >> 10);
31 /* Round mmio_basek to something the processor can support */
32 mmio_basek &= ~((1 << 6) -1);
35 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
36 /* Round the mmio hold to 256M */
37 mmio_basek &= ~((256*1024) - 1);
41 printk_debug("mmio_base: %dKB\n", mmio_basek);
44 for(idx = i = 0; i < 8; i++) {
46 unsigned basek, limitk, sizek;
47 base = pci_read_config32(dev, 0x40 + (i<<3));
48 limit = pci_read_config32(dev, 0x44 + (i<<3));
49 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
52 basek = (base & 0xffff0000) >> 2;
53 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
54 sizek = limitk - basek;
56 ((mem[idx -1].basek + mem[idx - 1].sizek) == basek)) {
57 mem[idx -1].sizek += sizek;
60 mem[idx].basek = basek;
61 mem[idx].sizek = sizek;
65 /* see if we need a hole from 0xa0000 to 0xbffff */
66 if((mem[idx-1].basek < ((8*64)+(8*16))) &&
67 (mem[idx-1].sizek > ((8*64)+(16*16)))) {
68 mem[idx].basek = (8*64)+(16*16);
69 mem[idx].sizek = mem[idx-1].sizek - ((8*64)+(16*16));
70 mem[idx-1].sizek = ((8*64)+(8*16)) - mem[idx-1].basek;
74 /* See if I need to split the region to accomodate pci memory space */
75 if ((mem[idx - 1].basek <= mmio_basek) &&
76 ((mem[idx - 1].basek + mem[idx - 1].sizek) > mmio_basek)) {
77 if (mem[idx - 1].basek < mmio_basek) {
79 pre_sizek = mmio_basek - mem[idx - 1].basek;
80 mem[idx].basek = mmio_basek;
81 mem[idx].sizek = mem[idx - 1].sizek - pre_sizek;
82 mem[idx - 1].sizek = pre_sizek;
85 if ((mem[idx - 1].basek + mem[idx - 1].sizek) <= 4*1024*1024) {
89 mem[idx - 1].basek = 4*1024*1024;
90 mem[idx - 1].sizek -= (4*1024*1024 - mmio_basek);
95 for(i = 0; i < idx; i++) {
96 printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
97 i, mem[i].basek, i, mem[i].sizek);
100 while(idx < sizeof(mem)/sizeof(mem[0])) {
109 static device_t __f1_dev[F1_DEVS];
112 static void debug_f1_devs(void)
115 for(i = 0; i < F1_DEVS; i++) {
119 printk_debug("__f1_dev[%d]: %s bus: %p\n",
120 i, dev_path(dev), dev->bus);
126 static void get_f1_devs(void)
132 for(i = 0; i < F1_DEVS; i++) {
133 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
136 die("Cannot find 0:0x18.1\n");
140 static uint32_t f1_read_config32(unsigned reg)
143 return pci_read_config32(__f1_dev[0], reg);
146 static void f1_write_config32(unsigned reg, uint32_t value)
150 for(i = 0; i < F1_DEVS; i++) {
154 pci_write_config32(dev, reg, value);
159 static unsigned int amdk8_nodeid(device_t dev)
161 return (dev->path.u.pci.devfn >> 3) - 0x18;
165 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
169 nodeid = amdk8_nodeid(dev);
171 printk_debug("amdk8_scan_chains max: %d starting...\n", max);
173 for(link = 0; link < dev->links; link++) {
175 uint32_t busses, config_busses;
176 unsigned free_reg, config_reg;
177 dev->link[link].cap = 0x80 + (link *0x20);
179 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
180 } while(link_type & ConnectionPending);
181 if (!(link_type & LinkConnected)) {
185 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
186 } while(!(link_type & InitComplete));
187 if (!(link_type & NonCoherent)) {
190 /* See if there is an available configuration space mapping register in function 1. */
192 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
194 config = f1_read_config32(config_reg);
195 if (!free_reg && ((config & 3) == 0)) {
196 free_reg = config_reg;
199 if (((config & 3) == 3) &&
200 (((config >> 4) & 7) == nodeid) &&
201 (((config >> 8) & 3) == link)) {
205 if (free_reg && (config_reg > 0xec)) {
206 config_reg = free_reg;
208 /* If we can't find an available configuration space mapping register skip this bus */
209 if (config_reg > 0xec) {
213 /* Set up the primary, secondary and subordinate bus numbers. We have
214 * no idea how many busses are behind this bridge yet, so we set the subordinate
215 * bus number to 0xff for the moment.
217 dev->link[link].secondary = ++max;
218 dev->link[link].subordinate = 0xff;
220 /* Read the existing primary/secondary/subordinate bus
221 * number configuration.
223 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
224 config_busses = f1_read_config32(config_reg);
226 /* Configure the bus numbers for this bridge: the configuration
227 * transactions will not be propagates by the bridge if it is not
228 * correctly configured
230 busses &= 0xff000000;
231 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
232 ((unsigned int)(dev->link[link].secondary) << 8) |
233 ((unsigned int)(dev->link[link].subordinate) << 16));
234 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
236 config_busses &= 0x0000ffff;
237 config_busses |= ((dev->link[link].secondary) << 16) |
238 ((dev->link[link].subordinate) << 24);
239 f1_write_config32(config_reg, config_busses);
242 printk_debug("Hyper transport scan link: %d max: %d\n", link, max);
244 /* Now we can scan all of the subordinate busses i.e. the chain on the hypertranport link */
245 max = hypertransport_scan_chain(&dev->link[link], max);
248 printk_debug("Hyper transport scan link: %d new max: %d\n", link, max);
251 /* We know the number of busses behind this bridge. Set the subordinate
252 * bus number to it's real value
254 dev->link[link].subordinate = max;
255 busses = (busses & 0xff00ffff) |
256 ((unsigned int) (dev->link[link].subordinate) << 16);
257 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
259 config_busses &= 0x000fc88;
261 (3 << 0) | /* rw enable, no device compare */
262 (( nodeid & 7) << 4) |
263 (( link & 3 ) << 8) |
264 ((dev->link[link].secondary) << 16) |
265 ((dev->link[link].subordinate) << 24);
266 f1_write_config32(config_reg, config_busses);
268 printk_debug("Hypertransport scan link done\n");
272 printk_debug("amdk8_scan_chains max: %d done\n", max);
278 static unsigned amdk8_find_iopair(unsigned nodeid, unsigned link)
280 unsigned free_reg, reg;
283 for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
284 uint32_t base, limit;
285 base = f1_read_config32(reg);
286 limit = f1_read_config32(reg + 0x4);
287 /* Do I have a free register */
288 if (!free_reg && ((base & 3) == 0)) {
291 /* Do I have a match for this node and link? */
292 if (((base & 3) == 3) &&
293 ((limit & 3) == nodeid) &&
294 (((limit >> 4) & 3) == link)) {
298 /* If I didn't find an exact match return a free register */
302 /* Return an available I/O pair or 0 on failure */
306 static unsigned amdk8_find_mempair(unsigned nodeid, unsigned link)
308 unsigned free_reg, reg;
310 for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
311 uint32_t base, limit;
312 base = f1_read_config32(reg);
313 limit = f1_read_config32(reg + 0x4);
314 /* Do I have a free register */
315 if (!free_reg && ((base & 3) == 0)) {
318 /* Do I have a match for this node and link? */
319 if (((base & 3) == 3) &&
320 ((limit & 3) == nodeid) &&
321 (((limit >> 4) & 3) == link)) {
325 /* If I didn't find an exact match return a free register */
329 /* Return an available I/O pair or 0 on failure */
333 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
335 unsigned int reg = dev->resources;
338 /* Initialize the io space constraints on the current bus */
339 index = amdk8_find_iopair(nodeid, link);
341 dev->resource[reg].base = 0;
342 dev->resource[reg].size = 0;
343 dev->resource[reg].align = log2(HT_IO_HOST_ALIGN);
344 dev->resource[reg].gran = log2(HT_IO_HOST_ALIGN);
345 dev->resource[reg].limit = 0xffffUL;
346 dev->resource[reg].flags = IORESOURCE_IO;
347 dev->resource[reg].index = index | (link & 0x3);
348 compute_allocate_resource(&dev->link[link], &dev->resource[reg],
349 IORESOURCE_IO, IORESOURCE_IO);
353 /* Initialize the memory constraints on the current bus */
354 index = amdk8_find_mempair(nodeid, link);
356 dev->resource[reg].base = 0;
357 dev->resource[reg].size = 0;
358 dev->resource[reg].align = log2(HT_MEM_HOST_ALIGN);
359 dev->resource[reg].gran = log2(HT_MEM_HOST_ALIGN);
360 dev->resource[reg].limit = 0xffffffffUL;
361 dev->resource[reg].flags = IORESOURCE_MEM;
362 dev->resource[reg].index = index | (link & 0x3);
363 compute_allocate_resource(&dev->link[link], &dev->resource[reg],
364 IORESOURCE_MEM, IORESOURCE_MEM);
367 dev->resources = reg;
370 static void amdk8_read_resources(device_t dev)
372 unsigned nodeid, link;
373 nodeid = amdk8_nodeid(dev);
375 memset(&dev->resource, 0, sizeof(dev->resource));
376 for(link = 0; link < dev->links; link++) {
377 if (dev->link[link].children) {
378 amdk8_link_read_bases(dev, nodeid, link);
383 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
385 unsigned long rbase, rlimit;
387 /* Make certain the resource has actually been set */
388 if (!(resource->flags & IORESOURCE_SET)) {
392 /* Only handle PCI memory and IO resources */
393 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
396 /* Get the base address */
397 rbase = resource->base;
399 /* Get the limit (rounded up) */
400 rlimit = rbase + ((resource->size + resource->align - 1UL) & ~(resource->align -1)) - 1UL;
402 /* Get the register and link */
403 reg = resource->index & ~3;
404 link = resource->index & 3;
406 if (resource->flags & IORESOURCE_IO) {
407 uint32_t base, limit;
408 compute_allocate_resource(&dev->link[link], resource,
409 IORESOURCE_IO, IORESOURCE_IO);
410 base = f1_read_config32(reg);
411 limit = f1_read_config32(reg + 0x4);
413 base |= rbase & 0x01fff000;
416 limit |= rlimit & 0x01fff000;
417 limit |= (link & 3) << 4;
418 limit |= (nodeid & 3);
419 f1_write_config32(reg + 0x4, limit);
420 f1_write_config32(reg, base);
422 else if (resource->flags & IORESOURCE_MEM) {
423 uint32_t base, limit;
424 compute_allocate_resource(&dev->link[link], resource,
425 IORESOURCE_MEM, IORESOURCE_MEM);
426 base = f1_read_config32(reg);
427 limit = f1_read_config32(reg + 0x4);
429 base |= (rbase & 0xffff0000) >> 8;
432 limit |= (rlimit & 0xffff0000) >> 8;
433 limit |= (link & 3) << 4;
434 limit |= (nodeid & 3);
435 f1_write_config32(reg + 0x4, limit);
436 f1_write_config32(reg, base);
439 "%s %02x <- [0x%08lx - 0x%08lx] node %d link %d %s\n",
444 (resource->flags & IORESOURCE_IO)? "io": "mem");
447 static void amdk8_set_resources(device_t dev)
449 unsigned nodeid, link;
452 /* Find the nodeid */
453 nodeid = amdk8_nodeid(dev);
455 /* Set each resource we have found */
456 for(i = 0; i < dev->resources; i++) {
457 amdk8_set_resource(dev, &dev->resource[i], nodeid);
460 for(link = 0; link < dev->links; link++) {
462 bus = &dev->link[link];
464 assign_resources(bus);
469 unsigned int amdk8_scan_root_bus(device_t root, unsigned int max)
472 /* Unmap all of HT chains */
473 for(reg = 0xe0; reg <= 0xec; reg += 4) {
474 f1_write_config32(reg, 0);
476 max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
480 static struct device_operations northbridge_operations = {
481 .read_resources = amdk8_read_resources,
482 .set_resources = amdk8_set_resources,
483 .enable_resources = pci_dev_enable_resources,
485 .scan_bus = amdk8_scan_chains,
490 static void enumerate(struct chip *chip)
492 chip_enumerate(chip);
493 chip->dev->ops = &northbridge_operations;
496 struct chip_control northbridge_amd_amdk8_control = {
497 .name = "AMD K8 Northbridge",
498 .enumerate = enumerate,