src/northbridge/amd/amdk8/northbridge.c

   1 /* This should be done by Eric
   2         2004.12 yhlu add dual core support
   3         2005.01 yhlu add support move apic before pci_domain in MB Config.lb
   4         2005.02 yhlu add e0 memory hole support
   5         2005.11 yhlu add put sb ht chain on bus 0
   6 */
   7
   8 #include <console/console.h>
   9 #include <arch/io.h>
  10 #include <stdint.h>
  11 #include <device/device.h>
  12 #include <device/pci.h>
  13 #include <device/pci_ids.h>
  14 #include <device/hypertransport.h>
  15 #include <stdlib.h>
  16 #include <string.h>
  17 #include <bitops.h>
  18 #include <cpu/cpu.h>
  19
  20 #include <cpu/x86/lapic.h>
  21
  22 #include <cpu/amd/dualcore.h>
  23 #if CONFIG_LOGICAL_CPUS==1
  24 #include <pc80/mc146818rtc.h>
  25 #endif
  26
  27 #include "chip.h"
  28 #include "root_complex/chip.h"
  29 #include "northbridge.h"
  30
  31 #include "amdk8.h"
  32
  33 #include <cpu/amd/model_fxx_rev.h>
  34
  35 #include <cpu/amd/amdk8_sysconf.h>
  36
  37 struct amdk8_sysconf_t sysconf;
  38
  39 #define FX_DEVS 8
  40 static device_t __f0_dev[FX_DEVS];
  41 static device_t __f1_dev[FX_DEVS];
  42
  43 #if 0
  44 static void debug_fx_devs(void)
  45 {
  46         int i;
  47         for(i = 0; i < FX_DEVS; i++) {
  48                 device_t dev;
  49                 dev = __f0_dev[i];
  50                 if (dev) {
  51                         printk_debug("__f0_dev[%d]: %s bus: %p\n",
  52                                 i, dev_path(dev), dev->bus);
  53                 }
  54                 dev = __f1_dev[i];
  55                 if (dev) {
  56                         printk_debug("__f1_dev[%d]: %s bus: %p\n",
  57                                 i, dev_path(dev), dev->bus);
  58                 }
  59         }
  60 }
  61 #endif
  62
  63 static void get_fx_devs(void)
  64 {
  65         int i;
  66         if (__f1_dev[0]) {
  67                 return;
  68         }
  69         for(i = 0; i < FX_DEVS; i++) {
  70                 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
  71                 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
  72         }
  73         if (!__f1_dev[0]) {
  74                 die("Cannot find 0:0x18.1\n");
  75         }
  76 }
  77
  78 static uint32_t f1_read_config32(unsigned reg)
  79 {
  80         get_fx_devs();
  81         return pci_read_config32(__f1_dev[0], reg);
  82 }
  83
  84 static void f1_write_config32(unsigned reg, uint32_t value)
  85 {
  86         int i;
  87         get_fx_devs();
  88         for(i = 0; i < FX_DEVS; i++) {
  89                 device_t dev;
  90                 dev = __f1_dev[i];
  91                 if (dev && dev->enabled) {
  92                         pci_write_config32(dev, reg, value);
  93                 }
  94         }
  95 }
  96
  97 static unsigned int amdk8_nodeid(device_t dev)
  98 {
  99         return (dev->path.pci.devfn >> 3) - 0x18;
 100 }
 101
 102 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
 103 {
 104
 105                 uint32_t link_type;
 106                 int i;
 107                 uint32_t busses, config_busses;
 108                 unsigned free_reg, config_reg;
 109                 unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
 110                 unsigned max_bus;
 111                 unsigned min_bus;
 112                 unsigned max_devfn;
 113
 114                 dev->link[link].cap = 0x80 + (link *0x20);
 115                 do {
 116                         link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 117                 } while(link_type & ConnectionPending);
 118                 if (!(link_type & LinkConnected)) {
 119                         return max;
 120                 }
 121                 do {
 122                         link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 123                 } while(!(link_type & InitComplete));
 124                 if (!(link_type & NonCoherent)) {
 125                         return max;
 126                 }
 127                 /* See if there is an available configuration space mapping
 128                  * register in function 1.
 129                  */
 130                 free_reg = 0;
 131                 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
 132                         uint32_t config;
 133                         config = f1_read_config32(config_reg);
 134                         if (!free_reg && ((config & 3) == 0)) {
 135                                 free_reg = config_reg;
 136                                 continue;
 137                         }
 138                         if (((config & 3) == 3) &&
 139                                 (((config >> 4) & 7) == nodeid) &&
 140                                 (((config >> 8) & 3) == link)) {
 141                                 break;
 142                         }
 143                 }
 144                 if (free_reg && (config_reg > 0xec)) {
 145                         config_reg = free_reg;
 146                 }
 147                 /* If we can't find an available configuration space mapping
 148                  * register skip this bus
 149                  */
 150                 if (config_reg > 0xec) {
 151                         return max;
 152                 }
 153
 154                 /* Set up the primary, secondary and subordinate bus numbers.
 155                  * We have no idea how many busses are behind this bridge yet,
 156                  * so we set the subordinate bus number to 0xff for the moment.
 157                  */
 158 #if SB_HT_CHAIN_ON_BUS0 > 0
 159                 // first chain will on bus 0
 160                 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
 161                         min_bus = max;
 162                 }
 163         #if SB_HT_CHAIN_ON_BUS0 > 1
 164                 // second chain will be on 0x40, third 0x80, forth 0xc0
 165                 else {
 166                         min_bus = ((max>>6) + 1) * 0x40;
 167                 }
 168                 max = min_bus;
 169         #else
 170                 //other ...
 171                 else  {
 172                         min_bus = ++max;
 173                 }
 174         #endif
 175 #else
 176                 min_bus = ++max;
 177 #endif
 178                 max_bus = 0xff;
 179
 180                 dev->link[link].secondary = min_bus;
 181                 dev->link[link].subordinate = max_bus;
 182
 183                 /* Read the existing primary/secondary/subordinate bus
 184                  * number configuration.
 185                  */
 186                 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
 187                 config_busses = f1_read_config32(config_reg);
 188
 189                 /* Configure the bus numbers for this bridge: the configuration
 190                  * transactions will not be propagates by the bridge if it is
 191                  * not correctly configured
 192                  */
 193                 busses &= 0xff000000;
 194                 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
 195                         ((unsigned int)(dev->link[link].secondary) << 8) |
 196                         ((unsigned int)(dev->link[link].subordinate) << 16));
 197                 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 198
 199                 config_busses &= 0x000fc88;
 200                 config_busses |=
 201                         (3 << 0) |  /* rw enable, no device compare */
 202                         (( nodeid & 7) << 4) |
 203                         (( link & 3 ) << 8) |
 204                         ((dev->link[link].secondary) << 16) |
 205                         ((dev->link[link].subordinate) << 24);
 206                 f1_write_config32(config_reg, config_busses);
 207
 208                 /* Now we can scan all of the subordinate busses i.e. the
 209                  * chain on the hypertranport link
 210                  */
 211                 for(i=0;i<4;i++) {
 212                         ht_unitid_base[i] = 0x20;
 213                 }
 214
 215                 if (min_bus == 0)
 216                         max_devfn = (0x17<<3) | 7;
 217                 else
 218                         max_devfn = (0x1f<<3) | 7;
 219
 220                 max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
 221
 222                 /* We know the number of busses behind this bridge.  Set the
 223                  * subordinate bus number to it's real value
 224                  */
 225                 dev->link[link].subordinate = max;
 226                 busses = (busses & 0xff00ffff) |
 227                         ((unsigned int) (dev->link[link].subordinate) << 16);
 228                 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 229
 230                 config_busses = (config_busses & 0x00ffffff) |
 231                         (dev->link[link].subordinate << 24);
 232                 f1_write_config32(config_reg, config_busses);
 233
 234                 {
 235                         // config config_reg, and ht_unitid_base to update hcdn_reg;
 236                         int index;
 237                         unsigned temp = 0;
 238                         index = (config_reg-0xe0) >> 2;
 239                         for(i=0;i<4;i++) {
 240                                 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
 241                         }
 242
 243                         sysconf.hcdn_reg[index] = temp;
 244
 245                 }
 246
 247         return max;
 248 }
 249
 250 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
 251 {
 252         unsigned nodeid;
 253         unsigned link;
 254         unsigned sblink = 0;
 255         unsigned offset_unitid = 0;
 256         nodeid = amdk8_nodeid(dev);
 257
 258         if(nodeid==0) {
 259                 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
 260 #if SB_HT_CHAIN_ON_BUS0 > 0
 261         #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
 262                 offset_unitid = 1;
 263         #endif
 264                 max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
 265 #endif
 266         }
 267
 268         for(link = 0; link < dev->links; link++) {
 269 #if SB_HT_CHAIN_ON_BUS0 > 0
 270                 if( (nodeid == 0) && (sblink == link) ) continue; //already done
 271 #endif
 272                 offset_unitid = 0;
 273                 #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
 274                         #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 275                         if((nodeid == 0) && (sblink == link))
 276                         #endif
 277                                 offset_unitid = 1;
 278                 #endif
 279
 280                 max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
 281         }
 282
 283         return max;
 284 }
 285
 286
 287 static int reg_useable(unsigned reg,
 288         device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
 289 {
 290         struct resource *res;
 291         unsigned nodeid, link;
 292         int result;
 293         res = 0;
 294         for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
 295                 device_t dev;
 296                 dev = __f0_dev[nodeid];
 297                 for(link = 0; !res && (link < 3); link++) {
 298                         res = probe_resource(dev, 0x100 + (reg | link));
 299                 }
 300         }
 301         result = 2;
 302         if (res) {
 303                 result = 0;
 304                 if (    (goal_link == (link - 1)) &&
 305                         (goal_nodeid == (nodeid - 1)) &&
 306                         (res->flags <= 1)) {
 307                         result = 1;
 308                 }
 309         }
 310
 311         return result;
 312 }
 313
 314 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
 315 {
 316         struct resource *resource;
 317         unsigned free_reg, reg;
 318         resource = 0;
 319         free_reg = 0;
 320         for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
 321                 int result;
 322                 result = reg_useable(reg, dev, nodeid, link);
 323                 if (result == 1) {
 324                         /* I have been allocated this one */
 325                         break;
 326                 }
 327                 else if (result > 1) {
 328                         /* I have a free register pair */
 329                         free_reg = reg;
 330                 }
 331         }
 332         if (reg > 0xd8) {
 333                 reg = free_reg;
 334         }
 335         if (reg > 0) {
 336                 resource = new_resource(dev, 0x100 + (reg | link));
 337         }
 338         return resource;
 339 }
 340
 341 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
 342 {
 343         struct resource *resource;
 344         unsigned free_reg, reg;
 345         resource = 0;
 346         free_reg = 0;
 347         for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
 348                 int result;
 349                 result = reg_useable(reg, dev, nodeid, link);
 350                 if (result == 1) {
 351                         /* I have been allocated this one */
 352                         break;
 353                 }
 354                 else if (result > 1) {
 355                         /* I have a free register pair */
 356                         free_reg = reg;
 357                 }
 358         }
 359         if (reg > 0xb8) {
 360                 reg = free_reg;
 361         }
 362         if (reg > 0) {
 363                 resource = new_resource(dev, 0x100 + (reg | link));
 364         }
 365         return resource;
 366 }
 367
 368 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
 369 {
 370         struct resource *resource;
 371
 372         /* Initialize the io space constraints on the current bus */
 373         resource =  amdk8_find_iopair(dev, nodeid, link);
 374         if (resource) {
 375                 resource->base  = 0;
 376                 resource->size  = 0;
 377                 resource->align = log2(HT_IO_HOST_ALIGN);
 378                 resource->gran  = log2(HT_IO_HOST_ALIGN);
 379                 resource->limit = 0xffffUL;
 380                 resource->flags = IORESOURCE_IO;
 381                 compute_allocate_resource(&dev->link[link], resource,
 382                         IORESOURCE_IO, IORESOURCE_IO);
 383         }
 384
 385         /* Initialize the prefetchable memory constraints on the current bus */
 386         resource = amdk8_find_mempair(dev, nodeid, link);
 387         if (resource) {
 388                 resource->base  = 0;
 389                 resource->size  = 0;
 390                 resource->align = log2(HT_MEM_HOST_ALIGN);
 391                 resource->gran  = log2(HT_MEM_HOST_ALIGN);
 392                 resource->limit = 0xffffffffffULL;
 393                 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 394                 compute_allocate_resource(&dev->link[link], resource,
 395                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 396                         IORESOURCE_MEM | IORESOURCE_PREFETCH);
 397         }
 398
 399         /* Initialize the memory constraints on the current bus */
 400         resource = amdk8_find_mempair(dev, nodeid, link);
 401         if (resource) {
 402                 resource->base  = 0;
 403                 resource->size  = 0;
 404                 resource->align = log2(HT_MEM_HOST_ALIGN);
 405                 resource->gran  = log2(HT_MEM_HOST_ALIGN);
 406                 resource->limit = 0xffffffffffULL;
 407                 resource->flags = IORESOURCE_MEM;
 408                 compute_allocate_resource(&dev->link[link], resource,
 409                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 410                         IORESOURCE_MEM);
 411         }
 412 }
 413
 414 static void amdk8_read_resources(device_t dev)
 415 {
 416         unsigned nodeid, link;
 417         nodeid = amdk8_nodeid(dev);
 418         for(link = 0; link < dev->links; link++) {
 419                 if (dev->link[link].children) {
 420                         amdk8_link_read_bases(dev, nodeid, link);
 421                 }
 422         }
 423 }
 424
 425 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
 426 {
 427         resource_t rbase, rend;
 428         unsigned reg, link;
 429         char buf[50];
 430
 431         /* Make certain the resource has actually been set */
 432         if (!(resource->flags & IORESOURCE_ASSIGNED)) {
 433                 return;
 434         }
 435
 436         /* If I have already stored this resource don't worry about it */
 437         if (resource->flags & IORESOURCE_STORED) {
 438                 return;
 439         }
 440
 441         /* Only handle PCI memory and IO resources */
 442         if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 443                 return;
 444
 445         /* Ensure I am actually looking at a resource of function 1 */
 446         if (resource->index < 0x100) {
 447                 return;
 448         }
 449         /* Get the base address */
 450         rbase = resource->base;
 451
 452         /* Get the limit (rounded up) */
 453         rend  = resource_end(resource);
 454
 455         /* Get the register and link */
 456         reg  = resource->index & 0xfc;
 457         link = resource->index & 3;
 458
 459         if (resource->flags & IORESOURCE_IO) {
 460                 uint32_t base, limit;
 461                 compute_allocate_resource(&dev->link[link], resource,
 462                         IORESOURCE_IO, IORESOURCE_IO);
 463                 base  = f1_read_config32(reg);
 464                 limit = f1_read_config32(reg + 0x4);
 465                 base  &= 0xfe000fcc;
 466                 base  |= rbase  & 0x01fff000;
 467                 base  |= 3;
 468                 limit &= 0xfe000fc8;
 469                 limit |= rend & 0x01fff000;
 470                 limit |= (link & 3) << 4;
 471                 limit |= (nodeid & 7);
 472
 473                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 474                         printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
 475                                     __func__, dev_path(dev), link);
 476                         base |= PCI_IO_BASE_VGA_EN;
 477                 }
 478                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
 479                         base |= PCI_IO_BASE_NO_ISA;
 480                 }
 481
 482                 f1_write_config32(reg + 0x4, limit);
 483                 f1_write_config32(reg, base);
 484         }
 485         else if (resource->flags & IORESOURCE_MEM) {
 486                 uint32_t base, limit;
 487                 compute_allocate_resource(&dev->link[link], resource,
 488                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 489                         resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
 490                 base  = f1_read_config32(reg);
 491                 limit = f1_read_config32(reg + 0x4);
 492                 base  &= 0x000000f0;
 493                 base  |= (rbase >> 8) & 0xffffff00;
 494                 base  |= 3;
 495                 limit &= 0x00000048;
 496                 limit |= (rend >> 8) & 0xffffff00;
 497                 limit |= (link & 3) << 4;
 498                 limit |= (nodeid & 7);
 499                 f1_write_config32(reg + 0x4, limit);
 500                 f1_write_config32(reg, base);
 501         }
 502         resource->flags |= IORESOURCE_STORED;
 503         sprintf(buf, " <node %d link %d>",
 504                 nodeid, link);
 505         report_resource_stored(dev, resource, buf);
 506 }
 507
 508 /**
 509  *
 510  * I tried to reuse the resource allocation code in amdk8_set_resource()
 511  * but it is too diffcult to deal with the resource allocation magic.
 512  */
 513 #if CONFIG_CONSOLE_VGA_MULTI == 1
 514 extern device_t vga_pri;        // the primary vga device, defined in device.c
 515 #endif
 516
 517 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
 518 {
 519         struct resource *resource;
 520         unsigned link;
 521         uint32_t base, limit;
 522         unsigned reg;
 523
 524         /* find out which link the VGA card is connected,
 525          * we only deal with the 'first' vga card */
 526         for (link = 0; link < dev->links; link++) {
 527                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 528 #if CONFIG_CONSOLE_VGA_MULTI == 1
 529                         printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 530                                 dev->link[link].secondary,dev->link[link].subordinate);
 531                         /* We need to make sure the vga_pri is under the link */
 532                         if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
 533                                 (vga_pri->bus->secondary <= dev->link[link].subordinate )
 534                         )
 535 #endif
 536                         break;
 537                 }
 538         }
 539
 540         /* no VGA card installed */
 541         if (link == dev->links)
 542                 return;
 543
 544         printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 545
 546         /* allocate a temp resrouce for legacy VGA buffer */
 547         resource = amdk8_find_mempair(dev, nodeid, link);
 548         if(!resource){
 549                 printk_debug("VGA: Can not find free mmio reg for legacy VGA buffer\n");
 550                 return;
 551         }
 552         resource->base = 0xa0000;
 553         resource->size = 0x20000;
 554
 555         /* write the resource to the hardware */
 556         reg  = resource->index & 0xfc;
 557         base  = f1_read_config32(reg);
 558         limit = f1_read_config32(reg + 0x4);
 559         base  &= 0x000000f0;
 560         base  |= (resource->base >> 8) & 0xffffff00;
 561         base  |= 3;
 562         limit &= 0x00000048;
 563         limit |= (resource_end(resource) >> 8) & 0xffffff00;
 564         limit |= (resource->index & 3) << 4;
 565         limit |= (nodeid & 7);
 566         f1_write_config32(reg + 0x4, limit);
 567         f1_write_config32(reg, base);
 568
 569         /* release the temp resource */
 570         resource->flags = 0;
 571 }
 572
 573 static void amdk8_set_resources(device_t dev)
 574 {
 575         unsigned nodeid, link;
 576         int i;
 577
 578         /* Find the nodeid */
 579         nodeid = amdk8_nodeid(dev);
 580
 581         amdk8_create_vga_resource(dev, nodeid);
 582
 583         /* Set each resource we have found */
 584         for(i = 0; i < dev->resources; i++) {
 585                 amdk8_set_resource(dev, &dev->resource[i], nodeid);
 586         }
 587
 588         for(link = 0; link < dev->links; link++) {
 589                 struct bus *bus;
 590                 bus = &dev->link[link];
 591                 if (bus->children) {
 592                         assign_resources(bus);
 593                 }
 594         }
 595 }
 596
 597 static void amdk8_enable_resources(device_t dev)
 598 {
 599         pci_dev_enable_resources(dev);
 600         enable_childrens_resources(dev);
 601 }
 602
 603 static void mcf0_control_init(struct device *dev)
 604 {
 605 #if 0
 606         printk_debug("NB: Function 0 Misc Control.. ");
 607 #endif
 608 #if 0
 609         printk_debug("done.\n");
 610 #endif
 611 }
 612
 613 static struct device_operations northbridge_operations = {
 614         .read_resources   = amdk8_read_resources,
 615         .set_resources    = amdk8_set_resources,
 616         .enable_resources = amdk8_enable_resources,
 617         .init             = mcf0_control_init,
 618         .scan_bus         = amdk8_scan_chains,
 619         .enable           = 0,
 620         .ops_pci          = 0,
 621 };
 622
 623
 624 static const struct pci_driver mcf0_driver __pci_driver = {
 625         .ops    = &northbridge_operations,
 626         .vendor = PCI_VENDOR_ID_AMD,
 627         .device = 0x1100,
 628 };
 629
 630 #if CONFIG_CHIP_NAME == 1
 631
 632 struct chip_operations northbridge_amd_amdk8_ops = {
 633         CHIP_NAME("AMD K8 Northbridge")
 634         .enable_dev = 0,
 635 };
 636
 637 #endif
 638
 639 static void pci_domain_read_resources(device_t dev)
 640 {
 641         struct resource *resource;
 642         unsigned reg;
 643
 644         /* Find the already assigned resource pairs */
 645         get_fx_devs();
 646         for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
 647                 uint32_t base, limit;
 648                 base  = f1_read_config32(reg);
 649                 limit = f1_read_config32(reg + 0x04);
 650                 /* Is this register allocated? */
 651                 if ((base & 3) != 0) {
 652                         unsigned nodeid, link;
 653                         device_t dev;
 654                         nodeid = limit & 7;
 655                         link   = (limit >> 4) & 3;
 656                         dev = __f0_dev[nodeid];
 657                         if (dev) {
 658                                 /* Reserve the resource  */
 659                                 struct resource *resource;
 660                                 resource = new_resource(dev, 0x100 + (reg | link));
 661                                 if (resource) {
 662                                         resource->flags = 1;
 663                                 }
 664                         }
 665                 }
 666         }
 667 #if CONFIG_PCI_64BIT_PREF_MEM == 0
 668         /* Initialize the system wide io space constraints */
 669         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 670         resource->base  = 0x400;
 671         resource->limit = 0xffffUL;
 672         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 673
 674         /* Initialize the system wide memory resources constraints */
 675         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 676         resource->limit = 0xfcffffffffULL;
 677         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 678 #else
 679         /* Initialize the system wide io space constraints */
 680         resource = new_resource(dev, 0);
 681         resource->base  = 0x400;
 682         resource->limit = 0xffffUL;
 683         resource->flags = IORESOURCE_IO;
 684         compute_allocate_resource(&dev->link[0], resource,
 685                 IORESOURCE_IO, IORESOURCE_IO);
 686
 687         /* Initialize the system wide prefetchable memory resources constraints */
 688         resource = new_resource(dev, 1);
 689         resource->limit = 0xfcffffffffULL;
 690         resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 691         compute_allocate_resource(&dev->link[0], resource,
 692                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 693                 IORESOURCE_MEM | IORESOURCE_PREFETCH);
 694
 695         /* Initialize the system wide memory resources constraints */
 696         resource = new_resource(dev, 2);
 697         resource->limit = 0xfcffffffffULL;
 698         resource->flags = IORESOURCE_MEM;
 699         compute_allocate_resource(&dev->link[0], resource,
 700                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 701                 IORESOURCE_MEM);
 702 #endif
 703 }
 704
 705 static void ram_resource(device_t dev, unsigned long index,
 706         unsigned long basek, unsigned long sizek)
 707 {
 708         struct resource *resource;
 709
 710         if (!sizek) {
 711                 return;
 712         }
 713         resource = new_resource(dev, index);
 714         resource->base  = ((resource_t)basek) << 10;
 715         resource->size  = ((resource_t)sizek) << 10;
 716         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 717                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 718 }
 719
 720 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 721 {
 722         struct resource **best_p = gp;
 723         struct resource *best;
 724         best = *best_p;
 725         if (!best || (best->base > new->base)) {
 726                 best = new;
 727         }
 728         *best_p = best;
 729 }
 730
 731 static uint32_t find_pci_tolm(struct bus *bus)
 732 {
 733         struct resource *min;
 734         uint32_t tolm;
 735         min = 0;
 736         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 737         tolm = 0xffffffffUL;
 738         if (min && tolm > min->base) {
 739                 tolm = min->base;
 740         }
 741         return tolm;
 742 }
 743
 744 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 745 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
 746 #endif
 747
 748 #if HW_MEM_HOLE_SIZEK != 0
 749
 750 struct hw_mem_hole_info {
 751         unsigned hole_startk;
 752         int node_id;
 753 };
 754
 755 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 756 {
 757                 struct hw_mem_hole_info mem_hole;
 758                 int i;
 759
 760                 mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
 761                 mem_hole.node_id = -1;
 762
 763                 for (i = 0; i < 8; i++) {
 764                         uint32_t base;
 765                         uint32_t hole;
 766                         base  = f1_read_config32(0x40 + (i << 3));
 767                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 768                                 continue;
 769                         }
 770
 771                         hole = pci_read_config32(__f1_dev[i], 0xf0);
 772                         if(hole & 1) { // we find the hole
 773                                 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
 774                                 mem_hole.node_id = i; // record the node No with hole
 775                                 break; // only one hole
 776                         }
 777                 }
 778
 779                 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
 780                 if(mem_hole.node_id==-1) {
 781                         uint32_t limitk_pri = 0;
 782                         for(i=0; i<8; i++) {
 783                                 uint32_t base, limit;
 784                                 unsigned base_k, limit_k;
 785                                 base  = f1_read_config32(0x40 + (i << 3));
 786                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 787                                         continue;
 788                                 }
 789
 790                                 base_k = (base & 0xffff0000) >> 2;
 791                                 if(limitk_pri != base_k) { // we find the hole
 792                                         mem_hole.hole_startk = limitk_pri;
 793                                         mem_hole.node_id = i;
 794                                         break; //only one hole
 795                                 }
 796
 797                                 limit = f1_read_config32(0x44 + (i << 3));
 798                                 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 799                                 limitk_pri = limit_k;
 800                         }
 801                 }
 802
 803                 return mem_hole;
 804
 805 }
 806 static void disable_hoist_memory(unsigned long hole_startk, int i)
 807 {
 808         int ii;
 809         device_t dev;
 810         uint32_t base, limit;
 811         uint32_t hoist;
 812         uint32_t hole_sizek;
 813
 814
 815         //1. find which node has hole
 816         //2. change limit in that node.
 817         //3. change base and limit in later node
 818         //4. clear that node f0
 819
 820         //if there is not mem hole enabled, we need to change it's base instead
 821
 822         hole_sizek = (4*1024*1024) - hole_startk;
 823
 824         for(ii=7;ii>i;ii--) {
 825
 826                 base  = f1_read_config32(0x40 + (ii << 3));
 827                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 828                         continue;
 829                 }
 830                 limit = f1_read_config32(0x44 + (ii << 3));
 831                 f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
 832                 f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
 833         }
 834         limit = f1_read_config32(0x44 + (i << 3));
 835         f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
 836         dev = __f1_dev[i];
 837         hoist = pci_read_config32(dev, 0xf0);
 838         if(hoist & 1) {
 839                 pci_write_config32(dev, 0xf0, 0);
 840         }
 841         else {
 842                 base = pci_read_config32(dev, 0x40 + (i << 3));
 843                 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
 844         }
 845
 846 }
 847
 848 static uint32_t hoist_memory(unsigned long hole_startk, int i)
 849 {
 850         int ii;
 851         uint32_t carry_over;
 852         device_t dev;
 853         uint32_t base, limit;
 854         uint32_t basek;
 855         uint32_t hoist;
 856
 857         carry_over = (4*1024*1024) - hole_startk;
 858
 859         for(ii=7;ii>i;ii--) {
 860
 861                 base  = f1_read_config32(0x40 + (ii << 3));
 862                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 863                         continue;
 864                 }
 865                 limit = f1_read_config32(0x44 + (ii << 3));
 866                 f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
 867                 f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
 868         }
 869         limit = f1_read_config32(0x44 + (i << 3));
 870         f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
 871         dev = __f1_dev[i];
 872         base  = pci_read_config32(dev, 0x40 + (i << 3));
 873         basek  = (base & 0xffff0000) >> 2;
 874         if(basek == hole_startk) {
 875                 //don't need set memhole here, because hole off set will be 0, overflow
 876                 //so need to change base reg instead, new basek will be 4*1024*1024
 877                 base &= 0x0000ffff;
 878                 base |= (4*1024*1024)<<2;
 879                 f1_write_config32(0x40 + (i<<3), base);
 880         }
 881         else
 882         {
 883                 hoist = /* hole start address */
 884                         ((hole_startk << 10) & 0xff000000) +
 885                         /* hole address to memory controller address */
 886                         (((basek + carry_over) >> 6) & 0x0000ff00) +
 887                         /* enable */
 888                         1;
 889
 890                 pci_write_config32(dev, 0xf0, hoist);
 891         }
 892
 893         return carry_over;
 894 }
 895 #endif
 896
 897 #if HAVE_HIGH_TABLES==1
 898 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
 899 extern uint64_t high_tables_base, high_tables_size;
 900 #endif
 901
 902 static void pci_domain_set_resources(device_t dev)
 903 {
 904 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 905         struct resource *io, *mem1, *mem2;
 906         struct resource *resource, *last;
 907 #endif
 908         unsigned long mmio_basek;
 909         uint32_t pci_tolm;
 910         int i, idx;
 911 #if HW_MEM_HOLE_SIZEK != 0
 912         struct hw_mem_hole_info mem_hole;
 913         unsigned reset_memhole = 1;
 914 #endif
 915
 916 #if 0
 917         /* Place the IO devices somewhere safe */
 918         io = find_resource(dev, 0);
 919         io->base = DEVICE_IO_START;
 920 #endif
 921 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 922         /* Now reallocate the pci resources memory with the
 923          * highest addresses I can manage.
 924          */
 925         mem1 = find_resource(dev, 1);
 926         mem2 = find_resource(dev, 2);
 927
 928 #if 1
 929         printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 930                 mem1->base, mem1->limit, mem1->size, mem1->align);
 931         printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 932                 mem2->base, mem2->limit, mem2->size, mem2->align);
 933 #endif
 934
 935         /* See if both resources have roughly the same limits */
 936         if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
 937                 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
 938         {
 939                 /* If so place the one with the most stringent alignment first
 940                  */
 941                 if (mem2->align > mem1->align) {
 942                         struct resource *tmp;
 943                         tmp = mem1;
 944                         mem1 = mem2;
 945                         mem2 = tmp;
 946                 }
 947                 /* Now place the memory as high up as it will go */
 948                 mem2->base = resource_max(mem2);
 949                 mem1->limit = mem2->base - 1;
 950                 mem1->base = resource_max(mem1);
 951         }
 952         else {
 953                 /* Place the resources as high up as they will go */
 954                 mem2->base = resource_max(mem2);
 955                 mem1->base = resource_max(mem1);
 956         }
 957
 958 #if 1
 959         printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 960                 mem1->base, mem1->limit, mem1->size, mem1->align);
 961         printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 962                 mem2->base, mem2->limit, mem2->size, mem2->align);
 963 #endif
 964
 965         last = &dev->resource[dev->resources];
 966         for(resource = &dev->resource[0]; resource < last; resource++)
 967         {
 968 #if 1
 969                 resource->flags |= IORESOURCE_ASSIGNED;
 970                 resource->flags &= ~IORESOURCE_STORED;
 971 #endif
 972                 compute_allocate_resource(&dev->link[0], resource,
 973                         BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
 974
 975                 resource->flags |= IORESOURCE_STORED;
 976                 report_resource_stored(dev, resource, "");
 977
 978         }
 979 #endif
 980
 981
 982         pci_tolm = find_pci_tolm(&dev->link[0]);
 983
 984 #warning "FIXME handle interleaved nodes"
 985         mmio_basek = pci_tolm >> 10;
 986         /* Round mmio_basek to something the processor can support */
 987         mmio_basek &= ~((1 << 6) -1);
 988
 989 #if 1
 990 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
 991         /* Round the mmio hold to 64M */
 992         mmio_basek &= ~((64*1024) - 1);
 993 #endif
 994
 995 #if HW_MEM_HOLE_SIZEK != 0
 996         /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
 997          * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
 998          * otherwise We reset the hole to the mmio_basek
 999          */
1000         #if K8_REV_F_SUPPORT == 0
1001                 if (!is_cpu_pre_e0()) {
1002         #endif
1003
1004                 mem_hole = get_hw_mem_hole_info();
1005
1006                 if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
1007                         mmio_basek = mem_hole.hole_startk;
1008                         reset_memhole = 0;
1009                 }
1010
1011                 //mmio_basek = 3*1024*1024; // for debug to meet boundary
1012
1013                 if(reset_memhole) {
1014                         if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
1015                                // We need to reset our Mem Hole, because We want more big HOLE than we already set
1016                                //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
1017                                 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
1018                         }
1019
1020                 #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
1021                         //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
1022                         uint32_t basek_pri;
1023                         for (i = 0; i < 8; i++) {
1024                                 uint32_t base;
1025                                 uint32_t basek;
1026                                 base  = f1_read_config32(0x40 + (i << 3));
1027                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1028                                         continue;
1029                                 }
1030
1031                                 basek = (base & 0xffff0000) >> 2;
1032                                 if(mmio_basek == basek) {
1033                                         mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
1034                                         break;
1035                                 }
1036                                 basek_pri = basek;
1037                         }
1038                 #endif
1039                 }
1040
1041 #if K8_REV_F_SUPPORT == 0
1042         } // is_cpu_pre_e0
1043 #endif
1044
1045 #endif
1046
1047         idx = 0x10;
1048         for(i = 0; i < 8; i++) {
1049                 uint32_t base, limit;
1050                 unsigned basek, limitk, sizek;
1051                 base  = f1_read_config32(0x40 + (i << 3));
1052                 limit = f1_read_config32(0x44 + (i << 3));
1053                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1054                         continue;
1055                 }
1056                 basek = (base & 0xffff0000) >> 2;
1057                 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
1058                 sizek = limitk - basek;
1059
1060                 /* see if we need a hole from 0xa0000 to 0xbffff */
1061                 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
1062                         ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1063                         idx += 0x10;
1064                         basek = (8*64)+(16*16);
1065                         sizek = limitk - ((8*64)+(16*16));
1066
1067                 }
1068
1069
1070 //              printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1071
1072                 /* See if I need to split the region to accomodate pci memory space */
1073                 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1074                         if (basek <= mmio_basek) {
1075                                 unsigned pre_sizek;
1076                                 pre_sizek = mmio_basek - basek;
1077                                 if(pre_sizek>0) {
1078                                         ram_resource(dev, (idx | i), basek, pre_sizek);
1079                                         idx += 0x10;
1080                                         sizek -= pre_sizek;
1081 #if HAVE_HIGH_TABLES==1
1082                                         if (i==0 && high_tables_base==0) {
1083                                         /* Leave some space for ACPI, PIRQ and MP tables */
1084                                                 high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
1085                                                 high_tables_size = HIGH_TABLES_SIZE * 1024;
1086                                                 printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
1087                                                              high_tables_base);
1088                                         }
1089 #endif
1090                                 }
1091                                 #if HW_MEM_HOLE_SIZEK != 0
1092                                 if(reset_memhole)
1093                                         #if K8_REV_F_SUPPORT == 0
1094                                         if(!is_cpu_pre_e0() )
1095                                         #endif
1096                                                  sizek += hoist_memory(mmio_basek,i);
1097                                 #endif
1098
1099                                 basek = mmio_basek;
1100                         }
1101                         if ((basek + sizek) <= 4*1024*1024) {
1102                                 sizek = 0;
1103                         }
1104                         else {
1105                                 basek = 4*1024*1024;
1106                                 sizek -= (4*1024*1024 - mmio_basek);
1107                         }
1108                 }
1109                 /* If sizek == 0, it was split at mmio_basek without a hole.
1110                  * Don't create an empty ram_resource.
1111                  */
1112                 if (sizek)
1113                         ram_resource(dev, (idx | i), basek, sizek);
1114                 idx += 0x10;
1115 #if HAVE_HIGH_TABLES==1
1116                 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
1117                              i, mmio_basek, basek, limitk);
1118                 if (i==0 && high_tables_base==0) {
1119                 /* Leave some space for ACPI, PIRQ and MP tables */
1120                         high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
1121                         high_tables_size = HIGH_TABLES_SIZE * 1024;
1122                 }
1123 #endif
1124         }
1125         assign_resources(&dev->link[0]);
1126
1127 }
1128
1129 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1130 {
1131         unsigned reg;
1132         int i;
1133         /* Unmap all of the HT chains */
1134         for(reg = 0xe0; reg <= 0xec; reg += 4) {
1135                 f1_write_config32(reg, 0);
1136         }
1137         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
1138
1139         /* Tune the hypertransport transaction for best performance.
1140          * Including enabling relaxed ordering if it is safe.
1141          */
1142         get_fx_devs();
1143         for(i = 0; i < FX_DEVS; i++) {
1144                 device_t f0_dev;
1145                 f0_dev = __f0_dev[i];
1146                 if (f0_dev && f0_dev->enabled) {
1147                         uint32_t httc;
1148                         httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1149                         httc &= ~HTTC_RSP_PASS_PW;
1150                         if (!dev->link[0].disable_relaxed_ordering) {
1151                                 httc |= HTTC_RSP_PASS_PW;
1152                         }
1153                         printk_spew("%s passpw: %s\n",
1154                                 dev_path(dev),
1155                                 (!dev->link[0].disable_relaxed_ordering)?
1156                                 "enabled":"disabled");
1157                         pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1158                 }
1159         }
1160         return max;
1161 }
1162
1163 static struct device_operations pci_domain_ops = {
1164         .read_resources   = pci_domain_read_resources,
1165         .set_resources    = pci_domain_set_resources,
1166         .enable_resources = enable_childrens_resources,
1167         .init             = 0,
1168         .scan_bus         = pci_domain_scan_bus,
1169         .ops_pci_bus      = &pci_cf8_conf1,
1170 };
1171
1172 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
1173 {
1174         struct bus *cpu_bus;
1175         device_t dev_mc;
1176         int bsp_apicid;
1177         int i,j;
1178         unsigned nb_cfg_54;
1179         unsigned siblings;
1180         int e0_later_single_core;
1181         int disable_siblings;
1182
1183         nb_cfg_54 = 0;
1184         sysconf.enabled_apic_ext_id = 0;
1185         sysconf.lift_bsp_apicid = 0;
1186         siblings = 0;
1187
1188         /* Find the bootstrap processors apicid */
1189         bsp_apicid = lapicid();
1190         sysconf.apicid_offset = bsp_apicid;
1191
1192         disable_siblings = !CONFIG_LOGICAL_CPUS;
1193 #if CONFIG_LOGICAL_CPUS == 1
1194         get_option(&disable_siblings, "dual_core");
1195 #endif
1196
1197         // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
1198         // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
1199
1200         nb_cfg_54 = read_nb_cfg_54();
1201
1202         dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1203         if (!dev_mc) {
1204                 die("0:18.0 not found?");
1205         }
1206
1207         sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1208
1209
1210         if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1211         {
1212                 sysconf.enabled_apic_ext_id = 1;
1213                 if(bsp_apicid == 0) {
1214                         /* bsp apic id is not changed */
1215                         sysconf.apicid_offset = APIC_ID_OFFSET;
1216                 } else
1217                 {
1218                         sysconf.lift_bsp_apicid = 1;
1219                 }
1220
1221         }
1222
1223         /* Find which cpus are present */
1224         cpu_bus = &dev->link[0];
1225         for(i = 0; i < sysconf.nodes; i++) {
1226                 device_t dev, cpu;
1227                 struct device_path cpu_path;
1228
1229                 /* Find the cpu's pci device */
1230                 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1231                 if (!dev) {
1232                         /* If I am probing things in a weird order
1233                          * ensure all of the cpu's pci devices are found.
1234                          */
1235                         int j;
1236                         device_t dev_f0;
1237                         for(j = 0; j <= 3; j++) {
1238                                 dev = pci_probe_dev(NULL, dev_mc->bus,
1239                                         PCI_DEVFN(0x18 + i, j));
1240                         }
1241                         /* Ok, We need to set the links for that device.
1242                          * otherwise the device under it will not be scanned
1243                          */
1244                         dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1245                         if(dev_f0) {
1246                                 dev_f0->links = 3;
1247                                 for(j=0;j<3;j++) {
1248                                         dev_f0->link[j].link = j;
1249                                         dev_f0->link[j].dev = dev_f0;
1250                                 }
1251                         }
1252
1253                 }
1254
1255                 e0_later_single_core = 0;
1256                 if (dev && dev->enabled) {
1257                         j = pci_read_config32(dev, 0xe8);
1258                         j = (j >> 12) & 3; // dev is func 3
1259                         printk_debug("  %s siblings=%d\n", dev_path(dev), j);
1260
1261                         if(nb_cfg_54) {
1262                                 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1263                                 //  ----> you can mixed single core e0 and dual core e0 at any sequence
1264                                 // That is the typical case
1265
1266                                 if(j == 0 ){
1267                                        #if K8_REV_F_SUPPORT == 0
1268                                         e0_later_single_core = is_e0_later_in_bsp(i);  // single core
1269                                        #else
1270                                         e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
1271                                        #endif
1272                                 } else {
1273                                        e0_later_single_core = 0;
1274                                 }
1275                                 if(e0_later_single_core) {
1276                                         printk_debug("\tFound Rev E or Rev F later single core\r\n");
1277
1278                                         j=1;
1279                                 }
1280
1281                                 if(siblings > j ) {
1282                                 }
1283                                 else {
1284                                         siblings = j;
1285                                 }
1286                         } else {
1287                                 siblings = j;
1288                         }
1289                 }
1290
1291                 unsigned jj;
1292                 if(e0_later_single_core || disable_siblings) {
1293                         jj = 0;
1294                 } else
1295                 {
1296                         jj = siblings;
1297                 }
1298 #if 0
1299                 jj = 0; // if create cpu core1 path in amd_siblings by core0
1300 #endif
1301
1302                 for (j = 0; j <=jj; j++ ) {
1303
1304                         /* Build the cpu device path */
1305                         cpu_path.type = DEVICE_PATH_APIC;
1306                         cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1307
1308                         /* See if I can find the cpu */
1309                         cpu = find_dev_path(cpu_bus, &cpu_path);
1310
1311                         /* Enable the cpu if I have the processor */
1312                         if (dev && dev->enabled) {
1313                                 if (!cpu) {
1314                                         cpu = alloc_dev(cpu_bus, &cpu_path);
1315                                 }
1316                                 if (cpu) {
1317                                         cpu->enabled = 1;
1318                                 }
1319                         }
1320
1321                         /* Disable the cpu if I don't have the processor */
1322                         if (cpu && (!dev || !dev->enabled)) {
1323                                 cpu->enabled = 0;
1324                         }
1325
1326                         /* Report what I have done */
1327                         if (cpu) {
1328                                 cpu->path.apic.node_id = i;
1329                                 cpu->path.apic.core_id = j;
1330                                 if(sysconf.enabled_apic_ext_id) {
1331                                         if(sysconf.lift_bsp_apicid) {
1332                                                 cpu->path.apic.apic_id += sysconf.apicid_offset;
1333                                         } else
1334                                         {
1335                                                if (cpu->path.apic.apic_id != 0)
1336                                                        cpu->path.apic.apic_id += sysconf.apicid_offset;
1337                                         }
1338                                 }
1339                                 printk_debug("CPU: %s %s\n",
1340                                         dev_path(cpu), cpu->enabled?"enabled":"disabled");
1341                         }
1342
1343                 } //j
1344         }
1345         return max;
1346 }
1347
1348 static void cpu_bus_init(device_t dev)
1349 {
1350         initialize_cpus(&dev->link[0]);
1351 }
1352
1353 static void cpu_bus_noop(device_t dev)
1354 {
1355 }
1356
1357 static struct device_operations cpu_bus_ops = {
1358         .read_resources   = cpu_bus_noop,
1359         .set_resources    = cpu_bus_noop,
1360         .enable_resources = cpu_bus_noop,
1361         .init             = cpu_bus_init,
1362         .scan_bus         = cpu_bus_scan,
1363 };
1364
1365 static void root_complex_enable_dev(struct device *dev)
1366 {
1367         /* Set the operations if it is a special bus type */
1368         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1369                 dev->ops = &pci_domain_ops;
1370         }
1371         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1372                 dev->ops = &cpu_bus_ops;
1373         }
1374 }
1375
1376 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1377         CHIP_NAME("AMD K8 Root Complex")
1378         .enable_dev = root_complex_enable_dev,
1379 };