1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/hypertransport.h>
13 #include "root_complex/chip.h"
14 #include "northbridge.h"
18 static device_t __f0_dev[FX_DEVS];
19 static device_t __f1_dev[FX_DEVS];
22 static void debug_fx_devs(void)
25 for (i = 0; i < FX_DEVS; i++) {
29 printk_debug("__f0_dev[%d]: %s bus: %p\n",
30 i, dev_path(dev), dev->bus);
34 printk_debug("__f1_dev[%d]: %s bus: %p\n",
35 i, dev_path(dev), dev->bus);
41 static void get_fx_devs(void)
47 for (i = 0; i < FX_DEVS; i++) {
48 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
49 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
52 die("Cannot find 0:0x18.1\n");
56 static uint32_t f1_read_config32(unsigned reg)
59 return pci_read_config32(__f1_dev[0], reg);
62 static void f1_write_config32(unsigned reg, uint32_t value)
66 for (i = 0; i < FX_DEVS; i++) {
69 if (dev && dev->enabled) {
70 pci_write_config32(dev, reg, value);
75 static unsigned int amdk8_nodeid(device_t dev)
77 return (dev->path.u.pci.devfn >> 3) - 0x18;
80 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
84 nodeid = amdk8_nodeid(dev);
86 printk_debug("%s amdk8_scan_chains max: %d starting...\n",
89 for (link = 0; link < dev->links; link++) {
91 uint32_t busses, config_busses;
92 unsigned free_reg, config_reg;
93 dev->link[link].cap = 0x80 + (link *0x20);
95 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
96 } while(link_type & ConnectionPending);
97 if (!(link_type & LinkConnected)) {
101 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
102 } while(!(link_type & InitComplete));
103 if (!(link_type & NonCoherent)) {
106 /* See if there is an available configuration space mapping
107 * register in function 1. */
109 for (config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
111 config = f1_read_config32(config_reg);
112 if (!free_reg && ((config & 3) == 0)) {
113 free_reg = config_reg;
116 if (((config & 3) == 3) &&
117 (((config >> 4) & 7) == nodeid) &&
118 (((config >> 8) & 3) == link)) {
122 if (free_reg && (config_reg > 0xec)) {
123 config_reg = free_reg;
125 /* If we can't find an available configuration space mapping
126 * register skip this bus */
127 if (config_reg > 0xec) {
131 /* Set up the primary, secondary and subordinate bus numbers.
132 * We have no idea how many busses are behind this bridge yet,
133 * so we set the subordinate bus number to 0xff for the moment.
135 dev->link[link].secondary = ++max;
136 dev->link[link].subordinate = 0xff;
138 /* Read the existing primary/secondary/subordinate bus
139 * number configuration.
141 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
142 config_busses = f1_read_config32(config_reg);
144 /* Configure the bus numbers for this bridge: the configuration
145 * transactions will not be propagates by the bridge if it is
146 * not correctly configured
148 busses &= 0xff000000;
149 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
150 ((unsigned int)(dev->link[link].secondary) << 8) |
151 ((unsigned int)(dev->link[link].subordinate) << 16));
152 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
154 config_busses &= 0x000fc88;
156 (3 << 0) | /* rw enable, no device compare */
157 (( nodeid & 7) << 4) |
158 (( link & 3 ) << 8) |
159 ((dev->link[link].secondary) << 16) |
160 ((dev->link[link].subordinate) << 24);
161 f1_write_config32(config_reg, config_busses);
164 printk_debug("%s Hyper transport scan link: %d max: %d\n",
165 dev_path(dev), link, max);
167 /* Now we can scan all of the subordinate busses i.e. the
168 * chain on the hypertranport link */
169 max = hypertransport_scan_chain(&dev->link[link], max);
172 printk_debug("%s Hyper transport scan link: %d new max: %d\n",
173 dev_path(dev), link, max);
176 /* We know the number of busses behind this bridge. Set the
177 * subordinate bus number to it's real value
179 dev->link[link].subordinate = max;
180 busses = (busses & 0xff00ffff) |
181 ((unsigned int) (dev->link[link].subordinate) << 16);
182 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
184 config_busses = (config_busses & 0x00ffffff) |
185 (dev->link[link].subordinate << 24);
186 f1_write_config32(config_reg, config_busses);
188 printk_debug("%s Hypertransport scan link: %d done\n",
189 dev_path(dev), link);
193 printk_debug("%s amdk8_scan_chains max: %d done\n",
199 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
202 struct resource *res;
203 unsigned nodeid, link;
206 for (nodeid = 0; !res && (nodeid < 8); nodeid++) {
208 dev = __f0_dev[nodeid];
209 for (link = 0; !res && (link < 3); link++) {
210 res = probe_resource(dev, 0x100 + (reg | link));
216 if ((goal_link == (link - 1)) &&
217 (goal_nodeid == (nodeid - 1)) &&
223 printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
224 reg, result, goal_nodeid, goal_link, nodeid, link);
229 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
231 struct resource *resource;
232 unsigned free_reg, reg;
235 for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
237 result = reg_useable(reg, dev, nodeid, link);
239 /* I have been allocated this one */
242 else if (result > 1) {
243 /* I have a free register pair */
251 resource = new_resource(dev, 0x100 + (reg | link));
256 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
258 struct resource *resource;
259 unsigned free_reg, reg;
262 for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
264 result = reg_useable(reg, dev, nodeid, link);
266 /* I have been allocated this one */
269 else if (result > 1) {
270 /* I have a free register pair */
278 resource = new_resource(dev, 0x100 + (reg | link));
283 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
285 struct resource *resource;
287 /* Initialize the io space constraints on the current bus */
288 resource = amdk8_find_iopair(dev, nodeid, link);
292 resource->align = log2(HT_IO_HOST_ALIGN);
293 resource->gran = log2(HT_IO_HOST_ALIGN);
294 resource->limit = 0xffffUL;
295 resource->flags = IORESOURCE_IO;
296 compute_allocate_resource(&dev->link[link], resource,
297 IORESOURCE_IO, IORESOURCE_IO);
300 /* Initialize the prefetchable memory constraints on the current bus */
301 resource = amdk8_find_mempair(dev, nodeid, link);
305 resource->align = log2(HT_MEM_HOST_ALIGN);
306 resource->gran = log2(HT_MEM_HOST_ALIGN);
307 resource->limit = 0xffffffffffULL;
308 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
309 compute_allocate_resource(&dev->link[link], resource,
310 IORESOURCE_MEM | IORESOURCE_PREFETCH,
311 IORESOURCE_MEM | IORESOURCE_PREFETCH);
314 /* Initialize the memory constraints on the current bus */
315 resource = amdk8_find_mempair(dev, nodeid, link);
319 resource->align = log2(HT_MEM_HOST_ALIGN);
320 resource->gran = log2(HT_MEM_HOST_ALIGN);
321 resource->limit = 0xffffffffffULL;
322 resource->flags = IORESOURCE_MEM;
323 compute_allocate_resource(&dev->link[link], resource,
324 IORESOURCE_MEM | IORESOURCE_PREFETCH,
329 static void amdk8_read_resources(device_t dev)
331 unsigned nodeid, link;
332 nodeid = amdk8_nodeid(dev);
333 for (link = 0; link < dev->links; link++) {
334 if (dev->link[link].children) {
335 amdk8_link_read_bases(dev, nodeid, link);
340 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
342 resource_t rbase, rend;
346 /* Make certain the resource has actually been set */
347 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
351 /* If I have already stored this resource don't worry about it */
352 if (resource->flags & IORESOURCE_STORED) {
356 /* Only handle PCI memory and IO resources */
357 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
360 /* Ensure I am actually looking at a resource of function 1 */
361 if (resource->index < 0x100) {
364 /* Get the base address */
365 rbase = resource->base;
367 /* Get the limit (rounded up) */
368 rend = resource_end(resource);
370 /* Get the register and link */
371 reg = resource->index & 0xfc;
372 link = resource->index & 3;
374 if (resource->flags & IORESOURCE_IO) {
375 uint32_t base, limit;
376 compute_allocate_resource(&dev->link[link], resource,
377 IORESOURCE_IO, IORESOURCE_IO);
378 base = f1_read_config32(reg);
379 limit = f1_read_config32(reg + 0x4);
381 base |= rbase & 0x01fff000;
384 limit |= rend & 0x01fff000;
385 limit |= (link & 3) << 4;
386 limit |= (nodeid & 7);
388 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
389 base |= PCI_IO_BASE_VGA_EN;
391 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
392 base |= PCI_IO_BASE_NO_ISA;
395 f1_write_config32(reg + 0x4, limit);
396 f1_write_config32(reg, base);
398 else if (resource->flags & IORESOURCE_MEM) {
399 uint32_t base, limit;
400 compute_allocate_resource(&dev->link[link], resource,
401 IORESOURCE_MEM | IORESOURCE_PREFETCH,
402 resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
403 base = f1_read_config32(reg);
404 limit = f1_read_config32(reg + 0x4);
406 base |= (rbase >> 8) & 0xffffff00;
409 limit |= (rend >> 8) & 0xffffff00;
410 limit |= (link & 3) << 4;
411 limit |= (nodeid & 7);
412 f1_write_config32(reg + 0x4, limit);
413 f1_write_config32(reg, base);
415 resource->flags |= IORESOURCE_STORED;
416 sprintf(buf, " <node %d link %d>",
418 report_resource_stored(dev, resource, buf);
423 * I tried to reuse the resource allocation code in amdk8_set_resource()
424 * but it is too diffcult to deal with the resource allocation magic.
426 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
428 struct resource *resource;
430 uint32_t base, limit;
433 /* find out which link the VGA card is connected,
434 * we only deal with the 'first' vga card */
435 for (link = 0; link < dev->links; link++) {
436 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
441 /* no VGA card installed */
442 if (link == dev->links)
445 /* allocate a temp resrouce for legacy VGA buffer */
446 resource = amdk8_find_mempair(dev, nodeid, link);
447 resource->base = 0xa0000;
448 resource->size = 0x20000;
450 /* write the resource to the hardware */
451 reg = resource->index & 0xfc;
452 base = f1_read_config32(reg);
453 limit = f1_read_config32(reg + 0x4);
455 base |= (resource->base >> 8) & 0xffffff00;
458 limit |= ((resource->base + resource->size) >> 8) & 0xffffff00;
459 limit |= (resource->index & 3) << 4;
460 limit |= (nodeid & 7);
461 f1_write_config32(reg + 0x4, limit);
462 f1_write_config32(reg, base);
464 /* release the temp resource */
468 static void amdk8_set_resources(device_t dev)
470 unsigned nodeid, link;
473 /* Find the nodeid */
474 nodeid = amdk8_nodeid(dev);
476 amdk8_create_vga_resource(dev, nodeid);
478 /* Set each resource we have found */
479 for (i = 0; i < dev->resources; i++) {
480 amdk8_set_resource(dev, &dev->resource[i], nodeid);
483 for (link = 0; link < dev->links; link++) {
485 bus = &dev->link[link];
487 assign_resources(bus);
492 static void amdk8_enable_resources(device_t dev)
494 pci_dev_enable_resources(dev);
495 enable_childrens_resources(dev);
498 static void mcf0_control_init(struct device *dev)
503 printk_debug("NB: Function 0 Misc Control.. ");
506 /* improve latency and bandwith on HT */
507 cmd = pci_read_config32(dev, 0x68);
510 pci_write_config32(dev, 0x68, cmd );
514 /* over drive the ht port to 1000 Mhz */
515 cmd = pci_read_config32(dev, 0xa8);
518 pci_write_config32(dev, 0xdc, cmd );
521 printk_debug("done.\n");
525 static struct device_operations northbridge_operations = {
526 .read_resources = amdk8_read_resources,
527 .set_resources = amdk8_set_resources,
528 .enable_resources = amdk8_enable_resources,
529 .init = mcf0_control_init,
530 .scan_bus = amdk8_scan_chains,
536 static struct pci_driver mcf0_driver __pci_driver = {
537 .ops = &northbridge_operations,
538 .vendor = PCI_VENDOR_ID_AMD,
542 #if CONFIG_CHIP_NAME == 1
544 struct chip_operations northbridge_amd_amdk8_ops = {
545 CHIP_NAME("AMD K8 Northbridge")
551 static void pci_domain_read_resources(device_t dev)
553 struct resource *resource;
556 /* Find the already assigned resource pairs */
558 for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
559 uint32_t base, limit;
560 base = f1_read_config32(reg);
561 limit = f1_read_config32(reg + 0x04);
562 /* Is this register allocated? */
563 if ((base & 3) != 0) {
564 unsigned nodeid, link;
567 link = (limit >> 4) & 3;
568 dev = __f0_dev[nodeid];
570 /* Reserve the resource */
571 struct resource *resource;
572 resource = new_resource(dev, 0x100 + (reg | link));
580 /* Initialize the system wide io space constraints */
581 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
582 resource->base = 0x400;
583 resource->limit = 0xffffUL;
584 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
586 /* Initialize the system wide memory resources constraints */
587 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
588 resource->limit = 0xfcffffffffULL;
589 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
592 static void ram_resource(device_t dev, unsigned long index,
593 unsigned long basek, unsigned long sizek)
595 struct resource *resource;
600 resource = new_resource(dev, index);
601 resource->base = ((resource_t)basek) << 10;
602 resource->size = ((resource_t)sizek) << 10;
603 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
604 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
607 static void tolm_test(void *gp, struct device *dev, struct resource *new)
609 struct resource **best_p = gp;
610 struct resource *best;
612 if (!best || (best->base > new->base)) {
618 static uint32_t find_pci_tolm(struct bus *bus)
620 struct resource *min;
623 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
625 if (min && tolm > min->base) {
631 static void pci_domain_set_resources(device_t dev)
633 unsigned long mmio_basek;
637 pci_tolm = find_pci_tolm(&dev->link[0]);
639 #warning "FIXME handle interleaved nodes"
640 mmio_basek = pci_tolm >> 10;
641 /* Round mmio_basek to something the processor can support */
642 mmio_basek &= ~((1 << 6) -1);
645 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
646 /* Round the mmio hold to 64M */
647 mmio_basek &= ~((64*1024) - 1);
651 for (i = 0; i < 8; i++) {
652 uint32_t base, limit;
653 unsigned basek, limitk, sizek;
654 base = f1_read_config32(0x40 + (i << 3));
655 limit = f1_read_config32(0x44 + (i << 3));
656 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
659 basek = (base & 0xffff0000) >> 2;
660 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
661 sizek = limitk - basek;
663 /* see if we need a hole from 0xa0000 to 0xbffff */
664 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
665 ram_resource(dev, idx++, basek, ((8*64)+(8*16)) - basek);
666 basek = (8*64)+(16*16);
667 sizek = limitk - ((8*64)+(16*16));
672 /* See if I need to split the region to accomodate pci memory space */
673 if ((basek < mmio_basek) && (limitk > mmio_basek)) {
674 if (basek < mmio_basek) {
676 pre_sizek = mmio_basek - basek;
677 ram_resource(dev, idx++, basek, pre_sizek);
681 if ((basek + sizek) <= 4*1024*1024) {
686 sizek -= (4*1024*1024 - mmio_basek);
689 ram_resource(dev, idx++, basek, sizek);
691 assign_resources(&dev->link[0]);
694 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
697 /* Unmap all of the HT chains */
698 for (reg = 0xe0; reg <= 0xec; reg += 4) {
699 f1_write_config32(reg, 0);
701 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
705 static struct device_operations pci_domain_ops = {
706 .read_resources = pci_domain_read_resources,
707 .set_resources = pci_domain_set_resources,
708 .enable_resources = enable_childrens_resources,
710 .scan_bus = pci_domain_scan_bus,
711 .ops_pci_bus = &pci_cf8_conf1,
714 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
718 int apic_id_offset = lapicid(); // bsp apicid
720 /* Find which cpus are present */
721 cpu_bus = &dev->link[0];
722 for (i = 0; i < 8; i++) {
724 struct device_path cpu_path;
726 /* Find the cpu's memory controller */
727 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
729 /* Build the cpu device path */
730 cpu_path.type = DEVICE_PATH_APIC;
731 cpu_path.u.apic.apic_id = i;
733 /* See if I can find the cpu */
734 cpu = find_dev_path(cpu_bus, &cpu_path);
736 /* Enable the cpu if I have the processor */
737 if (dev && dev->enabled) {
739 cpu = alloc_dev(cpu_bus, &cpu_path);
746 /* Disable the cpu if I don't have the processor */
747 if (cpu && (!dev || !dev->enabled)) {
751 /* Report what I have done */
753 if(cpu->path.u.apic.apic_id<apic_id_offset) {
754 cpu->path.u.apic.apic_id += apic_id_offset;
756 printk_debug("CPU: %s %s\n", dev_path(cpu),
757 cpu->enabled?"enabled":"disabled");
763 static void cpu_bus_init(device_t dev)
765 initialize_cpus(&dev->link[0]);
768 static void cpu_bus_noop(device_t dev)
772 static struct device_operations cpu_bus_ops = {
773 .read_resources = cpu_bus_noop,
774 .set_resources = cpu_bus_noop,
775 .enable_resources = cpu_bus_noop,
776 .init = cpu_bus_init,
777 .scan_bus = cpu_bus_scan,
780 static void root_complex_enable_dev(struct device *dev)
782 /* Set the operations if it is a special bus type */
783 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
784 dev->ops = &pci_domain_ops;
786 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
787 dev->ops = &cpu_bus_ops;
791 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
792 CHIP_NAME("AMD K8 Root Complex")
793 .enable_dev = root_complex_enable_dev,