src/northbridge/amd/amdk8/northbridge.c

   1 /* This should be done by Eric
   2         2004.12 yhlu add dual core support
   3         2005.01 yhlu add support move apic before pci_domain in MB Config.lb
   4         2005.02 yhlu add e0 memory hole support
   5         2005.11 yhlu add put sb ht chain on bus 0
   6 */
   7
   8 #include <console/console.h>
   9 #include <arch/io.h>
  10 #include <stdint.h>
  11 #include <device/device.h>
  12 #include <device/pci.h>
  13 #include <device/pci_ids.h>
  14 #include <device/hypertransport.h>
  15 #include <stdlib.h>
  16 #include <string.h>
  17 #include <bitops.h>
  18 #include <cpu/cpu.h>
  19
  20 #include <cpu/x86/lapic.h>
  21
  22 #include <cpu/amd/dualcore.h>
  23 #if CONFIG_LOGICAL_CPUS==1
  24 #include <pc80/mc146818rtc.h>
  25 #endif
  26
  27 #include "chip.h"
  28 #include "root_complex/chip.h"
  29 #include "northbridge.h"
  30
  31 #include "amdk8.h"
  32
  33 #include <cpu/amd/model_fxx_rev.h>
  34
  35 #include <cpu/amd/amdk8_sysconf.h>
  36
  37 struct amdk8_sysconf_t sysconf;
  38
  39 #define MAX_FX_DEVS 8
  40 static device_t __f0_dev[MAX_FX_DEVS];
  41 static device_t __f1_dev[MAX_FX_DEVS];
  42 static unsigned fx_devs=0;
  43
  44 static void get_fx_devs(void)
  45 {
  46         int i;
  47         for(i = 0; i < MAX_FX_DEVS; i++) {
  48                 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
  49                 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
  50                 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
  51                         fx_devs = i+1;
  52         }
  53         if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
  54                 die("Cannot find 0:0x18.[0|1]\n");
  55         }
  56 }
  57
  58 static uint32_t f1_read_config32(unsigned reg)
  59 {
  60         if ( fx_devs == 0)
  61                 get_fx_devs();
  62         return pci_read_config32(__f1_dev[0], reg);
  63 }
  64
  65 static void f1_write_config32(unsigned reg, uint32_t value)
  66 {
  67         int i;
  68         if ( fx_devs == 0)
  69                 get_fx_devs();
  70         for(i = 0; i < fx_devs; i++) {
  71                 device_t dev;
  72                 dev = __f1_dev[i];
  73                 if (dev && dev->enabled) {
  74                         pci_write_config32(dev, reg, value);
  75                 }
  76         }
  77 }
  78
  79 static unsigned int amdk8_nodeid(device_t dev)
  80 {
  81         return (dev->path.pci.devfn >> 3) - 0x18;
  82 }
  83
  84 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
  85 {
  86
  87                 uint32_t link_type;
  88                 int i;
  89                 uint32_t busses, config_busses;
  90                 unsigned free_reg, config_reg;
  91                 unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
  92                 unsigned max_bus;
  93                 unsigned min_bus;
  94                 unsigned max_devfn;
  95
  96                 dev->link[link].cap = 0x80 + (link *0x20);
  97                 do {
  98                         link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
  99                 } while(link_type & ConnectionPending);
 100                 if (!(link_type & LinkConnected)) {
 101                         return max;
 102                 }
 103                 do {
 104                         link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 105                 } while(!(link_type & InitComplete));
 106                 if (!(link_type & NonCoherent)) {
 107                         return max;
 108                 }
 109                 /* See if there is an available configuration space mapping
 110                  * register in function 1.
 111                  */
 112                 free_reg = 0;
 113                 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
 114                         uint32_t config;
 115                         config = f1_read_config32(config_reg);
 116                         if (!free_reg && ((config & 3) == 0)) {
 117                                 free_reg = config_reg;
 118                                 continue;
 119                         }
 120                         if (((config & 3) == 3) &&
 121                                 (((config >> 4) & 7) == nodeid) &&
 122                                 (((config >> 8) & 3) == link)) {
 123                                 break;
 124                         }
 125                 }
 126                 if (free_reg && (config_reg > 0xec)) {
 127                         config_reg = free_reg;
 128                 }
 129                 /* If we can't find an available configuration space mapping
 130                  * register skip this bus
 131                  */
 132                 if (config_reg > 0xec) {
 133                         return max;
 134                 }
 135
 136                 /* Set up the primary, secondary and subordinate bus numbers.
 137                  * We have no idea how many busses are behind this bridge yet,
 138                  * so we set the subordinate bus number to 0xff for the moment.
 139                  */
 140 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 141                 // first chain will on bus 0
 142                 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
 143                         min_bus = max;
 144                 }
 145         #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
 146                 // second chain will be on 0x40, third 0x80, forth 0xc0
 147                 else {
 148                         min_bus = ((max>>6) + 1) * 0x40;
 149                 }
 150                 max = min_bus;
 151         #else
 152                 //other ...
 153                 else  {
 154                         min_bus = ++max;
 155                 }
 156         #endif
 157 #else
 158                 min_bus = ++max;
 159 #endif
 160                 max_bus = 0xff;
 161
 162                 dev->link[link].secondary = min_bus;
 163                 dev->link[link].subordinate = max_bus;
 164
 165                 /* Read the existing primary/secondary/subordinate bus
 166                  * number configuration.
 167                  */
 168                 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
 169                 config_busses = f1_read_config32(config_reg);
 170
 171                 /* Configure the bus numbers for this bridge: the configuration
 172                  * transactions will not be propagates by the bridge if it is
 173                  * not correctly configured
 174                  */
 175                 busses &= 0xff000000;
 176                 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
 177                         ((unsigned int)(dev->link[link].secondary) << 8) |
 178                         ((unsigned int)(dev->link[link].subordinate) << 16));
 179                 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 180
 181                 config_busses &= 0x000fc88;
 182                 config_busses |=
 183                         (3 << 0) |  /* rw enable, no device compare */
 184                         (( nodeid & 7) << 4) |
 185                         (( link & 3 ) << 8) |
 186                         ((dev->link[link].secondary) << 16) |
 187                         ((dev->link[link].subordinate) << 24);
 188                 f1_write_config32(config_reg, config_busses);
 189
 190                 /* Now we can scan all of the subordinate busses i.e. the
 191                  * chain on the hypertranport link
 192                  */
 193                 for(i=0;i<4;i++) {
 194                         ht_unitid_base[i] = 0x20;
 195                 }
 196
 197                 if (min_bus == 0)
 198                         max_devfn = (0x17<<3) | 7;
 199                 else
 200                         max_devfn = (0x1f<<3) | 7;
 201
 202                 max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
 203
 204                 /* We know the number of busses behind this bridge.  Set the
 205                  * subordinate bus number to it's real value
 206                  */
 207                 dev->link[link].subordinate = max;
 208                 busses = (busses & 0xff00ffff) |
 209                         ((unsigned int) (dev->link[link].subordinate) << 16);
 210                 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 211
 212                 config_busses = (config_busses & 0x00ffffff) |
 213                         (dev->link[link].subordinate << 24);
 214                 f1_write_config32(config_reg, config_busses);
 215
 216                 {
 217                         // config config_reg, and ht_unitid_base to update hcdn_reg;
 218                         int index;
 219                         unsigned temp = 0;
 220                         index = (config_reg-0xe0) >> 2;
 221                         for(i=0;i<4;i++) {
 222                                 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
 223                         }
 224
 225                         sysconf.hcdn_reg[index] = temp;
 226
 227                 }
 228
 229         return max;
 230 }
 231
 232 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
 233 {
 234         unsigned nodeid;
 235         unsigned link;
 236         unsigned sblink = 0;
 237         unsigned offset_unitid = 0;
 238         nodeid = amdk8_nodeid(dev);
 239
 240         if(nodeid==0) {
 241                 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
 242 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 243         #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
 244                 offset_unitid = 1;
 245         #endif
 246                 max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
 247 #endif
 248         }
 249
 250         for(link = 0; link < dev->links; link++) {
 251 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 252                 if( (nodeid == 0) && (sblink == link) ) continue; //already done
 253 #endif
 254                 offset_unitid = 0;
 255                 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
 256                         #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 257                         if((nodeid == 0) && (sblink == link))
 258                         #endif
 259                                 offset_unitid = 1;
 260                 #endif
 261
 262                 max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
 263         }
 264
 265         return max;
 266 }
 267
 268
 269 static int reg_useable(unsigned reg,
 270         device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
 271 {
 272         struct resource *res;
 273         unsigned nodeid, link=0;
 274         int result;
 275         res = 0;
 276         for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
 277                 device_t dev;
 278                 dev = __f0_dev[nodeid];
 279                 if (!dev)
 280                         continue;
 281                 for(link = 0; !res && (link < 3); link++) {
 282                         res = probe_resource(dev, IOINDEX(0x100 + reg, link));
 283                 }
 284         }
 285         result = 2;
 286         if (res) {
 287                 result = 0;
 288                 if (    (goal_link == (link - 1)) &&
 289                         (goal_nodeid == (nodeid - 1)) &&
 290                         (res->flags <= 1)) {
 291                         result = 1;
 292                 }
 293         }
 294
 295         return result;
 296 }
 297
 298 static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
 299                                unsigned min, unsigned max)
 300 {
 301         unsigned resource;
 302         unsigned free_reg, reg;
 303         resource = 0;
 304         free_reg = 0;
 305         for(reg = min; reg <= max; reg += 0x8) {
 306                 int result;
 307                 result = reg_useable(reg, dev, nodeid, link);
 308                 if (result == 1) {
 309                         /* I have been allocated this one */
 310                         break;
 311                 }
 312                 else if (result > 1) {
 313                         /* I have a free register pair */
 314                         free_reg = reg;
 315                 }
 316         }
 317         if (reg > max) {
 318                 reg = free_reg;
 319         }
 320         if (reg > 0) {
 321                 resource = IOINDEX(0x100 + reg, link);
 322         }
 323         return resource;
 324 }
 325
 326 static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
 327 {
 328         return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
 329 }
 330
 331 static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
 332 {
 333         return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
 334 }
 335
 336 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
 337 {
 338         struct resource *resource;
 339
 340         /* Initialize the io space constraints on the current bus */
 341         resource = new_resource(dev, IOINDEX(0, link));
 342         if (resource) {
 343                 resource->base  = 0;
 344                 resource->size  = 0;
 345                 resource->align = log2(HT_IO_HOST_ALIGN);
 346                 resource->gran  = log2(HT_IO_HOST_ALIGN);
 347                 resource->limit = 0xffffUL;
 348                 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
 349         }
 350
 351         /* Initialize the prefetchable memory constraints on the current bus */
 352         resource = new_resource(dev, IOINDEX(2, link));
 353         if (resource) {
 354                 resource->base  = 0;
 355                 resource->size  = 0;
 356                 resource->align = log2(HT_MEM_HOST_ALIGN);
 357                 resource->gran  = log2(HT_MEM_HOST_ALIGN);
 358                 resource->limit = 0xffffffffffULL;
 359                 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 360 #ifdef CONFIG_PCI_64BIT_PREF_MEM
 361                 resource->flags |= IORESOURCE_BRIDGE;
 362 #endif
 363         }
 364
 365         /* Initialize the memory constraints on the current bus */
 366         resource = new_resource(dev, IOINDEX(1, link));
 367         if (resource) {
 368                 resource->base  = 0;
 369                 resource->size  = 0;
 370                 resource->align = log2(HT_MEM_HOST_ALIGN);
 371                 resource->gran  = log2(HT_MEM_HOST_ALIGN);
 372                 resource->limit = 0xffffffffULL;
 373                 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
 374         }
 375 }
 376
 377 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
 378
 379 static void amdk8_read_resources(device_t dev)
 380 {
 381         unsigned nodeid, link;
 382         nodeid = amdk8_nodeid(dev);
 383         for(link = 0; link < dev->links; link++) {
 384                 if (dev->link[link].children) {
 385                         amdk8_link_read_bases(dev, nodeid, link);
 386                 }
 387         }
 388
 389         amdk8_create_vga_resource(dev, nodeid);
 390 }
 391
 392 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
 393 {
 394         resource_t rbase, rend;
 395         unsigned reg, link;
 396         char buf[50];
 397
 398         /* Make certain the resource has actually been set */
 399         if (!(resource->flags & IORESOURCE_ASSIGNED)) {
 400                 printk_err("%s: can't set unassigned resource @%lx %lx\n",
 401                            __func__, resource->index, resource->flags);
 402                 return;
 403         }
 404
 405         /* If I have already stored this resource don't worry about it */
 406         if (resource->flags & IORESOURCE_STORED) {
 407                 printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
 408                            resource->index, resource->flags);
 409                 return;
 410         }
 411
 412         /* Only handle PCI memory and IO resources */
 413         if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 414                 return;
 415
 416         /* Ensure I am actually looking at a resource of function 1 */
 417         if (resource->index < 0x100) {
 418                 return;
 419         }
 420
 421         if (resource->size == 0)
 422                 return;
 423
 424         /* Get the base address */
 425         rbase = resource->base;
 426
 427         /* Get the limit (rounded up) */
 428         rend  = resource_end(resource);
 429
 430         /* Get the register and link */
 431         reg  = resource->index & 0xfc;
 432         link = IOINDEX_LINK(resource->index);
 433
 434         if (resource->flags & IORESOURCE_IO) {
 435                 uint32_t base, limit;
 436                 base  = f1_read_config32(reg);
 437                 limit = f1_read_config32(reg + 0x4);
 438                 base  &= 0xfe000fcc;
 439                 base  |= rbase  & 0x01fff000;
 440                 base  |= 3;
 441                 limit &= 0xfe000fc8;
 442                 limit |= rend & 0x01fff000;
 443                 limit |= (link & 3) << 4;
 444                 limit |= (nodeid & 7);
 445
 446                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 447                         printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
 448                                     __func__, dev_path(dev), link);
 449                         base |= PCI_IO_BASE_VGA_EN;
 450                 }
 451                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
 452                         base |= PCI_IO_BASE_NO_ISA;
 453                 }
 454
 455                 f1_write_config32(reg + 0x4, limit);
 456                 f1_write_config32(reg, base);
 457         }
 458         else if (resource->flags & IORESOURCE_MEM) {
 459                 uint32_t base, limit;
 460                 base  = f1_read_config32(reg);
 461                 limit = f1_read_config32(reg + 0x4);
 462                 base  &= 0x000000f0;
 463                 base  |= (rbase >> 8) & 0xffffff00;
 464                 base  |= 3;
 465                 limit &= 0x00000048;
 466                 limit |= (rend >> 8) & 0xffffff00;
 467                 limit |= (link & 3) << 4;
 468                 limit |= (nodeid & 7);
 469                 f1_write_config32(reg + 0x4, limit);
 470                 f1_write_config32(reg, base);
 471         }
 472         resource->flags |= IORESOURCE_STORED;
 473         sprintf(buf, " <node %d link %d>",
 474                 nodeid, link);
 475         report_resource_stored(dev, resource, buf);
 476 }
 477
 478 #if CONFIG_CONSOLE_VGA_MULTI == 1
 479 extern device_t vga_pri;        // the primary vga device, defined in device.c
 480 #endif
 481
 482 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
 483 {
 484         struct resource *resource;
 485         unsigned link;
 486
 487         /* find out which link the VGA card is connected,
 488          * we only deal with the 'first' vga card */
 489         for (link = 0; link < dev->links; link++) {
 490                 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 491 #if CONFIG_CONSOLE_VGA_MULTI == 1
 492                         printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 493                                 dev->link[link].secondary,dev->link[link].subordinate);
 494                         /* We need to make sure the vga_pri is under the link */
 495                         if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
 496                                 (vga_pri->bus->secondary <= dev->link[link].subordinate )
 497                         )
 498 #endif
 499                         break;
 500                 }
 501         }
 502
 503         /* no VGA card installed */
 504         if (link == dev->links)
 505                 return;
 506
 507         printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 508
 509         /* allocate a temp resource for the legacy VGA buffer */
 510         resource = new_resource(dev, IOINDEX(4, link));
 511         if(!resource){
 512                 printk_debug("VGA: %s out of resources.\n", dev_path(dev));
 513                 return;
 514         }
 515         resource->base = 0xa0000;
 516         resource->size = 0x20000;
 517         resource->limit = 0xffffffff;
 518         resource->flags = IORESOURCE_FIXED | IORESOURCE_MEM |
 519                           IORESOURCE_ASSIGNED;
 520 }
 521
 522 static void amdk8_set_resources(device_t dev)
 523 {
 524         unsigned nodeid, link;
 525         int i;
 526
 527         /* Find the nodeid */
 528         nodeid = amdk8_nodeid(dev);
 529
 530         /* Set each resource we have found */
 531         for(i = 0; i < dev->resources; i++) {
 532                 struct resource *res = &dev->resource[i];
 533                 struct resource *old = NULL;
 534                 unsigned index;
 535
 536                 if (res->size == 0) /* No need to allocate registers. */
 537                         continue;
 538
 539                 if (res->flags & IORESOURCE_IO)
 540                         index = amdk8_find_iopair(dev, nodeid,
 541                                                   IOINDEX_LINK(res->index));
 542                 else
 543                         index = amdk8_find_mempair(dev, nodeid,
 544                                                    IOINDEX_LINK(res->index));
 545
 546                 old = probe_resource(dev, index);
 547                 if (old) {
 548                         res->index = old->index;
 549                         old->index = 0;
 550                         old->flags = 0;
 551                 }
 552                 else
 553                         res->index = index;
 554
 555                 amdk8_set_resource(dev, res, nodeid);
 556         }
 557
 558         compact_resources(dev);
 559
 560         for(link = 0; link < dev->links; link++) {
 561                 struct bus *bus;
 562                 bus = &dev->link[link];
 563                 if (bus->children) {
 564                         assign_resources(bus);
 565                 }
 566         }
 567 }
 568
 569 static void amdk8_enable_resources(device_t dev)
 570 {
 571         pci_dev_enable_resources(dev);
 572         enable_childrens_resources(dev);
 573 }
 574
 575 static void mcf0_control_init(struct device *dev)
 576 {
 577 #if 0
 578         printk_debug("NB: Function 0 Misc Control.. ");
 579 #endif
 580 #if 0
 581         printk_debug("done.\n");
 582 #endif
 583 }
 584
 585 static struct device_operations northbridge_operations = {
 586         .read_resources   = amdk8_read_resources,
 587         .set_resources    = amdk8_set_resources,
 588         .enable_resources = amdk8_enable_resources,
 589         .init             = mcf0_control_init,
 590         .scan_bus         = amdk8_scan_chains,
 591         .enable           = 0,
 592         .ops_pci          = 0,
 593 };
 594
 595
 596 static const struct pci_driver mcf0_driver __pci_driver = {
 597         .ops    = &northbridge_operations,
 598         .vendor = PCI_VENDOR_ID_AMD,
 599         .device = 0x1100,
 600 };
 601
 602 struct chip_operations northbridge_amd_amdk8_ops = {
 603         CHIP_NAME("AMD K8 Northbridge")
 604         .enable_dev = 0,
 605 };
 606
 607 static void amdk8_domain_read_resources(device_t dev)
 608 {
 609         unsigned reg;
 610
 611         /* Find the already assigned resource pairs */
 612         get_fx_devs();
 613         for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
 614                 uint32_t base, limit;
 615                 base  = f1_read_config32(reg);
 616                 limit = f1_read_config32(reg + 0x04);
 617                 /* Is this register allocated? */
 618                 if ((base & 3) != 0) {
 619                         unsigned nodeid, link;
 620                         device_t reg_dev;
 621                         nodeid = limit & 7;
 622                         link   = (limit >> 4) & 3;
 623                         reg_dev = __f0_dev[nodeid];
 624                         if (reg_dev) {
 625                                 /* Reserve the resource  */
 626                                 struct resource *res;
 627                                 res = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
 628                                 if (res) {
 629                                         res->base = base;
 630                                         res->limit = limit;
 631                                         res->flags = 1;
 632                                 }
 633                         }
 634                 }
 635         }
 636
 637         pci_domain_read_resources(dev);
 638
 639 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 640         /* Initialize the system wide prefetchable memory resources constraints */
 641         resource = new_resource(dev, 2);
 642         resource->limit = 0xfcffffffffULL;
 643         resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 644 #endif
 645 }
 646
 647 static void ram_resource(device_t dev, unsigned long index,
 648         unsigned long basek, unsigned long sizek)
 649 {
 650         struct resource *resource;
 651
 652         if (!sizek) {
 653                 return;
 654         }
 655         resource = new_resource(dev, index);
 656         resource->base  = ((resource_t)basek) << 10;
 657         resource->size  = ((resource_t)sizek) << 10;
 658         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 659                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 660 }
 661
 662 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 663 {
 664         struct resource **best_p = gp;
 665         struct resource *best;
 666         best = *best_p;
 667         /* Skip VGA. */
 668         if (!best || (best->base > new->base && new->base > 0xa0000)) {
 669                 best = new;
 670         }
 671         *best_p = best;
 672 }
 673
 674 static uint32_t find_pci_tolm(struct bus *bus)
 675 {
 676         struct resource *min;
 677         uint32_t tolm;
 678         min = 0;
 679         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 680         tolm = 0xffffffffUL;
 681         if (min && tolm > min->base) {
 682                 tolm = min->base;
 683         }
 684         return tolm;
 685 }
 686
 687 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 688
 689 struct hw_mem_hole_info {
 690         unsigned hole_startk;
 691         int node_id;
 692 };
 693
 694 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 695 {
 696                 struct hw_mem_hole_info mem_hole;
 697                 int i;
 698
 699                 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
 700                 mem_hole.node_id = -1;
 701
 702                 for (i = 0; i < fx_devs; i++) {
 703                         uint32_t base;
 704                         uint32_t hole;
 705                         base  = f1_read_config32(0x40 + (i << 3));
 706                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 707                                 continue;
 708                         }
 709
 710                         hole = pci_read_config32(__f1_dev[i], 0xf0);
 711                         if(hole & 1) { // we find the hole
 712                                 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
 713                                 mem_hole.node_id = i; // record the node No with hole
 714                                 break; // only one hole
 715                         }
 716                 }
 717
 718                 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
 719                 if(mem_hole.node_id==-1) {
 720                         uint32_t limitk_pri = 0;
 721                         for(i=0; i<8; i++) {
 722                                 uint32_t base, limit;
 723                                 unsigned base_k, limit_k;
 724                                 base  = f1_read_config32(0x40 + (i << 3));
 725                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 726                                         continue;
 727                                 }
 728
 729                                 base_k = (base & 0xffff0000) >> 2;
 730                                 if(limitk_pri != base_k) { // we find the hole
 731                                         mem_hole.hole_startk = limitk_pri;
 732                                         mem_hole.node_id = i;
 733                                         break; //only one hole
 734                                 }
 735
 736                                 limit = f1_read_config32(0x44 + (i << 3));
 737                                 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 738                                 limitk_pri = limit_k;
 739                         }
 740                 }
 741
 742                 return mem_hole;
 743
 744 }
 745
 746 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 747 {
 748         int i;
 749         device_t dev;
 750         uint32_t base, limit;
 751         uint32_t hoist;
 752         uint32_t hole_sizek;
 753
 754
 755         //1. find which node has hole
 756         //2. change limit in that node.
 757         //3. change base and limit in later node
 758         //4. clear that node f0
 759
 760         //if there is not mem hole enabled, we need to change it's base instead
 761
 762         hole_sizek = (4*1024*1024) - hole_startk;
 763
 764         for(i=7;i>node_id;i--) {
 765
 766                 base  = f1_read_config32(0x40 + (i << 3));
 767                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 768                         continue;
 769                 }
 770                 limit = f1_read_config32(0x44 + (i << 3));
 771                 f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
 772                 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
 773         }
 774         limit = f1_read_config32(0x44 + (node_id << 3));
 775         f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
 776         dev = __f1_dev[node_id];
 777         if (dev == NULL) {
 778                 printk_err("%s: node %x is NULL!\n", __func__, node_id);
 779                 return;
 780         }
 781         hoist = pci_read_config32(dev, 0xf0);
 782         if(hoist & 1)
 783                 pci_write_config32(dev, 0xf0, 0);
 784         else {
 785                 base = pci_read_config32(dev, 0x40 + (node_id << 3));
 786                 f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
 787         }
 788 }
 789
 790 static uint32_t hoist_memory(unsigned long hole_startk, int node_id)
 791 {
 792         int i;
 793         uint32_t carry_over;
 794         device_t dev;
 795         uint32_t base, limit;
 796         uint32_t basek;
 797         uint32_t hoist;
 798
 799         carry_over = (4*1024*1024) - hole_startk;
 800
 801         for(i=7;i>node_id;i--) {
 802
 803                 base  = f1_read_config32(0x40 + (i << 3));
 804                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 805                         continue;
 806                 }
 807                 limit = f1_read_config32(0x44 + (i << 3));
 808                 f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
 809                 f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
 810         }
 811         limit = f1_read_config32(0x44 + (node_id << 3));
 812         f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
 813         dev = __f1_dev[node_id];
 814         base  = pci_read_config32(dev, 0x40 + (node_id << 3));
 815         basek  = (base & 0xffff0000) >> 2;
 816         if(basek == hole_startk) {
 817                 //don't need set memhole here, because hole off set will be 0, overflow
 818                 //so need to change base reg instead, new basek will be 4*1024*1024
 819                 base &= 0x0000ffff;
 820                 base |= (4*1024*1024)<<2;
 821                 f1_write_config32(0x40 + (node_id<<3), base);
 822         }
 823         else if (dev)
 824         {
 825                 hoist = /* hole start address */
 826                         ((hole_startk << 10) & 0xff000000) +
 827                         /* hole address to memory controller address */
 828                         (((basek + carry_over) >> 6) & 0x0000ff00) +
 829                         /* enable */
 830                         1;
 831
 832                 pci_write_config32(dev, 0xf0, hoist);
 833         }
 834
 835         return carry_over;
 836 }
 837 #endif
 838
 839 #if CONFIG_WRITE_HIGH_TABLES==1
 840 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
 841 extern uint64_t high_tables_base, high_tables_size;
 842 #endif
 843
 844 static void amdk8_domain_set_resources(device_t dev)
 845 {
 846 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 847         struct resource *io, *mem1, *mem2;
 848         struct resource *resource, *last;
 849 #endif
 850         unsigned long mmio_basek;
 851         uint32_t pci_tolm;
 852         int i, idx;
 853 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 854         struct hw_mem_hole_info mem_hole;
 855         unsigned reset_memhole = 1;
 856 #endif
 857
 858 #if 0
 859         /* Place the IO devices somewhere safe */
 860         io = find_resource(dev, 0);
 861         io->base = DEVICE_IO_START;
 862 #endif
 863 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 864         /* Now reallocate the pci resources memory with the
 865          * highest addresses I can manage.
 866          */
 867         mem1 = find_resource(dev, 1);
 868         mem2 = find_resource(dev, 2);
 869
 870 #if 1
 871         printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 872                 mem1->base, mem1->limit, mem1->size, mem1->align);
 873         printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 874                 mem2->base, mem2->limit, mem2->size, mem2->align);
 875 #endif
 876
 877         /* See if both resources have roughly the same limits */
 878         if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
 879                 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
 880         {
 881                 /* If so place the one with the most stringent alignment first
 882                  */
 883                 if (mem2->align > mem1->align) {
 884                         struct resource *tmp;
 885                         tmp = mem1;
 886                         mem1 = mem2;
 887                         mem2 = tmp;
 888                 }
 889                 /* Now place the memory as high up as it will go */
 890                 mem2->base = resource_max(mem2);
 891                 mem1->limit = mem2->base - 1;
 892                 mem1->base = resource_max(mem1);
 893         }
 894         else {
 895                 /* Place the resources as high up as they will go */
 896                 mem2->base = resource_max(mem2);
 897                 mem1->base = resource_max(mem1);
 898         }
 899
 900 #if 1
 901         printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 902                 mem1->base, mem1->limit, mem1->size, mem1->align);
 903         printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 904                 mem2->base, mem2->limit, mem2->size, mem2->align);
 905 #endif
 906
 907         last = &dev->resource[dev->resources];
 908         for(resource = &dev->resource[0]; resource < last; resource++)
 909         {
 910                 resource->flags |= IORESOURCE_ASSIGNED;
 911                 resource->flags |= IORESOURCE_STORED;
 912                 report_resource_stored(dev, resource, "");
 913
 914         }
 915 #endif
 916
 917
 918         pci_tolm = find_pci_tolm(&dev->link[0]);
 919
 920 #warning "FIXME handle interleaved nodes"
 921         mmio_basek = pci_tolm >> 10;
 922         /* Round mmio_basek to something the processor can support */
 923         mmio_basek &= ~((1 << 6) -1);
 924
 925 #if 1
 926 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
 927         /* Round the mmio hold to 64M */
 928         mmio_basek &= ~((64*1024) - 1);
 929 #endif
 930
 931 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 932         /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
 933          * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
 934          * otherwise We reset the hole to the mmio_basek
 935          */
 936         #if CONFIG_K8_REV_F_SUPPORT == 0
 937                 if (!is_cpu_pre_e0()) {
 938         #endif
 939
 940                 mem_hole = get_hw_mem_hole_info();
 941
 942                 if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
 943                         mmio_basek = mem_hole.hole_startk;
 944                         reset_memhole = 0;
 945                 }
 946
 947                 //mmio_basek = 3*1024*1024; // for debug to meet boundary
 948
 949                 if(reset_memhole) {
 950                         if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
 951                                // We need to reset our Mem Hole, because We want more big HOLE than we already set
 952                                //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
 953                                 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
 954                         }
 955
 956                 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
 957                         //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
 958                         uint32_t basek_pri;
 959                         for (i = 0; i < fx_devs; i++) {
 960                                 uint32_t base;
 961                                 uint32_t basek;
 962                                 base  = f1_read_config32(0x40 + (i << 3));
 963                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 964                                         continue;
 965                                 }
 966
 967                                 basek = (base & 0xffff0000) >> 2;
 968                                 if(mmio_basek == basek) {
 969                                         mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
 970                                         break;
 971                                 }
 972                                 basek_pri = basek;
 973                         }
 974                 #endif
 975                 }
 976
 977 #if CONFIG_K8_REV_F_SUPPORT == 0
 978         } // is_cpu_pre_e0
 979 #endif
 980
 981 #endif
 982
 983         idx = 0x10;
 984         for(i = 0; i < fx_devs; i++) {
 985                 uint32_t base, limit;
 986                 unsigned basek, limitk, sizek;
 987                 base  = f1_read_config32(0x40 + (i << 3));
 988                 limit = f1_read_config32(0x44 + (i << 3));
 989                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 990                         continue;
 991                 }
 992                 basek = (base & 0xffff0000) >> 2;
 993                 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
 994                 sizek = limitk - basek;
 995
 996                 /* see if we need a hole from 0xa0000 to 0xbffff */
 997                 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
 998                         ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
 999                         idx += 0x10;
1000                         basek = (8*64)+(16*16);
1001                         sizek = limitk - ((8*64)+(16*16));
1002
1003                 }
1004
1005
1006 //              printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1007
1008                 /* See if I need to split the region to accomodate pci memory space */
1009                 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1010                         if (basek <= mmio_basek) {
1011                                 unsigned pre_sizek;
1012                                 pre_sizek = mmio_basek - basek;
1013                                 if(pre_sizek>0) {
1014                                         ram_resource(dev, (idx | i), basek, pre_sizek);
1015                                         idx += 0x10;
1016                                         sizek -= pre_sizek;
1017 #if CONFIG_WRITE_HIGH_TABLES==1
1018                                         if (i==0 && high_tables_base==0) {
1019                                         /* Leave some space for ACPI, PIRQ and MP tables */
1020                                                 high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
1021                                                 high_tables_size = HIGH_TABLES_SIZE * 1024;
1022                                                 printk_debug(" split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
1023                                                              high_tables_base);
1024                                         }
1025 #endif
1026                                 }
1027                                 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1028                                 if(reset_memhole)
1029                                         #if CONFIG_K8_REV_F_SUPPORT == 0
1030                                         if(!is_cpu_pre_e0() )
1031                                         #endif
1032                                                  sizek += hoist_memory(mmio_basek,i);
1033                                 #endif
1034
1035                                 basek = mmio_basek;
1036                         }
1037                         if ((basek + sizek) <= 4*1024*1024) {
1038                                 sizek = 0;
1039                         }
1040                         else {
1041                                 basek = 4*1024*1024;
1042                                 sizek -= (4*1024*1024 - mmio_basek);
1043                         }
1044                 }
1045                 /* If sizek == 0, it was split at mmio_basek without a hole.
1046                  * Don't create an empty ram_resource.
1047                  */
1048                 if (sizek)
1049                         ram_resource(dev, (idx | i), basek, sizek);
1050                 idx += 0x10;
1051 #if CONFIG_WRITE_HIGH_TABLES==1
1052                 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
1053                              i, mmio_basek, basek, limitk);
1054                 if (i==0 && high_tables_base==0) {
1055                 /* Leave some space for ACPI, PIRQ and MP tables */
1056                         high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
1057                         high_tables_size = HIGH_TABLES_SIZE * 1024;
1058                 }
1059 #endif
1060         }
1061         assign_resources(&dev->link[0]);
1062
1063 }
1064
1065 static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
1066 {
1067         unsigned reg;
1068         int i;
1069         /* Unmap all of the HT chains */
1070         for(reg = 0xe0; reg <= 0xec; reg += 4) {
1071                 f1_write_config32(reg, 0);
1072         }
1073         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
1074
1075         /* Tune the hypertransport transaction for best performance.
1076          * Including enabling relaxed ordering if it is safe.
1077          */
1078         get_fx_devs();
1079         for(i = 0; i < fx_devs; i++) {
1080                 device_t f0_dev;
1081                 f0_dev = __f0_dev[i];
1082                 if (f0_dev && f0_dev->enabled) {
1083                         uint32_t httc;
1084                         httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1085                         httc &= ~HTTC_RSP_PASS_PW;
1086                         if (!dev->link[0].disable_relaxed_ordering) {
1087                                 httc |= HTTC_RSP_PASS_PW;
1088                         }
1089                         printk_spew("%s passpw: %s\n",
1090                                 dev_path(dev),
1091                                 (!dev->link[0].disable_relaxed_ordering)?
1092                                 "enabled":"disabled");
1093                         pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1094                 }
1095         }
1096         return max;
1097 }
1098
1099 static struct device_operations pci_domain_ops = {
1100         .read_resources   = amdk8_domain_read_resources,
1101         .set_resources    = amdk8_domain_set_resources,
1102         .enable_resources = enable_childrens_resources,
1103         .init             = 0,
1104         .scan_bus         = amdk8_domain_scan_bus,
1105         .ops_pci_bus      = &pci_cf8_conf1,
1106 };
1107
1108 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
1109 {
1110         struct bus *cpu_bus;
1111         device_t dev_mc;
1112         int bsp_apicid;
1113         int i,j;
1114         unsigned nb_cfg_54;
1115         unsigned siblings;
1116         int e0_later_single_core;
1117         int disable_siblings;
1118
1119         nb_cfg_54 = 0;
1120         sysconf.enabled_apic_ext_id = 0;
1121         sysconf.lift_bsp_apicid = 0;
1122         siblings = 0;
1123
1124         /* Find the bootstrap processors apicid */
1125         bsp_apicid = lapicid();
1126         sysconf.apicid_offset = bsp_apicid;
1127
1128         disable_siblings = !CONFIG_LOGICAL_CPUS;
1129 #if CONFIG_LOGICAL_CPUS == 1
1130         get_option(&disable_siblings, "dual_core");
1131 #endif
1132
1133         // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
1134         // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
1135
1136         nb_cfg_54 = read_nb_cfg_54();
1137
1138         dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1139         if (!dev_mc) {
1140                 die("0:18.0 not found?");
1141         }
1142
1143         sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1144
1145
1146         if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1147         {
1148                 sysconf.enabled_apic_ext_id = 1;
1149                 if(bsp_apicid == 0) {
1150                         /* bsp apic id is not changed */
1151                         sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
1152                 } else
1153                 {
1154                         sysconf.lift_bsp_apicid = 1;
1155                 }
1156
1157         }
1158
1159         /* Find which cpus are present */
1160         cpu_bus = &dev->link[0];
1161         for(i = 0; i < sysconf.nodes; i++) {
1162                 device_t cpu_dev, cpu;
1163                 struct device_path cpu_path;
1164
1165                 /* Find the cpu's pci device */
1166                 cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1167                 if (!cpu_dev) {
1168                         /* If I am probing things in a weird order
1169                          * ensure all of the cpu's pci devices are found.
1170                          */
1171                         int local_j;
1172                         device_t dev_f0;
1173                         for(local_j = 0; local_j <= 3; local_j++) {
1174                                 cpu_dev = pci_probe_dev(NULL, dev_mc->bus,
1175                                         PCI_DEVFN(0x18 + i, local_j));
1176                         }
1177                         /* Ok, We need to set the links for that device.
1178                          * otherwise the device under it will not be scanned
1179                          */
1180                         dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1181                         if(dev_f0) {
1182                                 dev_f0->links = 3;
1183                                 for(local_j=0;local_j<3;local_j++) {
1184                                         dev_f0->link[local_j].link = local_j;
1185                                         dev_f0->link[local_j].dev = dev_f0;
1186                                 }
1187                         }
1188
1189                 }
1190
1191                 e0_later_single_core = 0;
1192                 if (cpu_dev && cpu_dev->enabled) {
1193                         j = pci_read_config32(cpu_dev, 0xe8);
1194                         j = (j >> 12) & 3; // dev is func 3
1195                         printk_debug("  %s siblings=%d\n", dev_path(cpu_dev), j);
1196
1197                         if(nb_cfg_54) {
1198                                 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1199                                 //  ----> you can mixed single core e0 and dual core e0 at any sequence
1200                                 // That is the typical case
1201
1202                                 if(j == 0 ){
1203                                        #if CONFIG_K8_REV_F_SUPPORT == 0
1204                                         e0_later_single_core = is_e0_later_in_bsp(i);  // single core
1205                                        #else
1206                                         e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
1207                                        #endif
1208                                 } else {
1209                                        e0_later_single_core = 0;
1210                                 }
1211                                 if(e0_later_single_core) {
1212                                         printk_debug("\tFound Rev E or Rev F later single core\r\n");
1213
1214                                         j=1;
1215                                 }
1216
1217                                 if(siblings > j ) {
1218                                 }
1219                                 else {
1220                                         siblings = j;
1221                                 }
1222                         } else {
1223                                 siblings = j;
1224                         }
1225                 }
1226
1227                 unsigned jj;
1228                 if(e0_later_single_core || disable_siblings) {
1229                         jj = 0;
1230                 } else
1231                 {
1232                         jj = siblings;
1233                 }
1234 #if 0
1235                 jj = 0; // if create cpu core1 path in amd_siblings by core0
1236 #endif
1237
1238                 for (j = 0; j <=jj; j++ ) {
1239
1240                         /* Build the cpu device path */
1241                         cpu_path.type = DEVICE_PATH_APIC;
1242                         cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1243
1244                         /* See if I can find the cpu */
1245                         cpu = find_dev_path(cpu_bus, &cpu_path);
1246
1247                         /* Enable the cpu if I have the processor */
1248                         if (cpu_dev && cpu_dev->enabled) {
1249                                 if (!cpu) {
1250                                         cpu = alloc_dev(cpu_bus, &cpu_path);
1251                                 }
1252                                 if (cpu) {
1253                                         cpu->enabled = 1;
1254                                 }
1255                         }
1256
1257                         /* Disable the cpu if I don't have the processor */
1258                         if (cpu && (!cpu_dev || !cpu_dev->enabled)) {
1259                                 cpu->enabled = 0;
1260                         }
1261
1262                         /* Report what I have done */
1263                         if (cpu) {
1264                                 cpu->path.apic.node_id = i;
1265                                 cpu->path.apic.core_id = j;
1266                                 if(sysconf.enabled_apic_ext_id) {
1267                                         if(sysconf.lift_bsp_apicid) {
1268                                                 cpu->path.apic.apic_id += sysconf.apicid_offset;
1269                                         } else
1270                                         {
1271                                                if (cpu->path.apic.apic_id != 0)
1272                                                        cpu->path.apic.apic_id += sysconf.apicid_offset;
1273                                         }
1274                                 }
1275                                 printk_debug("CPU: %s %s\n",
1276                                         dev_path(cpu), cpu->enabled?"enabled":"disabled");
1277                         }
1278
1279                 } //j
1280         }
1281         return max;
1282 }
1283
1284 static void cpu_bus_init(device_t dev)
1285 {
1286         initialize_cpus(&dev->link[0]);
1287 }
1288
1289 static void cpu_bus_noop(device_t dev)
1290 {
1291 }
1292
1293 static struct device_operations cpu_bus_ops = {
1294         .read_resources   = cpu_bus_noop,
1295         .set_resources    = cpu_bus_noop,
1296         .enable_resources = cpu_bus_noop,
1297         .init             = cpu_bus_init,
1298         .scan_bus         = cpu_bus_scan,
1299 };
1300
1301 static void root_complex_enable_dev(struct device *dev)
1302 {
1303         /* Set the operations if it is a special bus type */
1304         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1305                 dev->ops = &pci_domain_ops;
1306         }
1307         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1308                 dev->ops = &cpu_bus_ops;
1309         }
1310 }
1311
1312 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1313         CHIP_NAME("AMD K8 Root Complex")
1314         .enable_dev = root_complex_enable_dev,
1315 };