1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/hypertransport.h>
13 #include "northbridge.h"
16 #define DEVICE_MEM_HIGH 0xFEC00000ULL /* Reserve 20M for the system */
17 #define DEVICE_IO_START 0x1000
20 static device_t __f0_dev[FX_DEVS];
21 static device_t __f1_dev[FX_DEVS];
24 static void debug_fx_devs(void)
27 for(i = 0; i < FX_DEVS; i++) {
31 printk_debug("__f0_dev[%d]: %s bus: %p\n",
32 i, dev_path(dev), dev->bus);
36 printk_debug("__f1_dev[%d]: %s bus: %p\n",
37 i, dev_path(dev), dev->bus);
43 static void get_fx_devs(void)
49 for(i = 0; i < FX_DEVS; i++) {
50 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
51 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
54 die("Cannot find 0:0x18.1\n");
58 static uint32_t f1_read_config32(unsigned reg)
61 return pci_read_config32(__f1_dev[0], reg);
64 static void f1_write_config32(unsigned reg, uint32_t value)
68 for(i = 0; i < FX_DEVS; i++) {
71 if (dev && dev->enabled) {
72 pci_write_config32(dev, reg, value);
77 static unsigned int amdk8_nodeid(device_t dev)
79 return (dev->path.u.pci.devfn >> 3) - 0x18;
82 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
86 nodeid = amdk8_nodeid(dev);
88 printk_debug("%s amdk8_scan_chains max: %d starting...\n",
91 for(link = 0; link < dev->links; link++) {
93 uint32_t busses, config_busses;
94 unsigned free_reg, config_reg;
95 dev->link[link].cap = 0x80 + (link *0x20);
97 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
98 } while(link_type & ConnectionPending);
99 if (!(link_type & LinkConnected)) {
103 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
104 } while(!(link_type & InitComplete));
105 if (!(link_type & NonCoherent)) {
108 /* See if there is an available configuration space mapping register in function 1. */
110 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
112 config = f1_read_config32(config_reg);
113 if (!free_reg && ((config & 3) == 0)) {
114 free_reg = config_reg;
117 if (((config & 3) == 3) &&
118 (((config >> 4) & 7) == nodeid) &&
119 (((config >> 8) & 3) == link)) {
123 if (free_reg && (config_reg > 0xec)) {
124 config_reg = free_reg;
126 /* If we can't find an available configuration space mapping register skip this bus */
127 if (config_reg > 0xec) {
131 /* Set up the primary, secondary and subordinate bus numbers. We have
132 * no idea how many busses are behind this bridge yet, so we set the subordinate
133 * bus number to 0xff for the moment.
135 dev->link[link].secondary = ++max;
136 dev->link[link].subordinate = 0xff;
138 /* Read the existing primary/secondary/subordinate bus
139 * number configuration.
141 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
142 config_busses = f1_read_config32(config_reg);
144 /* Configure the bus numbers for this bridge: the configuration
145 * transactions will not be propagates by the bridge if it is not
146 * correctly configured
148 busses &= 0xff000000;
149 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
150 ((unsigned int)(dev->link[link].secondary) << 8) |
151 ((unsigned int)(dev->link[link].subordinate) << 16));
152 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
154 config_busses &= 0x000fc88;
156 (3 << 0) | /* rw enable, no device compare */
157 (( nodeid & 7) << 4) |
158 (( link & 3 ) << 8) |
159 ((dev->link[link].secondary) << 16) |
160 ((dev->link[link].subordinate) << 24);
161 f1_write_config32(config_reg, config_busses);
164 printk_debug("%s Hyper transport scan link: %d max: %d\n",
165 dev_path(dev), link, max);
167 /* Now we can scan all of the subordinate busses i.e. the chain on the hypertranport link */
168 max = hypertransport_scan_chain(&dev->link[link], max);
171 printk_debug("%s Hyper transport scan link: %d new max: %d\n",
172 dev_path(dev), link, max);
175 /* We know the number of busses behind this bridge. Set the subordinate
176 * bus number to it's real value
178 dev->link[link].subordinate = max;
179 busses = (busses & 0xff00ffff) |
180 ((unsigned int) (dev->link[link].subordinate) << 16);
181 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
183 config_busses = (config_busses & 0x00ffffff) | (dev->link[link].subordinate << 24);
184 f1_write_config32(config_reg, config_busses);
186 printk_debug("%s Hypertransport scan link: %d done\n",
187 dev_path(dev), link);
191 printk_debug("%s amdk8_scan_chains max: %d done\n",
197 static int reg_useable(unsigned reg,
198 device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
200 struct resource *res;
201 unsigned nodeid, link;
204 for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
206 dev = __f0_dev[nodeid];
207 for(link = 0; !res && (link < 3); link++) {
208 res = probe_resource(dev, 0x100 + (reg | link));
214 if ( (goal_link == (link - 1)) &&
215 (goal_nodeid == (nodeid - 1)) &&
221 printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
223 goal_nodeid, goal_link,
230 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
232 struct resource *resource;
233 unsigned free_reg, reg;
236 for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
238 result = reg_useable(reg, dev, nodeid, link);
240 /* I have been allocated this one */
243 else if (result > 1) {
244 /* I have a free register pair */
252 resource = new_resource(dev, 0x100 + (reg | link));
257 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
259 struct resource *resource;
260 unsigned free_reg, reg;
263 for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
265 result = reg_useable(reg, dev, nodeid, link);
267 /* I have been allocated this one */
270 else if (result > 1) {
271 /* I have a free register pair */
279 resource = new_resource(dev, 0x100 + (reg | link));
283 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
285 struct resource *resource;
287 /* Initialize the io space constraints on the current bus */
288 resource = amdk8_find_iopair(dev, nodeid, link);
292 resource->align = log2(HT_IO_HOST_ALIGN);
293 resource->gran = log2(HT_IO_HOST_ALIGN);
294 resource->limit = 0xffffUL;
295 resource->flags = IORESOURCE_IO;
296 compute_allocate_resource(&dev->link[link], resource,
297 IORESOURCE_IO, IORESOURCE_IO);
300 /* Initialize the prefetchable memory constraints on the current bus */
301 resource = amdk8_find_mempair(dev, nodeid, link);
305 resource->align = log2(HT_MEM_HOST_ALIGN);
306 resource->gran = log2(HT_MEM_HOST_ALIGN);
307 resource->limit = 0xffffffffffULL;
308 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
309 compute_allocate_resource(&dev->link[link], resource,
310 IORESOURCE_MEM | IORESOURCE_PREFETCH,
311 IORESOURCE_MEM | IORESOURCE_PREFETCH);
314 /* Initialize the memory constraints on the current bus */
315 resource = amdk8_find_mempair(dev, nodeid, link);
319 resource->align = log2(HT_MEM_HOST_ALIGN);
320 resource->gran = log2(HT_MEM_HOST_ALIGN);
321 resource->limit = 0xffffffffffULL;
322 resource->flags = IORESOURCE_MEM;
323 compute_allocate_resource(&dev->link[link], resource,
324 IORESOURCE_MEM | IORESOURCE_PREFETCH,
329 static void amdk8_read_resources(device_t dev)
331 unsigned nodeid, link;
332 nodeid = amdk8_nodeid(dev);
333 for(link = 0; link < dev->links; link++) {
334 if (dev->link[link].children) {
335 amdk8_link_read_bases(dev, nodeid, link);
340 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
342 resource_t rbase, rend;
346 /* Make certain the resource has actually been set */
347 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
351 /* If I have already stored this resource don't worry about it */
352 if (resource->flags & IORESOURCE_STORED) {
356 /* Only handle PCI memory and IO resources */
357 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
360 /* Ensure I am actually looking at a resource of function 1 */
361 if (resource->index < 0x100) {
364 /* Get the base address */
365 rbase = resource->base;
367 /* Get the limit (rounded up) */
368 rend = resource_end(resource);
370 /* Get the register and link */
371 reg = resource->index & 0xfc;
372 link = resource->index & 3;
374 if (resource->flags & IORESOURCE_IO) {
375 uint32_t base, limit;
376 compute_allocate_resource(&dev->link[link], resource,
377 IORESOURCE_IO, IORESOURCE_IO);
378 base = f1_read_config32(reg);
379 limit = f1_read_config32(reg + 0x4);
381 base |= rbase & 0x01fff000;
384 limit |= rend & 0x01fff000;
385 limit |= (link & 3) << 4;
386 limit |= (nodeid & 7);
388 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
389 base |= PCI_IO_BASE_VGA_EN;
391 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
392 base |= PCI_IO_BASE_NO_ISA;
395 f1_write_config32(reg + 0x4, limit);
396 f1_write_config32(reg, base);
398 else if (resource->flags & IORESOURCE_MEM) {
399 uint32_t base, limit;
400 compute_allocate_resource(&dev->link[link], resource,
401 IORESOURCE_MEM | IORESOURCE_PREFETCH,
402 resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
403 base = f1_read_config32(reg);
404 limit = f1_read_config32(reg + 0x4);
406 base |= (rbase >> 8) & 0xffffff00;
409 limit |= (rend >> 8) & 0xffffff00;
410 limit |= (link & 3) << 4;
411 limit |= (nodeid & 7);
412 f1_write_config32(reg + 0x4, limit);
413 f1_write_config32(reg, base);
415 resource->flags |= IORESOURCE_STORED;
416 sprintf(buf, " <node %d link %d>",
418 report_resource_stored(dev, resource, buf);
421 static void amdk8_set_resources(device_t dev)
423 unsigned nodeid, link;
426 /* Find the nodeid */
427 nodeid = amdk8_nodeid(dev);
429 /* Set each resource we have found */
430 for(i = 0; i < dev->resources; i++) {
431 amdk8_set_resource(dev, &dev->resource[i], nodeid);
434 for(link = 0; link < dev->links; link++) {
436 bus = &dev->link[link];
438 assign_resources(bus);
443 static void amdk8_enable_resources(device_t dev)
445 pci_dev_enable_resources(dev);
446 enable_childrens_resources(dev);
449 static void mcf0_control_init(struct device *dev)
454 printk_debug("NB: Function 0 Misc Control.. ");
457 /* improve latency and bandwith on HT */
458 cmd = pci_read_config32(dev, 0x68);
461 pci_write_config32(dev, 0x68, cmd );
465 /* over drive the ht port to 1000 Mhz */
466 cmd = pci_read_config32(dev, 0xa8);
469 pci_write_config32(dev, 0xdc, cmd );
471 printk_debug("done.\n");
474 static struct device_operations northbridge_operations = {
475 .read_resources = amdk8_read_resources,
476 .set_resources = amdk8_set_resources,
477 .enable_resources = amdk8_enable_resources,
478 .init = mcf0_control_init,
479 .scan_bus = amdk8_scan_chains,
485 static struct pci_driver mcf0_driver __pci_driver = {
486 .ops = &northbridge_operations,
487 .vendor = PCI_VENDOR_ID_AMD,
492 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
494 static void pci_domain_read_resources(device_t dev)
496 struct resource *resource;
499 /* Find the already assigned resource pairs */
501 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
502 uint32_t base, limit;
503 base = f1_read_config32(reg);
504 limit = f1_read_config32(reg + 0x04);
505 /* Is this register allocated? */
506 if ((base & 3) != 0) {
507 unsigned nodeid, link;
510 link = (limit >> 4) & 3;
511 dev = __f0_dev[nodeid];
513 /* Reserve the resource */
514 struct resource *resource;
515 resource = new_resource(dev, 0x100 + (reg | link));
523 /* Initialize the system wide io space constraints */
524 resource = new_resource(dev, 0);
525 resource->base = 0x400;
526 resource->limit = 0xffffUL;
527 resource->flags = IORESOURCE_IO;
528 compute_allocate_resource(&dev->link[0], resource,
529 IORESOURCE_IO, IORESOURCE_IO);
531 /* Initialize the system wide prefetchable memory resources constraints */
532 resource = new_resource(dev, 1);
533 resource->limit = 0xfcffffffffULL;
534 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
535 compute_allocate_resource(&dev->link[0], resource,
536 IORESOURCE_MEM | IORESOURCE_PREFETCH,
537 IORESOURCE_MEM | IORESOURCE_PREFETCH);
539 /* Initialize the system wide memory resources constraints */
540 resource = new_resource(dev, 2);
541 resource->limit = 0xfcffffffffULL;
542 resource->flags = IORESOURCE_MEM;
543 compute_allocate_resource(&dev->link[0], resource,
544 IORESOURCE_MEM | IORESOURCE_PREFETCH,
548 static void ram_resource(device_t dev, unsigned long index,
549 unsigned long basek, unsigned long sizek)
551 struct resource *resource;
556 resource = new_resource(dev, index);
557 resource->base = ((resource_t)basek) << 10;
558 resource->size = ((resource_t)sizek) << 10;
559 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
560 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
563 static void pci_domain_set_resources(device_t dev)
565 struct resource *io, *mem1, *mem2;
566 struct resource *resource, *last;
567 unsigned long mmio_basek;
572 /* Place the IO devices somewhere safe */
573 io = find_resource(dev, 0);
574 io->base = DEVICE_IO_START;
577 /* Now reallocate the pci resources memory with the
578 * highest addresses I can manage.
580 mem1 = find_resource(dev, 1);
581 mem2 = find_resource(dev, 2);
582 /* See if both resources have roughly the same limits */
583 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
584 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
586 /* If so place the one with the most stringent alignment first
588 if (mem2->align > mem1->align) {
589 struct resource *tmp;
594 /* Now place the memory as high up as it will go */
595 mem2->base = resource_max(mem2);
596 mem1->limit = mem2->base - 1;
597 mem1->base = resource_max(mem1);
600 /* Place the resources as high up as they will go */
601 mem2->base = resource_max(mem2);
602 mem1->base = resource_max(mem1);
606 printk_debug("base1: 0x%08Lx limit1: 0x%08lx size: 0x%08Lx\n",
607 mem1->base, mem1->limit, mem1->size);
608 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx\n",
609 mem2->base, mem2->limit, mem2->size);
612 pci_tolm = 0xffffffffUL;
613 last = &dev->resource[dev->resources];
614 for(resource = &dev->resource[0]; resource < last; resource++)
617 resource->flags |= IORESOURCE_ASSIGNED;
618 resource->flags &= ~IORESOURCE_STORED;
620 compute_allocate_resource(&dev->link[0], resource,
621 BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
623 resource->flags |= IORESOURCE_STORED;
624 report_resource_stored(dev, resource, "");
626 if ((resource->flags & IORESOURCE_MEM) &&
627 (pci_tolm > resource->base))
629 pci_tolm = resource->base;
633 #warning "FIXME handle interleaved nodes"
634 mmio_basek = pci_tolm >> 10;
635 /* Round mmio_basek to something the processor can support */
636 mmio_basek &= ~((1 << 6) -1);
639 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
640 /* Round the mmio hold to 64M */
641 mmio_basek &= ~((64*1024) - 1);
645 for(i = 0; i < 8; i++) {
646 uint32_t base, limit;
647 unsigned basek, limitk, sizek;
648 base = f1_read_config32(0x40 + (i << 3));
649 limit = f1_read_config32(0x44 + (i << 3));
650 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
653 basek = (base & 0xffff0000) >> 2;
654 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
655 sizek = limitk - basek;
657 /* see if we need a hole from 0xa0000 to 0xbffff */
658 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
659 ram_resource(dev, idx++, basek, ((8*64)+(8*16)) - basek);
660 basek = (8*64)+(16*16);
661 sizek = limitk - ((8*64)+(16*16));
666 /* See if I need to split the region to accomodate pci memory space */
667 if ((basek < mmio_basek) && (limitk > mmio_basek)) {
668 if (basek < mmio_basek) {
670 pre_sizek = mmio_basek - basek;
671 ram_resource(dev, idx++, basek, pre_sizek);
675 if ((basek + sizek) <= 4*1024*1024) {
680 sizek -= (4*1024*1024 - mmio_basek);
683 ram_resource(dev, idx++, basek, sizek);
686 assign_resources(&dev->link[0]);
689 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
693 /* Unmap all of the HT chains */
694 for(reg = 0xe0; reg <= 0xec; reg += 4) {
695 f1_write_config32(reg, 0);
697 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
701 static struct device_operations pci_domain_ops = {
702 .read_resources = pci_domain_read_resources,
703 .set_resources = pci_domain_set_resources,
704 .enable_resources = enable_childrens_resources,
706 .scan_bus = pci_domain_scan_bus,
709 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
715 /* Find which cpus are present */
716 cpu_bus = &dev->link[0];
717 for(i = 0; i < 7; i++) {
719 struct device_path cpu_path;
721 /* Find the cpu's memory controller */
722 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
724 /* Build the cpu device path */
725 cpu_path.type = DEVICE_PATH_APIC;
726 cpu_path.u.apic.apic_id = i;
728 /* See if I can find the cpu */
729 cpu = find_dev_path(cpu_bus, &cpu_path);
731 /* Enable the cpu if I have the processor */
732 if (dev && dev->enabled) {
734 cpu = alloc_dev(cpu_bus, &cpu_path);
741 /* Disable the cpu if I don't have the processor */
742 if (cpu && (!dev || !dev->enabled)) {
746 /* Report what I have done */
748 printk_debug("CPU: %s %s\n",
749 dev_path(cpu), cpu->enabled?"enabled":"disabled");
755 static void cpu_bus_init(device_t dev)
757 initialize_cpus(&dev->link[0]);
760 static void cpu_bus_noop(device_t dev)
764 static struct device_operations cpu_bus_ops = {
765 .read_resources = cpu_bus_noop,
766 .set_resources = cpu_bus_noop,
767 .enable_resources = cpu_bus_noop,
768 .init = cpu_bus_init,
769 .scan_bus = cpu_bus_scan,
772 static void enable_dev(struct device *dev)
774 struct device_path path;
776 /* Set the operations if it is a special bus type */
777 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
778 dev->ops = &pci_domain_ops;
780 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
781 dev->ops = &cpu_bus_ops;
785 struct chip_operations northbridge_amd_amdk8_ops = {
786 .name = "AMD K8 Northbridge",
787 .enable_dev = enable_dev,