2 This should be done by Eric
3 2004.12 yhlu add multi ht chain dynamically support
4 2005.11 yhlu add let real sb to use small unitid
6 #include <device/pci_def.h>
7 #include <device/pci_ids.h>
8 #include <device/hypertransport_def.h>
10 // Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
11 #ifndef K8_ALLOCATE_MMIO_RANGE
12 #define K8_ALLOCATE_MMIO_RANGE 0
15 static inline void print_linkn_in (const char *strval, uint8_t byteval)
17 printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
20 static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
25 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
29 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
30 (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
31 pos = PCI_CAPABILITY_LIST;
33 if (pos > PCI_CAP_LIST_NEXT) {
34 pos = pci_read_config8(dev, pos);
36 while(pos != 0) { /* loop through the linked list */
38 cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
39 if (cap == PCI_CAP_ID_HT) {
42 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
43 if ((flags >> 13) == val) {
44 /* Entry is a slave or host , success... */
48 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
53 static uint8_t ht_lookup_slave_capability(device_t dev)
55 return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
59 static uint8_t ht_lookup_host_capability(device_t dev)
61 return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
65 static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
69 //actually, only for one HT device HT chain, and unitid is 0
70 #if CONFIG_HT_CHAIN_UNITID_BASE == 0
76 /* Check if is already collapsed */
77 if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
79 dev = PCI_DEV(bus, 0, 0);
80 id = pci_read_config32(dev, PCI_VENDOR_ID);
81 if (!((id == 0xffffffff) || (id == 0x00000000) ||
82 (id == 0x0000ffff) || (id == 0xffff0000))) {
87 /* Spin through the devices and collapse any previous
88 * hypertransport enumeration.
90 for(dev = PCI_DEV(bus, 1, 0); dev <= PCI_DEV(bus, 0x1f, 0x7); dev += PCI_DEV(0, 1, 0)) {
95 id = pci_read_config32(dev, PCI_VENDOR_ID);
96 if ((id == 0xffffffff) || (id == 0x00000000) ||
97 (id == 0x0000ffff) || (id == 0xffff0000)) {
101 pos = ht_lookup_slave_capability(dev);
106 /* Clear the unitid */
107 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
109 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
113 static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
115 /* Handle bugs in valid hypertransport frequency reporting */
119 freq_cap = pci_read_config16(dev, pos);
120 printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap);
121 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
123 id = pci_read_config32(dev, 0);
125 /* AMD 8131 Errata 48 */
126 if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) {
127 freq_cap &= ~(1 << HT_FREQ_800Mhz);
131 /* AMD 8151 Errata 23 */
132 if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) {
133 freq_cap &= ~(1 << HT_FREQ_800Mhz);
137 /* AMD K8 Unsupported 1Ghz? */
138 if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
139 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
140 #if CONFIG_K8_REV_F_SUPPORT == 0
141 if (is_cpu_pre_e0()) { // only E0 later support 1GHz
142 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
146 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
150 printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
152 #if CONFIG_SOUTHBRIDGE_VIA_K8M890 == 1
154 printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
159 static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
161 uint8_t width_cap = pci_read_config8(dev, pos);
165 id = pci_read_config32(dev, 0);
167 /* netlogic micro cap doesn't support 16 bit yet */
168 if (id == (0x184e | (0x0001 << 16))) {
169 if((width_cap & 0x77) == 0x11) {
178 #define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \
179 (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
181 #define LINK_CTRL(OFFS) ((OFFS >> 24) & 0xFF)
182 #define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF)
183 #define LINK_FREQ(OFFS) ((OFFS >> 8) & 0xFF)
184 #define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
186 #define PCI_HT_HOST_OFFS LINK_OFFS( \
187 PCI_HT_CAP_HOST_CTRL, \
188 PCI_HT_CAP_HOST_WIDTH, \
189 PCI_HT_CAP_HOST_FREQ, \
190 PCI_HT_CAP_HOST_FREQ_CAP)
192 #define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
193 PCI_HT_CAP_SLAVE_CTRL0, \
194 PCI_HT_CAP_SLAVE_WIDTH0, \
195 PCI_HT_CAP_SLAVE_FREQ0, \
196 PCI_HT_CAP_SLAVE_FREQ_CAP0)
198 #define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
199 PCI_HT_CAP_SLAVE_CTRL1, \
200 PCI_HT_CAP_SLAVE_WIDTH1, \
201 PCI_HT_CAP_SLAVE_FREQ1, \
202 PCI_HT_CAP_SLAVE_FREQ_CAP1)
204 static int ht_optimize_link(
205 device_t dev1, uint8_t pos1, unsigned offs1,
206 device_t dev2, uint8_t pos2, unsigned offs2)
208 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
209 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
210 uint16_t freq_cap1, freq_cap2;
211 uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
212 uint8_t freq, old_freq;
214 /* Set link width and frequency */
216 printk(BIOS_SPEW, "entering ht_optimize_link\n");
217 /* Initially assume everything is already optimized and I don't need a reset */
220 /* Get the frequency capabilities */
221 freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
222 freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
223 printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2);
225 /* Calculate the highest possible frequency */
226 freq = log2(freq_cap1 & freq_cap2);
228 /* See if I am changing the link freqency */
229 old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
231 needs_reset |= old_freq != freq;
232 printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
233 old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
235 needs_reset |= old_freq != freq;
236 printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
238 /* Set the Calculated link frequency */
239 pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
240 pci_write_config8(dev2, pos2 + LINK_FREQ(offs2), freq);
242 /* Get the width capabilities */
243 width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
244 width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
245 printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2);
247 /* Calculate dev1's input width */
248 ln_width1 = link_width_to_pow2[width_cap1 & 7];
249 ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
250 printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
251 if (ln_width1 > ln_width2) {
252 ln_width1 = ln_width2;
254 width = pow2_to_link_width[ln_width1];
255 printk(BIOS_SPEW, "dev1 input width=0x%x\n", width);
256 /* Calculate dev1's output width */
257 ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
258 ln_width2 = link_width_to_pow2[width_cap2 & 7];
259 printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
260 if (ln_width1 > ln_width2) {
261 ln_width1 = ln_width2;
263 width |= pow2_to_link_width[ln_width1] << 4;
264 printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width);
266 /* See if I am changing dev1's width */
267 old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
269 needs_reset |= old_width != width;
270 printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width);
272 /* Set dev1's widths */
273 pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
275 /* Calculate dev2's width */
276 width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
277 printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width);
279 /* See if I am changing dev2's width */
280 old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
282 needs_reset |= old_width != width;
283 printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width);
285 /* Set dev2's widths */
286 pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
291 #if CONFIG_RAMINIT_SYSINFO
292 static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo)
294 static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid)
297 //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
299 uint8_t next_unitid, last_unitid;
302 #if !CONFIG_RAMINIT_SYSINFO
303 int reset_needed = 0;
306 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
307 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
308 unsigned real_last_unitid = 0;
309 uint8_t real_last_pos = 0;
311 uint8_t end_used = 0;
314 uoffs = PCI_HT_HOST_OFFS;
315 next_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
320 uint16_t flags, ctrl;
324 /* Wait until the link initialization is complete */
326 ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
327 /* Is this the end of the hypertransport chain? */
328 if (ctrl & (1 << 6)) {
332 if (ctrl & ((1 << 4) | (1 << 8))) {
334 * Either the link has failed, or we have
336 * Sometimes this can happen due to link
337 * retrain, so lets knock it down and see
340 ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
341 pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
342 ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
343 if (ctrl & ((1 << 4) | (1 << 8))) {
344 print_err("Detected error on Hypertransport Link\n");
348 } while((ctrl & (1 << 5)) == 0);
350 device_t dev = PCI_DEV(bus, 0, 0);
351 last_unitid = next_unitid;
353 id = pci_read_config32(dev, PCI_VENDOR_ID);
355 /* If the chain is enumerated quit */
356 if ((id == 0xffffffff) || (id == 0x00000000) ||
357 (id == 0x0000ffff) || (id == 0xffff0000))
362 pos = ht_lookup_slave_capability(dev);
364 print_err("udev="); print_err_hex32(udev);
365 print_err("\tupos="); print_err_hex32(upos);
366 print_err("\tuoffs="); print_err_hex32(uoffs);
367 print_err("\tHT link capability not found\n");
372 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
374 if(next_unitid>= (bus ? 0x20:0x18) ) {
376 next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
384 real_last_unitid = next_unitid;
388 /* Update the Unitid of the current device */
389 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
390 flags &= ~0x1f; /* mask out the base Unit ID */
391 flags |= next_unitid & 0x1f;
392 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
394 /* Compute the number of unitids consumed */
395 count = (flags >> 5) & 0x1f;
397 /* Note the change in device number */
398 dev = PCI_DEV(bus, next_unitid, 0);
400 next_unitid += count;
402 /* Find which side of the ht link we are on,
403 * by reading which direction our last write to PCI_CAP_FLAGS
406 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
407 offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
409 #if CONFIG_RAMINIT_SYSINFO
410 /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
412 struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
413 link_pair->udev = udev;
414 link_pair->upos = upos;
415 link_pair->uoffs = uoffs;
416 link_pair->dev = dev;
417 link_pair->pos = pos;
418 link_pair->offs = offs;
419 sysinfo->link_pair_num++;
422 reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, offs);
425 /* Remeber the location of the last device */
428 uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
430 } while (last_unitid != next_unitid );
432 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
437 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
438 if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
440 flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
442 flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
443 pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
445 #if CONFIG_RAMINIT_SYSINFO
446 // Here need to change the dev in the array
448 for(i=0;i<sysinfo->link_pair_num;i++)
450 struct link_pair_st *link_pair = &sysinfo->link_pair[i];
451 if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
452 link_pair->udev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0);
455 if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) {
456 link_pair->dev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0);
464 #if !CONFIG_RAMINIT_SYSINFO
471 #if CONFIG_RAMINIT_SYSINFO
472 static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo)
474 static int ht_setup_chain(device_t udev, unsigned upos)
477 unsigned offset_unitid = 0;
478 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
482 /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
483 * On most boards this just happens. If a cpu has multiple
484 * non Coherent links the appropriate bus registers for the
485 * links needs to be programed to point at bus 0.
488 /* Make certain the HT bus is not enumerated */
489 ht_collapse_previous_enumeration(0, 0);
491 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
495 #if CONFIG_RAMINIT_SYSINFO
496 ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
498 return ht_setup_chainx(udev, upos, 0, offset_unitid);
503 static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
505 uint32_t dword, dword_old;
508 /* This works on an Athlon64 because unimplemented links return 0 */
509 dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20));
510 link_type = dword & 0xff;
513 if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
514 dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc);
515 dword &= ~( 0xff<<(linkn *8) );
516 dword |= val << (linkn *8);
518 if (dword != dword_old) {
519 pci_write_config32(PCI_DEV(0,0x18+node,3), 0xdc, dword);
527 static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
534 for (i = 0; i < ht_c_num; i++) {
536 uint8_t nodeid, linkn;
541 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
542 #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
543 if(i==0) // to check if it is sb ht chain
545 devn = CONFIG_HT_CHAIN_UNITID_BASE;
548 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
550 nodeid = ((reg & 0xf0)>>4); // nodeid
551 linkn = ((reg & 0xf00)>>8); // link n
552 busn = (reg & 0xff0000)>>16; //busn
554 reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted
555 if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) {
557 } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) {
563 reset_needed |= optimize_link_read_pointer(nodeid, linkn, 0x07, val);
570 #if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55
571 static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
578 /* This works on an Athlon64 because unimplemented links return 0 */
579 regpos = 0x98 + (linkn * 0x20);
580 dev = PCI_DEV(0,0x18+node,0);
581 dword = pci_read_config32(dev, regpos);
582 link_type = dword & 0xff;
584 if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
585 regpos = 0x90 + (linkn * 0x20);
586 dword = pci_read_config32(dev, regpos );
589 pci_write_config32(dev, regpos, val);
597 static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val)
604 for (i = 0; i < ht_c_num; i++) {
606 uint8_t nodeid, linkn;
610 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
611 if((reg & 3) != 3) continue; // not enabled
613 nodeid = ((reg & 0xf0)>>4); // nodeid
614 linkn = ((reg & 0xf00)>>8); // link n
615 busn = (reg & 0xff0000)>>16; //busn
617 for(devn = 0; devn < 0x20; devn++) {
618 reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
619 if ( (reg & 0xffff) == vendorid ) {
620 reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
630 #if CONFIG_RAMINIT_SYSINFO
631 static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
633 static int ht_setup_chains(uint8_t ht_c_num)
636 /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
637 * On most boards this just happens. If a cpu has multiple
638 * non Coherent links the appropriate bus registers for the
639 * links needs to be programed to point at bus 0.
645 #if !CONFIG_RAMINIT_SYSINFO
646 int reset_needed = 0;
648 sysinfo->link_pair_num = 0;
651 // first one is SB Chain
652 for (i = 0; i < ht_c_num; i++) {
658 unsigned offset_unitid = 0;
660 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
662 //We need setup 0x94, 0xb4, and 0xd4 according to the reg
663 devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19
664 regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
665 busn = (reg & 0xff0000)>>16;
667 dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ;
668 dword &= ~(0xffff<<8);
669 dword |= (reg & 0xffff0000)>>8;
670 pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
673 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
674 #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
675 if(i==0) // to check if it is sb ht chain
680 /* Make certain the HT bus is not enumerated */
681 ht_collapse_previous_enumeration(busn, offset_unitid);
683 upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
684 udev = PCI_DEV(0, devpos, 0);
686 #if CONFIG_RAMINIT_SYSINFO
687 ht_setup_chainx(udev,upos,busn, offset_unitid, sysinfo); // all not
689 reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not
694 #if !CONFIG_RAMINIT_SYSINFO
695 reset_needed |= optimize_link_read_pointers_chain(ht_c_num);
702 #if defined (__GNUC__)
703 static inline unsigned get_nodes(void);
706 #if CONFIG_RAMINIT_SYSINFO
707 static void ht_setup_chains_x(struct sys_info *sysinfo)
709 static int ht_setup_chains_x(void)
718 #if CONFIG_K8_ALLOCATE_IO_RANGE
719 unsigned next_io_base;
724 /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
725 reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
726 /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
727 print_linkn_in("SBLink=", ((reg>>8) & 3) );
728 #if CONFIG_RAMINIT_SYSINFO
729 sysinfo->sblk = (reg>>8) & 3;
731 sysinfo->nodes = nodes;
733 tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
734 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
736 next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
738 #if CONFIG_K8_ALLOCATE_IO_RANGE
739 /* io range allocation */
740 tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit
741 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
742 tempreg = 3 | ( 3<<4) | (0<<12); //base
743 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0, tempreg);
744 next_io_base = 0x3+0x1;
748 for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
749 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
751 #if CONFIG_K8_ALLOCATE_IO_RANGE
752 /* io range allocation */
753 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
754 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
758 for(nodeid=0; nodeid<nodes; nodeid++) {
761 dev = PCI_DEV(0, 0x18+nodeid,0);
762 for(linkn = 0; linkn<3; linkn++) {
764 regpos = 0x98 + 0x20 * linkn;
765 reg = pci_read_config32(dev, regpos);
766 if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
767 print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
768 tempreg = 3 | (nodeid <<4) | (linkn<<8);
769 /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
770 for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
771 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
772 if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
776 if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
777 /*update to 0xe0...*/
778 if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */
779 print_linkn_in("\tbusn=", next_busn);
780 tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
781 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
784 #if CONFIG_K8_ALLOCATE_IO_RANGE
785 /* io range allocation */
786 tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
787 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
788 tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
789 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
790 next_io_base += 0x3+0x1;
795 /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
797 for(nodeid = 1; nodeid<nodes; nodeid++) {
800 dev = PCI_DEV(0, 0x18+nodeid,1);
801 for(i = 0; i< 4; i++) {
803 regpos = 0xe0 + i * 4;
804 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
805 pci_write_config32(dev, regpos, reg);
808 #if CONFIG_K8_ALLOCATE_IO_RANGE
809 /* io range allocation */
810 for(i = 0; i< 4; i++) {
812 regpos = 0xc4 + i * 8;
813 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
814 pci_write_config32(dev, regpos, reg);
816 for(i = 0; i< 4; i++) {
818 regpos = 0xc0 + i * 8;
819 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
820 pci_write_config32(dev, regpos, reg);
825 /* recount ht_c_num*/
827 for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
828 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
829 if(((reg & 0xf) != 0x0)) {
834 #if CONFIG_RAMINIT_SYSINFO
835 sysinfo->ht_c_num = i;
836 ht_setup_chains(i, sysinfo);
837 sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
839 return ht_setup_chains(i);
844 #if CONFIG_RAMINIT_SYSINFO
845 static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
847 // We need to use recorded link pair info to optimize the link
849 int reset_needed = 0;
851 unsigned link_pair_num = sysinfo->link_pair_num;
853 printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n");
854 printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num);
855 for(i=0; i< link_pair_num; i++) {
856 struct link_pair_st *link_pair= &sysinfo->link_pair[i];
857 reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
858 printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed);
861 reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
862 printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed);