1 #include <device/pci_def.h>
2 #include <device/pci_ids.h>
3 #include <device/hypertransport_def.h>
5 static unsigned ht_lookup_slave_capability(device_t dev)
10 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
14 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
15 (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
16 pos = PCI_CAPABILITY_LIST;
18 if (pos > PCI_CAP_LIST_NEXT) {
19 pos = pci_read_config8(dev, pos);
21 while(pos != 0) { /* loop through the linked list */
23 cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
24 if (cap == PCI_CAP_ID_HT) {
27 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
28 if ((flags >> 13) == 0) {
29 /* Entry is a Slave secondary, success... */
33 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
38 static void ht_collapse_previous_enumeration(unsigned bus)
42 /* Spin through the devices and collapse any previous
43 * hypertransport enumeration.
45 for(dev = PCI_DEV(bus, 0, 0); dev <= PCI_DEV(bus, 0x1f, 0x7); dev += PCI_DEV(0, 1, 0)) {
49 id = pci_read_config32(dev, PCI_VENDOR_ID);
50 if ((id == 0xffffffff) || (id == 0x00000000) ||
51 (id == 0x0000ffff) || (id == 0xffff0000)) {
54 pos = ht_lookup_slave_capability(dev);
59 /* Clear the unitid */
60 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
62 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
67 static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
69 /* Handle bugs in valid hypertransport frequency reporting */
73 freq_cap = pci_read_config16(dev, pos);
74 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
76 id = pci_read_config32(dev, 0);
78 /* AMD 8131 Errata 48 */
79 if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) {
80 freq_cap &= ~(1 << HT_FREQ_800Mhz);
82 /* AMD 8151 Errata 23 */
83 if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) {
84 freq_cap &= ~(1 << HT_FREQ_800Mhz);
86 /* AMD K8 Unsupported 1Ghz? */
87 if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
88 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
93 #define LINK_OFFS(WIDTH,FREQ,FREQ_CAP) \
94 (((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
96 #define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF)
97 #define LINK_FREQ(OFFS) ((OFFS >> 8) & 0xFF)
98 #define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
100 #define PCI_HT_HOST_OFFS LINK_OFFS( \
101 PCI_HT_CAP_HOST_WIDTH, \
102 PCI_HT_CAP_HOST_FREQ, \
103 PCI_HT_CAP_HOST_FREQ_CAP)
105 #define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
106 PCI_HT_CAP_SLAVE_WIDTH0, \
107 PCI_HT_CAP_SLAVE_FREQ0, \
108 PCI_HT_CAP_SLAVE_FREQ_CAP0)
110 #define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
111 PCI_HT_CAP_SLAVE_WIDTH1, \
112 PCI_HT_CAP_SLAVE_FREQ1, \
113 PCI_HT_CAP_SLAVE_FREQ_CAP1)
115 static int ht_optimize_link(
116 device_t dev1, uint8_t pos1, unsigned offs1,
117 device_t dev2, uint8_t pos2, unsigned offs2)
119 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
120 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
121 uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask;
122 uint8_t width_cap1, width_cap2, width_cap, width, old_width, ln_width1, ln_width2;
123 uint8_t freq, old_freq;
125 /* Set link width and frequency */
127 /* Initially assume everything is already optimized and I don't need a reset */
130 /* Get the frequency capabilities */
131 freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
132 freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
134 /* Calculate the highest possible frequency */
135 freq = log2(freq_cap1 & freq_cap2);
137 /* See if I am changing the link freqency */
138 old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
139 needs_reset |= old_freq != freq;
140 old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
141 needs_reset |= old_freq != freq;
143 /* Set the Calulcated link frequency */
144 pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
145 pci_write_config8(dev2, pos2 + LINK_FREQ(offs2), freq);
147 /* Get the width capabilities */
148 width_cap1 = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1));
149 width_cap2 = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2));
151 /* Calculate dev1's input width */
152 ln_width1 = link_width_to_pow2[width_cap1 & 7];
153 ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
154 if (ln_width1 > ln_width2) {
155 ln_width1 = ln_width2;
157 width = pow2_to_link_width[ln_width1];
158 /* Calculate dev1's output width */
159 ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
160 ln_width2 = link_width_to_pow2[width_cap2 & 7];
161 if (ln_width1 > ln_width2) {
162 ln_width1 = ln_width2;
164 width |= pow2_to_link_width[ln_width1] << 4;
166 /* See if I am changing dev1's width */
167 old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
168 needs_reset |= old_width != width;
170 /* Set dev1's widths */
171 pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
173 /* Calculate dev2's width */
174 width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
176 /* See if I am changing dev2's width */
177 old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
178 needs_reset |= old_width != width;
180 /* Set dev2's widths */
181 pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
186 static int ht_setup_chain(device_t udev, unsigned upos)
188 /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
189 * On most boards this just happens. If a cpu has multiple
190 * non Coherent links the appropriate bus registers for the
191 * links needs to be programed to point at bus 0.
193 unsigned next_unitid, last_unitid;
197 #warning "FIXME handle multiple chains!"
199 /* Make certain the HT bus is not enumerated */
200 ht_collapse_previous_enumeration(0);
203 uoffs = PCI_HT_HOST_OFFS;
208 unsigned flags, count;
209 device_t dev = PCI_DEV(0, 0, 0);
210 last_unitid = next_unitid;
212 id = pci_read_config32(dev, PCI_VENDOR_ID);
213 /* If the chain is enumerated quit */
214 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
215 (((id >> 16) & 0xffff) == 0xffff) ||
216 (((id >> 16) & 0xffff) == 0x0000)) {
219 pos = ht_lookup_slave_capability(dev);
221 print_err("HT link capability not found\r\n");
224 /* Setup the Hypertransport link */
225 reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
227 /* Update the Unitid of the current device */
228 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
229 flags &= ~0x1f; /* mask out the bse Unit ID */
230 flags |= next_unitid & 0x1f;
231 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
233 /* Remeber the location of the last device */
234 udev = PCI_DEV(0, next_unitid, 0);
236 uoffs = PCI_HT_SLAVE1_OFFS;
238 /* Compute the number of unitids consumed */
239 count = (flags >> 5) & 0x1f;
240 next_unitid += count;
242 } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));