2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 void exit_from_self(int controllers, const struct mem_controller *ctrl,
23 struct sys_info *sysinfo)
32 for (i = 0; i < controllers; i++) {
33 if (!sysinfo->ctrl_present[i])
35 /* Skip everything if I don't have any memory on this controller */
36 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
37 if (!(dch & DCH_MemClkFreqVal)) {
41 local_cpuid = pci_read_config32(ctrl[i].f3, 0xfc);
42 is_post_rev_g = ((local_cpuid & 0xfff00) > 0x50f00);
45 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
46 if (dcl & DCL_DimmEccEn) {
48 printk(BIOS_SPEW, "ECC enabled\n");
49 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
51 if (dcl & DCL_Width128) {
52 mnc |= MNC_CHIPKILL_EN;
54 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
57 printk(BIOS_DEBUG, "before resume errata #%d\n",
58 (is_post_rev_g) ? 270 : 125);
60 1. Restore memory controller registers as normal.
61 2. Set the DisAutoRefresh bit (Dev:2x8C[18]). (270 only)
62 3. Set the EnDramInit bit (Dev:2x7C[31]), clear all other bits in the same register).
63 4. Wait at least 750 us.
64 5. Clear the EnDramInit bit.
65 6. Clear the DisAutoRefresh bit. (270 only)
66 7. Read the value of Dev:2x80 and write that value back to Dev:2x80.
67 8. Set the exit from the self refresh bit (Dev:2x90[1]).
68 9. Clear the exit from self refresh bit immediately.
69 Note: Steps 8 and 9 must be executed in a single 64-byte aligned uninterrupted instruction stream.
75 printk(BIOS_DEBUG, "before exit errata - timer enabled\n");
79 pci_read_config32(ctrl[i].f2,
82 pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
87 pci_write_config32(ctrl[i].f2, DRAM_INIT, dcl);
91 printk(BIOS_DEBUG, "before exit errata - after mdelay\n");
93 dcl = pci_read_config32(ctrl[i].f2, DRAM_INIT);
94 dcl &= ~DI_EnDramInit;
95 pci_write_config32(ctrl[i].f2, DRAM_INIT, dcl);
99 pci_read_config32(ctrl[i].f2,
102 pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
106 dcl = pci_read_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP);
107 pci_write_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP, dcl);
109 /* I was unable to do that like: ctrl[i].f2->path.pci.devfn << 8 */
111 0x80000000 | ((((ctrl[i].node_id + 0x18) << 3) | 0x2)
113 printk(BIOS_DEBUG, "pcidev is %x\n", pcidev);
115 __asm__ __volatile__("pushl %0\n\t"
116 "movw $0xcf8, %%dx\n\t"
117 "out %%eax, (%%dx)\n\t"
118 "movw $0xcfc, %%dx\n\t"
119 "inl %%dx, %%eax\n\t"
123 "outl %%eax, (%%dx) \n\t"
125 "outl %%eax, (%%dx)\n\t"
126 "popl %0\n\t"::"a"(pcidev),
130 printk(BIOS_DEBUG, "after exit errata\n");
133 for (i = 0; i < controllers; i++) {
135 if (!sysinfo->ctrl_present[i])
137 /* Skip everything if I don't have any memory on this controller */
138 if (sysinfo->meminfo[i].dimm_mask == 0x00)
141 printk(BIOS_DEBUG, "Exiting memory from self refresh: ");
145 if ((loops & 1023) == 0) {
146 printk(BIOS_DEBUG, ".");
149 pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
150 } while (((dcm & DCM_MemClrStatus) ==
151 0) /* || ((dcm & DCM_DramEnabled) == 0) */ );
153 if (loops >= TIMEOUT_LOOPS) {
154 printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i);
158 printk(BIOS_DEBUG, " done\n");
161 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
162 /* init hw mem hole here */
163 /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
164 set_hw_mem_hole(controllers, ctrl);
167 /* store tom to sysinfo, and it will be used by dqs_timing */
171 msr = rdmsr(TOP_MEM);
172 sysinfo->tom_k = ((msr.hi << 24) | (msr.lo >> 8)) >> 2;
175 msr = rdmsr(TOP_MEM2);
176 sysinfo->tom2_k = ((msr.hi << 24) | (msr.lo >> 8)) >> 2;
179 for (i = 0; i < controllers; i++) {
181 if (!sysinfo->ctrl_present[i])
184 /* Skip everything if I don't have any memory on this controller */
185 if (sysinfo->meminfo[i].dimm_mask == 0x00)
188 dqs_restore_MC_NVRAM((ctrl + i)->f2);
189 sysinfo->mem_trained[i] = 1; // mem was trained