src/northbridge/amd/amdk8/early_ht.c

   1 static int enumerate_ht_chain(void)
   2 {
   3         /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
   4          * On most boards this just happens.  If a cpu has multiple
   5          * non Coherent links the appropriate bus registers for the
   6          * links needs to be programed to point at bus 0.
   7          */
   8         unsigned next_unitid, last_unitid;
   9         int reset_needed = 0;
  10         next_unitid = 1;
  11         do {
  12                 uint32_t id;
  13                 uint8_t hdr_type, pos;
  14                 last_unitid = next_unitid;
  15
  16                 id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
  17                 /* If the chain is enumerated quit */
  18                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  19                     (((id >> 16) & 0xffff) == 0xffff) ||
  20                     (((id >> 16) & 0xffff) == 0x0000)) {
  21                         break;
  22                 }
  23                 hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
  24                 pos = 0;
  25                 hdr_type &= 0x7f;
  26
  27                 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
  28                     (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
  29                         pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
  30                 }
  31                 while(pos != 0) {
  32                         uint8_t cap;
  33                         cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
  34                         if (cap == PCI_CAP_ID_HT) {
  35                                 uint16_t flags;
  36                                 flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
  37                                 if ((flags >> 13) == 0) {
  38                                         unsigned count;
  39                                         flags &= ~0x1f;
  40                                         flags |= next_unitid & 0x1f;
  41                                         count = (flags >> 5) & 0x1f;
  42                                         pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
  43                                         next_unitid += count;
  44                                         break;
  45                                 }
  46                         }
  47                         pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
  48                 }
  49         } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
  50         return reset_needed;
  51 }
  52