src/northbridge/amd/amdk8/early_ht.c

   1 static void enumerate_ht_chain(void)
   2 {
   3         /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
   4          * On most boards this just happens.  If a cpu has multiple
   5          * non Coherent links the appropriate bus registers for the
   6          * links needs to be programed to point at bus 0.
   7          */
   8         unsigned next_unitid, last_unitid;;
   9         next_unitid = 1;
  10         do {
  11                 uint32_t id;
  12                 uint8_t hdr_type, pos;
  13                 last_unitid = next_unitid;
  14
  15                 id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
  16                 /* If the chain is enumerated quit */
  17                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  18                         (((id >> 16) & 0xffff) == 0xffff) ||
  19                         (((id >> 16) & 0xffff) == 0x0000)) {
  20                         break;
  21                 }
  22                 hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
  23                 pos = 0;
  24                 hdr_type &= 0x7f;
  25
  26                 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
  27                         (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
  28                         pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
  29                 }
  30                 while(pos != 0) {
  31                         uint8_t cap;
  32                         cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
  33                         if (cap == PCI_CAP_ID_HT) {
  34                                 uint16_t flags;
  35                                 flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
  36                                 if ((flags >> 13) == 0) {
  37                                         unsigned count;
  38                                         flags &= ~0x1f;
  39                                         flags |= next_unitid & 0x1f;
  40                                         count = (flags >> 5) & 0x1f;
  41                                         pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
  42                                         next_unitid += count;
  43                                         break;
  44                                 }
  45                         }
  46                         pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
  47                 }
  48         } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
  49 }