1 static int enumerate_ht_chain(void)
3 /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
4 * On most boards this just happens. If a cpu has multiple
5 * non Coherent links the appropriate bus registers for the
6 * links needs to be programed to point at bus 0.
8 unsigned next_unitid, last_unitid;
13 uint8_t hdr_type, pos;
14 last_unitid = next_unitid;
16 id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
17 /* If the chain is enumerated quit */
18 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
19 (((id >> 16) & 0xffff) == 0xffff) ||
20 (((id >> 16) & 0xffff) == 0x0000))
24 hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
28 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
29 (hdr_type == PCI_HEADER_TYPE_BRIDGE))
31 pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
35 cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
36 if (cap == PCI_CAP_ID_HT) {
38 flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
39 if ((flags >> 13) == 0) {
42 flags |= next_unitid & 0x1f;
43 count = (flags >> 5) & 0x1f;
44 pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
49 pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
51 } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));