src/northbridge/amd/amdk8/early_ht.c

   1 /*
   2         2005.11 yhlu add let the real sb to use small unitid
   3 */
   4 // only for sb ht chain
   5 static void enumerate_ht_chain(void)
   6 {
   7 #if HT_CHAIN_UNITID_BASE != 0
   8 /* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain  */
   9
  10         /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
  11          * On most boards this just happens.  If a cpu has multiple
  12          * non Coherent links the appropriate bus registers for the
  13          * links needs to be programed to point at bus 0.
  14          */
  15         unsigned next_unitid, last_unitid;
  16 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
  17         //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
  18         unsigned real_last_unitid;
  19         uint8_t real_last_pos;
  20         int ht_dev_num = 0; // except host_bridge
  21 #endif
  22
  23         next_unitid = HT_CHAIN_UNITID_BASE;
  24         do {
  25                 uint32_t id;
  26                 uint8_t hdr_type, pos;
  27                 last_unitid = next_unitid;
  28
  29                 id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
  30                 /* If the chain is enumerated quit */
  31                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  32                         (((id >> 16) & 0xffff) == 0xffff) ||
  33                         (((id >> 16) & 0xffff) == 0x0000))
  34                 {
  35                         break;
  36                 }
  37
  38                 hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
  39                 pos = 0;
  40                 hdr_type &= 0x7f;
  41
  42                 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
  43                         (hdr_type == PCI_HEADER_TYPE_BRIDGE))
  44                 {
  45                         pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
  46                 }
  47                 while(pos != 0) {
  48                         uint8_t cap;
  49                         cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
  50                         if (cap == PCI_CAP_ID_HT) {
  51                                 uint16_t flags;
  52                                 /* Read and write and reread flags so the link
  53                                  * direction bit is valid.
  54                                  */
  55                                 flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
  56                                 pci_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags);
  57                                 flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
  58                                 if ((flags >> 13) == 0) {
  59                                         unsigned count;
  60                                         unsigned ctrl, ctrl_off;
  61
  62                                         flags &= ~0x1f;
  63                                         flags |= next_unitid & 0x1f;
  64                                         count = (flags >> 5) & 0x1f;
  65 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
  66                                         real_last_unitid = next_unitid;
  67                                         real_last_pos = pos;
  68                                         ht_dev_num++ ;
  69 #endif
  70                                         next_unitid += count;
  71
  72                                         /* Test for end of chain */
  73                                         ctrl_off = ((flags >> 10) & 1)?
  74                                                 PCI_HT_CAP_SLAVE_CTRL1 : PCI_HT_CAP_SLAVE_CTRL0;
  75                                         ctrl = pci_read_config16(PCI_DEV(0,0,0), pos + ctrl_off);
  76                                         /* Is this the end of the hypertransport chain.
  77                                          * or has the link failed?
  78                                          */
  79                                         if (ctrl & ((1 << 6)|(1 << 4))) {
  80                                                 next_unitid = 0x20;
  81                                         }
  82
  83                                         pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
  84                                         break;
  85                                 }
  86                         }
  87                         pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
  88                 }
  89         } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
  90 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
  91         if(ht_dev_num>0) {
  92                 uint16_t flags;
  93                 flags = pci_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
  94                 flags &= ~0x1f;
  95                 flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
  96                 pci_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
  97         }
  98 #endif
  99
 100 #endif
 101
 102 }
 103