1 /* coherent hypertransport initialization for AMD64
3 * written by Stefan Reinauer <stepan@openbios.org>
4 * (c) 2003-2004 by SuSE Linux AG
6 * (c) 2004 Tyan Computer
7 * 2004.12 yhlu added support to create routing table dynamically.
8 * it also support 8 ways too. (8 ways ladder or 8 ways crossbar)
10 * This code is licensed under GPL.
14 * This algorithm assumes a grid configuration as follows:
17 * org. : 1x1 2x1 2x2 2x3 2x4
66 #include <device/pci_def.h>
67 #include <device/pci_ids.h>
68 #include <device/hypertransport_def.h>
69 #include "arch/romcc_io.h"
73 #define enable_bsp_routing() enable_routing(0)
75 #define NODE_HT(x) PCI_DEV(0,24+x,0)
76 #define NODE_MP(x) PCI_DEV(0,24+x,1)
77 #define NODE_MC(x) PCI_DEV(0,24+x,3)
79 #define DEFAULT 0x00010101 /* default row entry */
84 #ifndef CROSS_BAR_47_56
85 #define CROSS_BAR_47_56 0
88 #ifndef TRY_HIGH_FIRST
89 #define TRY_HIGH_FIRST 0
92 #ifndef K8_HT_FREQ_1G_SUPPORT
93 #define K8_HT_FREQ_1G_SUPPORT 0
96 #ifndef K8_HT_CHECK_PENDING_LINK
97 #if CONFIG_MAX_PHYSICAL_CPUS >= 4
98 #define K8_HT_CHECK_PENDING_LINK 1
100 #define K8_HT_CHECK_PENDING_LINK 0
104 #ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
105 #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
108 #ifndef ENABLE_APIC_EXT_ID
109 #define ENABLE_APIC_EXT_ID 0
113 static inline void print_linkn (const char *strval, uint8_t byteval)
116 #if CONFIG_USE_PRINTK_IN_CAR
117 printk_debug("%s%02x\r\n", strval, byteval);
119 print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
124 static void disable_probes(void)
126 /* disable read/write/fill probes for uniprocessor setup
127 * they don't make sense if only one cpu is available
130 /* Hypetransport Transaction Control Register
132 * [ 0: 0] Disable read byte probe
134 * 1 = Probes not issued
135 * [ 1: 1] Disable Read Doubleword probe
137 * 1 = Probes not issued
138 * [ 2: 2] Disable write byte probes
140 * 1 = Probes not issued
141 * [ 3: 3] Disable Write Doubleword Probes
143 * 1 = Probes not issued.
144 * [10:10] Disable Fill Probe
145 * 0 = Probes issued for cache fills
146 * 1 = Probes not issued for cache fills.
151 print_spew("Disabling read/write/fill probes for UP... ");
153 val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
154 val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
155 HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
156 HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
157 pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
159 print_spew("done.\r\n");
163 static void enable_apic_ext_id(u8 node)
165 #if ENABLE_APIC_EXT_ID==1
166 #warning "FIXME Is the right place to enable apic ext id here?"
170 val = pci_read_config32(NODE_HT(node), 0x68);
171 val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
172 pci_write_config32(NODE_HT(node), 0x68, val);
176 static void enable_routing(u8 node)
180 /* HT Initialization Control Register
182 * [ 0: 0] Routing Table Disable
183 * 0 = Packets are routed according to routing tables
184 * 1 = Packets are routed according to the default link field
185 * [ 1: 1] Request Disable (BSP should clear this)
186 * 0 = Request packets may be generated
187 * 1 = Request packets may not be generated.
188 * [ 3: 2] Default Link (Read-only)
192 * 11 = CPU on same node
194 * - Scratch bit cleared by a cold reset
195 * [ 5: 5] BIOS Reset Detect
196 * - Scratch bit cleared by a cold reset
197 * [ 6: 6] INIT Detect
198 * - Scratch bit cleared by a warm or cold reset not by an INIT
202 /* Enable routing table */
203 print_spew("Enabling routing table for node ");
204 print_spew_hex8(node);
206 val=pci_read_config32(NODE_HT(node), 0x6c);
207 val &= ~((1<<1)|(1<<0));
208 pci_write_config32(NODE_HT(node), 0x6c, val);
210 print_spew(" done.\r\n");
213 static void fill_row(u8 node, u8 row, u32 value)
215 pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
218 #if CONFIG_MAX_PHYSICAL_CPUS > 1
219 static u8 link_to_register(int ldt)
222 * [ 0: 3] Request Route
223 * [0] Route to this node
224 * [1] Route to Link 0
225 * [2] Route to Link 1
226 * [3] Route to Link 2
229 if (ldt&0x08) return 0x40;
230 if (ldt&0x04) return 0x20;
231 if (ldt&0x02) return 0x00;
233 /* we should never get here */
234 print_spew("Unknown Link\n");
238 static u32 get_row(u8 node, u8 row)
240 return pci_read_config32(NODE_HT(node), 0x40+(row<<2));
243 static int link_connection(u8 src, u8 dest)
245 return get_row(src, dest) & 0x0f;
248 static void rename_temp_node(u8 node)
252 print_spew("Renaming current temporary node to ");
253 print_spew_hex8(node);
255 val=pci_read_config32(NODE_HT(7), 0x60);
256 val &= (~7); /* clear low bits. */
257 val |= node; /* new node */
258 pci_write_config32(NODE_HT(7), 0x60, val);
260 print_spew(" done.\r\n");
263 static int verify_connection(u8 dest)
265 /* See if we have a valid connection to dest */
268 /* Verify that the coherent hypertransport link is
269 * established and actually working by reading the
270 * remode node's vendor/device id
272 val = pci_read_config32(NODE_HT(dest),0);
273 if(val != 0x11001022)
279 static uint16_t read_freq_cap(device_t dev, uint8_t pos)
281 /* Handle bugs in valid hypertransport frequency reporting */
285 freq_cap = pci_read_config16(dev, pos);
286 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
288 #if K8_HT_FREQ_1G_SUPPORT == 1
289 #if K8_REV_F_SUPPORT == 0
290 if (!is_cpu_pre_e0())
297 id = pci_read_config32(dev, 0);
299 /* AMD K8 Unsupported 1Ghz? */
300 if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
301 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
307 static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2)
309 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
310 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
311 uint16_t freq_cap1, freq_cap2;
312 uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
313 uint8_t freq, old_freq;
315 /* Set link width and frequency */
317 /* Initially assume everything is already optimized and I don't need a reset */
320 /* Get the frequency capabilities */
321 freq_cap1 = read_freq_cap(node1, link1 + PCI_HT_CAP_HOST_FREQ_CAP);
322 freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP);
324 /* Calculate the highest possible frequency */
325 freq = log2(freq_cap1 & freq_cap2);
327 /* See if I am changing the link freqency */
328 old_freq = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ);
330 needs_reset |= old_freq != freq;
331 old_freq = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ);
333 needs_reset |= old_freq != freq;
335 /* Set the Calulcated link frequency */
336 pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ, freq);
337 pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ, freq);
339 /* Get the width capabilities */
340 width_cap1 = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH);
341 width_cap2 = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH);
343 /* Calculate node1's input width */
344 ln_width1 = link_width_to_pow2[width_cap1 & 7];
345 ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
346 if (ln_width1 > ln_width2) {
347 ln_width1 = ln_width2;
349 width = pow2_to_link_width[ln_width1];
350 /* Calculate node1's output width */
351 ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
352 ln_width2 = link_width_to_pow2[width_cap2 & 7];
353 if (ln_width1 > ln_width2) {
354 ln_width1 = ln_width2;
356 width |= pow2_to_link_width[ln_width1] << 4;
358 /* See if I am changing node1's width */
359 old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1);
361 needs_reset |= old_width != width;
363 /* Set node1's widths */
364 pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1, width);
366 // * Calculate node2's width */
367 width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
369 /* See if I am changing node2's width */
370 old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1);
372 needs_reset |= old_width != width;
374 /* Set node2's widths */
375 pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width);
380 static uint8_t get_linkn_first(uint8_t byte)
382 if(byte & 0x02) { byte = 0; }
383 else if(byte & 0x04) { byte = 1; }
384 else if(byte & 0x08) { byte = 2; }
388 static uint8_t get_linkn_last(uint8_t byte)
390 if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
391 if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; }
392 if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
396 static uint8_t get_linkn_last_count(uint8_t byte)
399 if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
400 if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
401 if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
405 static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
410 for(linkn = 0; linkn<3; linkn++) {
413 regpos = 0x98 + 0x20 * linkn;
414 reg = pci_read_config32(NODE_HT(source), regpos);
415 if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/
420 fill_row(source,row, val);
423 static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
428 val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/
430 if(((source &1)!=(dest &1))
432 && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
433 //(6,5) (7,4) should be here
438 /*for CROSS_BAR_47_56 47, 56, should be here too
439 and for 47, 56, 57, 75, 46, 64 we need to substract another link to
442 val_s = get_row(temp, source);
443 val |= ((val_s>>16) - (1<<(linkn+1)))<<16;
446 fill_row(temp,dest, val );
450 static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
452 val = get_row(source, dest);
453 val -= link_connection(source, kickout)<<16;
454 fill_row(source, dest, val);
457 static void opt_broadcast_rt_group(const u8 *conn, int num) {
460 for(i=0; i<num; i+=3) {
461 opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
464 static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
466 val = get_row(source, dest);
467 val += link_connection(source, kickout)<<16;
468 fill_row(source, dest, val);
471 static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
474 for(i=0; i<num; i+=3) {
475 opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
480 static void setup_row_direct(u8 source, u8 dest, u8 linkn){
481 setup_row_direct_x(source, source, dest, linkn);
484 static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){
485 setup_row_direct_x(7, source, dest, linkn);
488 static void setup_temp_row(u8 source, u8 dest)
490 /* copy val from (source, dest) to (source,7) */
491 fill_row(source,7,get_row(source,dest));
494 static void clear_temp_row(u8 source)
496 fill_row(source, 7, DEFAULT);
499 static void setup_remote_node(u8 node)
501 static const uint8_t pci_reg[] = {
502 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
503 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
504 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
505 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
506 0xc4, 0xcc, 0xd4, 0xdc,
507 0xc0, 0xc8, 0xd0, 0xd8,
508 0xe0, 0xe4, 0xe8, 0xec,
512 print_spew("setup_remote_node: ");
514 /* copy the default resource map from node 0 */
515 for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
519 value = pci_read_config32(NODE_MP(0), reg);
520 pci_write_config32(NODE_MP(7), reg, value);
523 print_spew("done\r\n");
526 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
529 #if CONFIG_MAX_PHYSICAL_CPUS > 2
531 static void setup_row_indirect_x(u8 temp, u8 source, u8 dest)
533 static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 diff)
536 /*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */
543 gateway = source + 2;
545 gateway = source - 2;
548 val_s = get_row(temp, source);
549 val = get_row(temp, gateway);
556 diff = ((source&1)!=(dest &1));
559 if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/
561 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
563 /* Some node have two links left
564 * don't worry we only have (2, (3 as source need to handle
567 byte = get_linkn_last_count(byte);
568 if((byte>>2)>1) { /* make sure not the corner*/
570 val_s-=link_connection(temp, source-2); /* -down*/
575 val_s-=link_connection(temp, 6); // for 7,2 via 5
576 } else if (source==6){
577 val_s-=link_connection(temp, 7); // for 6,3 via 4
580 if (source < gateway) { // for 5, 4 via 7
581 val_s-=link_connection(temp, source-2);
584 val_s-=link_connection(temp, source+2); /* -up*/
592 if(diff) { /* cross rung?*/
596 val_s = get_row(temp, source);
597 val |= ((val_s>>16) - link_connection(temp, gateway))<<16;
600 fill_row(temp, dest, val);
605 static void setup_row_indirect(u8 source, u8 dest)
607 setup_row_indirect_x(source, source, dest);
610 static void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
612 setup_row_indirect_x(source, source, dest, gateway, diff);
616 static void setup_row_indirect_group(const u8 *conn, int num)
621 for(i=0; i<num; i+=2) {
622 setup_row_indirect(conn[i], conn[i+1]);
624 for(i=0; i<num; i+=4) {
625 setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
632 static void setup_remote_row_indirect(u8 source, u8 dest)
634 setup_row_indirect_x(7, source, dest);
637 static void setup_remote_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
639 setup_row_indirect_x(7, source, dest, gateway, diff);
643 static void setup_remote_row_indirect_group(const u8 *conn, int num)
648 for(i=0; i<num; i+=2) {
649 setup_remote_row_indirect(conn[i], conn[i+1]);
651 for(i=0; i<num; i+=4) {
652 setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
657 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 2*/
660 static void setup_uniprocessor(void)
662 print_spew("Enabling UP settings\r\n");
663 #if CONFIG_LOGICAL_CPUS==1
664 unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
670 #if CONFIG_MAX_PHYSICAL_CPUS > 2
671 static int optimize_connection_group(const u8 *opt_conn, int num) {
674 for(i=0; i<num; i+=2) {
675 needs_reset = optimize_connection(
676 NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])),
677 NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) );
683 #if CONFIG_MAX_PHYSICAL_CPUS > 1
684 static unsigned setup_smp2(void)
691 setup_row_local(0, 0); /* it will update the broadcast RT*/
694 byte = (val>>16) & 0xfe;
695 if(byte<0x2) { /* no coherent connection so get out.*/
700 /* Setup and check a temporary connection to node 1 */
701 #if TRY_HIGH_FIRST == 1
702 byte = get_linkn_last(byte); /* Max Link to node1 */
704 byte = get_linkn_first(byte); /*Min Link to node1 --- according to AMD*/
706 print_linkn("(0,1) link=", byte);
707 setup_row_direct(0,1, byte);
708 setup_temp_row(0, 1);
710 verify_connection(7);
712 /* We found 2 nodes so far */
713 val = pci_read_config32(NODE_HT(7), 0x6c);
714 byte = (val>>2) & 0x3; /*get default link on node7 to node0*/
715 print_linkn("(1,0) link=", byte);
716 setup_row_local(7,1);
717 setup_remote_row_direct(1, 0, byte);
719 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
721 byte = (val>>16) & 0xfe;
722 byte = get_linkn_last_count(byte);
723 if((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/
725 byte = (val>>16) & 0xfe;
726 #if TRY_HIGH_FIRST == 1
727 byte = get_linkn_first(byte); /* Min link to Node1 */
729 byte = get_linkn_last(byte); /* Max link to Node1*/
731 print_linkn("\t-->(0,1) link=", byte);
732 setup_row_direct(0,1, byte);
733 setup_temp_row(0, 1);
735 verify_connection(7);
737 /* We found 2 nodes so far */
738 val = pci_read_config32(NODE_HT(7), 0x6c);
739 byte = (val>>2) & 0x3; /* get default link on node7 to node0*/
740 print_linkn("\t-->(1,0) link=", byte);
741 setup_row_local(7,1);
742 setup_remote_row_direct(1, 0, byte);
746 setup_remote_node(1); /* Setup the regs on the remote node */
747 rename_temp_node(1); /* Rename Node 7 to Node 1 */
748 enable_routing(1); /* Enable routing on Node 1 */
750 /*don't need and it is done by clear_dead_links */
756 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 1 */
758 #if CONFIG_MAX_PHYSICAL_CPUS > 2
760 static unsigned setup_smp4(void)
768 /* Setup and check temporary connection from Node 0 to Node 2 */
770 byte = ((val>>16) & 0xfe) - link_connection(0,1);
771 byte = get_linkn_last_count(byte);
773 if((byte>>2)==0) { /* We should have two coherent for 4p and above*/
778 byte &= 3; /* bit [3,2] is count-1*/
779 print_linkn("(0,2) link=", byte);
780 setup_row_direct(0, 2, byte); /*(0,2) direct link done*/
782 /* We found 3 nodes so far. Now setup a temporary
783 * connection from node 0 to node 3 via node 1
785 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
786 /* here should setup_row_direct(1,3) at first, before that we should find the link in node 1 to 3*/
788 byte = ((val>>16) & 0xfe) - link_connection(1,0);
789 byte = get_linkn_first(byte);
790 print_linkn("(1,3) link=", byte);
791 setup_row_direct(1,3,byte); /* (1, 3) direct link done*/
793 /* We found 4 nodes so far. Now setup all nodes for 4p */
794 // We need to make sure 0,2 and 1,3 link is set already
796 static const u8 conn4_1[] = {
801 static const u8 conn4_1[] = {
807 setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0]));
810 verify_connection(7);
811 val = pci_read_config32(NODE_HT(7), 0x6c);
812 byte = (val>>2) & 0x3; /* get default link on 7 to 0*/
813 print_linkn("(2,0) link=", byte);
815 setup_row_local(7,2);
816 setup_remote_row_direct(2, 0, byte); /* node 2 to node 0 direct link done */
817 setup_remote_node(2); /* Setup the regs on the remote node */
819 rename_temp_node(2); /* Rename Node 7 to Node 2 */
820 enable_routing(2); /* Enable routing on Node 2 */
824 verify_connection(7);
826 val = pci_read_config32(NODE_HT(7), 0x6c);
827 byte = (val>>2) & 0x3; /* get default link on 7 to 1*/
828 print_linkn("(3,1) link=", byte);
830 setup_row_local(7,3);
831 setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */
832 setup_remote_node(3); /* Setup the regs on the remote node */
834 /* We need to init link between 2, and 3 direct link */
836 byte = ((val>>16) & 0xfe) - link_connection(2,0);
837 byte = get_linkn_last_count(byte);
838 print_linkn("(2,3) link=", byte & 3);
840 setup_row_direct(2,3, byte & 0x3);
843 verify_connection(7); /* to 3*/
845 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
846 /* We need to find out which link is to node3 */
847 if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/
849 if((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/
851 byte = ((val>>16) & 0xfe) - link_connection(2,0);
852 byte = get_linkn_first(byte);
853 print_linkn("\t-->(2,3) link=", byte);
854 setup_row_direct(2,3,byte);
856 verify_connection(7); /* to 3*/
861 val = pci_read_config32(NODE_HT(7), 0x6c);
862 byte = (val>>2) & 0x3; /* get default link on 7 to 2*/
863 print_linkn("(3,2) link=", byte);
864 setup_remote_row_direct(3,2, byte);
866 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
867 /* set link from 3 to 5 before enable it*/
869 byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
870 byte = get_linkn_last_count(byte);
871 if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
872 byte &= 3; /*bit [3,2] is count-2*/
873 print_linkn("(3,5) link=", byte);
874 setup_remote_row_direct(3, 5, byte);
878 byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
879 byte = get_linkn_last_count(byte);
881 if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
882 byte &= 3; /* bit [3,2] is count-2*/
883 print_linkn("(2,4) link=", byte);
884 setup_row_direct(2, 4, byte);
888 //Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3
890 static const u8 conn4_3[] = {
894 static const u8 conn4_3[] = {
898 setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0]));
900 /* ready to enable RT for Node 3 */
902 enable_routing(3); /* enable routing on node 3 (temp.) */
904 // beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2
906 static const u8 conn4_2[] = {
910 static const u8 conn4_2[] = {
914 setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0]));
917 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
918 /* it will be done by clear_dead_links */
927 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 2 */
929 #if CONFIG_MAX_PHYSICAL_CPUS > 4
931 static unsigned setup_smp6(void)
939 /* Setup and check temporary connection from Node 0 to Node 4 through 2*/
941 byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
942 byte = get_linkn_last_count(byte);
944 if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
949 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/
950 /* set link from 3 to 5 before enable it*/
952 byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
953 byte = get_linkn_last_count(byte);
954 if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
959 /* We found 6 nodes so far. Now setup all nodes for 6p */
960 #warning "FIXME we need to find out the correct gateway for 6p"
961 static const u8 conn6_1[] = {
979 setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0]));
981 for(byte=0; byte<4; byte+=2) {
982 setup_temp_row(byte,byte+2);
984 verify_connection(7);
985 val = pci_read_config32(NODE_HT(7), 0x6c);
986 byte = (val>>2) & 0x3; /*get default link on 7 to 2*/
987 print_linkn("(4,2) link=", byte);
989 setup_row_local(7,4);
990 setup_remote_row_direct(4, 2, byte);
991 setup_remote_node(4); /* Setup the regs on the remote node */
993 /* Set indirect connection to 0, to 3 */
994 //we only need to set 4,0 here
995 static const u8 conn6_2[] = {
1003 setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0]));
1005 rename_temp_node(4);
1008 setup_temp_row(0,1);
1009 for(byte=0; byte<4; byte+=2) {
1010 setup_temp_row(byte+1,byte+3);
1012 verify_connection(7);
1014 val = pci_read_config32(NODE_HT(7), 0x6c);
1015 byte = (val>>2) & 0x3; /* get default link on 7 to 3*/
1016 print_linkn("(5,3) link=", byte);
1017 setup_row_local(7,5);
1018 setup_remote_row_direct(5, 3, byte);
1019 setup_remote_node(5); /* Setup the regs on the remote node */
1021 #if !CROSS_BAR_47_56
1022 /* We need to init link between 4, and 5 direct link */
1024 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1025 byte = get_linkn_last_count(byte);
1026 print_linkn("(4,5) link=", byte & 3);
1028 setup_row_direct(4,5, byte & 0x3);
1029 setup_temp_row(0,2);
1030 setup_temp_row(2,4);
1031 setup_temp_row(4,5);
1032 verify_connection(7); /* to 5*/
1034 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1035 /* We need to find out which link is to node5 */
1037 if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/
1039 if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/
1041 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1042 byte = get_linkn_first(byte);
1043 print_linkn("\t-->(4,5) link=", byte);
1044 setup_row_direct(4,5,byte);
1045 setup_temp_row(4,5);
1046 verify_connection(7); /* to 5*/
1051 val = pci_read_config32(NODE_HT(7), 0x6c);
1052 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1053 print_linkn("(5,4) link=", byte);
1054 setup_remote_row_direct(5,4, byte);
1058 byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
1059 byte = get_linkn_last_count(byte);
1060 if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
1061 byte &= 3; /*bit [3,2] is count-2*/
1062 print_linkn("(5,7) link=", byte);
1063 setup_remote_row_direct(5, 7, byte);
1068 byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
1069 byte = get_linkn_last_count(byte);
1071 if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
1072 byte &= 3; /* bit [3,2] is count-2*/
1073 print_linkn("(4,6) link=", byte);
1074 setup_row_direct(4, 6, byte);
1079 //We need to set 5,0 here only, We need to set up 5, 7 to make 5,0
1080 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */
1081 static const u8 conn6_3[] = {
1082 #if !CROSS_BAR_47_56
1089 setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0]));
1091 /* ready to enable RT for 5 */
1092 rename_temp_node(5);
1093 enable_routing(5); /* enable routing on node 5 (temp.) */
1095 static const u8 conn6_4[] = {
1096 #if !CROSS_BAR_47_56
1115 setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0]));
1118 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
1119 * It will be done by clear_dead_links
1121 for(byte=0; byte<4; byte++) {
1122 clear_temp_row(byte);
1130 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 4 */
1132 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1134 static unsigned setup_smp8(void)
1142 /* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
1145 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1147 byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
1148 byte = get_linkn_last_count(byte); /* Max link to 6*/
1149 if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
1156 byte = get_linkn_last_count(byte); /* Max link to 6*/
1157 if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/
1161 #if TRY_HIGH_FIRST == 1
1162 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1163 byte = get_linkn_first(byte); /*Min link to 6*/
1165 byte &= 3; /* bit [3,2] is count-1 or 2*/
1167 print_linkn("(4,6) link=", byte);
1168 setup_row_direct(4, 6, byte);
1171 #if !CROSS_BAR_47_56
1172 /* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/
1174 byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
1175 byte = get_linkn_last_count(byte);
1176 if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
1182 /* We found 8 nodes so far. Now setup all nodes for 8p */
1183 static const u8 conn8_1[] = {
1184 #if !CROSS_BAR_47_56
1207 setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0]));
1209 for(byte=0; byte<6; byte+=2) {
1210 setup_temp_row(byte,byte+2);
1212 verify_connection(7);
1213 val = pci_read_config32(NODE_HT(7), 0x6c);
1214 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1215 print_linkn("(6,4) link=", byte);
1217 setup_row_local(7,6);
1218 setup_remote_row_direct(6, 4, byte);
1219 setup_remote_node(6); /* Setup the regs on the remote node */
1220 /* Set indirect connection to 0, to 3 */
1221 #warning "FIXME we need to find out the correct gateway for 8p"
1222 static const u8 conn8_2[] = {
1223 #if !CROSS_BAR_47_56
1230 setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0]));
1234 /* here init 5, 6 */
1235 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
1237 byte = ((val>>16) & 0xfe) - link_connection(5,3);
1238 #if TRY_HIGH_FIRST == 1
1239 byte = get_linkn_first(byte);
1241 byte = get_linkn_last(byte);
1243 print_linkn("(5,6) link=", byte);
1244 setup_row_direct(5, 6, byte);
1246 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1247 for(byte=0; byte<4; byte+=2) {
1248 setup_temp_row(byte+1,byte+3);
1250 setup_temp_row(5,6);
1252 verify_connection(7);
1254 val = get_row(7,6); // to chect it if it is node6 before renaming
1255 if( (val>>16) == 1) { // it is real node 7 so swap it
1256 /* We need to recompute link to 6 */
1258 byte = ((val>>16) & 0xfe) - link_connection(5,3);
1259 #if TRY_HIGH_FIRST == 1
1260 byte = get_linkn_first(byte);
1262 byte = get_linkn_last(byte);
1264 print_linkn("\t-->(5,6) link=", byte);
1265 setup_row_direct(5, 6, byte);
1267 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1268 for(byte=0; byte<4; byte+=2) {
1269 setup_temp_row(byte+1,byte+3);
1272 setup_temp_row(5,6);
1274 verify_connection(7);
1276 val = pci_read_config32(NODE_HT(7), 0x6c);
1277 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1278 print_linkn("(6,5) link=", byte);
1279 setup_remote_row_direct(6, 5, byte);
1280 /*Till now 56, 65 done */
1283 rename_temp_node(6);
1286 #if !CROSS_BAR_47_56
1287 setup_temp_row(0,1);
1288 for(byte=0; byte<6; byte+=2) {
1289 setup_temp_row(byte+1,byte+3);
1292 verify_connection(7);
1294 val = pci_read_config32(NODE_HT(7), 0x6c);
1295 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1296 print_linkn("(7,5) link=", byte);
1297 setup_row_local(7,7);
1298 setup_remote_row_direct(7, 5, byte);
1302 byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
1303 byte = get_linkn_first(byte);
1304 print_linkn("(4,7) link=", byte);
1305 setup_row_direct(4, 7, byte);
1307 /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
1308 for(byte=0; byte<4; byte+=2) {
1309 setup_temp_row(byte,byte+2);
1312 verify_connection(7);
1314 val = pci_read_config32(NODE_HT(7), 0x6c);
1315 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1316 print_linkn("(7,4) link=", byte);
1317 setup_row_local(7,7);
1318 setup_remote_row_direct(7, 4, byte);
1319 /* till now 4-7, 7-4 done. */
1321 setup_remote_node(7); /* Setup the regs on the remote node */
1324 /* here init 5, 7 */
1325 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
1327 byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6);
1328 byte = get_linkn_first(byte);
1329 print_linkn("(5,7) link=", byte);
1330 setup_row_direct(5, 7, byte);
1332 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1333 for(byte=0; byte<4; byte+=2) {
1334 setup_temp_row(byte+1,byte+3);
1337 verify_connection(7);
1339 val = pci_read_config32(NODE_HT(7), 0x6c);
1340 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1341 print_linkn("(7,5) link=", byte);
1342 setup_remote_row_direct(7, 5, byte);
1343 /*Till now 57, 75 done */
1347 /* We need to init link between 6, and 7 direct link */
1349 #if !CROSS_BAR_47_56
1350 byte = ((val>>16) & 0xfe) - link_connection(6,4);
1352 byte = ((val>>16) & 0xfe) - link_connection(6,4) - link_connection(6,5);
1354 byte = get_linkn_first(byte);
1355 print_linkn("(6,7) link=", byte);
1356 setup_row_direct(6,7, byte);
1359 #if !CROSS_BAR_47_56
1360 byte = ((val>>16) & 0xfe) - link_connection(7,5);
1362 byte = ((val>>16) & 0xfe) - link_connection(7,5) - link_connection(7,4);
1364 byte = get_linkn_first(byte);
1365 print_linkn("(7,6) link=", byte);
1366 setup_row_direct(7,6, byte);
1368 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */
1369 static const u8 conn8_3[] = {
1370 #if !CROSS_BAR_47_56
1371 0, 7, /* restore it*/
1393 6, 1, 5, 0, // or 4, 1
1395 6, 3, 5, 0, // or 4, 1
1397 7, 0, 4, 0, // or 5, 1
1399 7, 2, 4, 0, // or 5, 1
1402 0, 7, 2, 0, /* restore it*/
1407 2, 5, 4, 1, /* reset it */
1410 4, 1, 2, 1, /* reset it */
1413 5, 2, 3, 1, /* reset it */
1419 setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0]));
1422 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to
1424 static const u8 conn8_4[] = {
1447 6, 1, 7, // needed for via 5
1450 6, 3, 7, // needed for via 5
1452 7, 0, 6, // needed for via 4
1455 7, 2, 6, // needed for via 4
1460 opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0]));
1462 static const u8 conn8_5[] = {
1468 opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0]));
1473 /* ready to enable RT for Node 7 */
1474 enable_routing(7); /* enable routing on node 7 (temp.) */
1479 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 6 */
1482 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1484 static unsigned setup_smp(void)
1488 print_spew("Enabling SMP settings\r\n");
1490 nodes = setup_smp2();
1491 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1493 nodes = setup_smp4();
1496 #if CONFIG_MAX_PHYSICAL_CPUS > 4
1498 nodes = setup_smp6();
1501 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1503 nodes = setup_smp8();
1506 #if CONFIG_USE_PRINTK_IN_CAR
1507 printk_debug("%02x nodes initialized.\r\n", nodes);
1509 print_debug_hex8(nodes);
1510 print_debug(" nodes initialized.\r\n");
1516 static unsigned verify_mp_capabilities(unsigned nodes)
1518 unsigned node, mask;
1520 mask = 0x06; /* BigMPCap */
1522 for (node=0; node<nodes; node++) {
1523 mask &= pci_read_config32(NODE_MC(node), 0xe8);
1527 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1528 case 0x02: /* MPCap */
1530 print_err("Going back to DP\r\n");
1535 case 0x00: /* Non SMP */
1537 print_err("Going back to UP\r\n");
1548 static void clear_dead_routes(unsigned nodes)
1552 #if CONFIG_MAX_PHYSICAL_CPUS == 8
1553 if(nodes==8) return;/* don't touch (7,7)*/
1559 for(node = 7; node >= 0; node--) {
1560 for(row = 7; row >= last_row; row--) {
1561 fill_row(node, row, DEFAULT);
1565 /* Update the local row */
1566 for( node=0; node<nodes; node++) {
1568 for(row =0; row<nodes; row++) {
1569 val |= get_row(node, row);
1571 fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101);
1574 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
1576 #if CONFIG_LOGICAL_CPUS==1
1577 static unsigned verify_dualcore(unsigned nodes)
1579 unsigned node, totalcpus, tmp;
1582 for (node=0; node<nodes; node++) {
1583 tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ;
1584 totalcpus += (tmp + 1);
1592 static void coherent_ht_finalize(unsigned nodes)
1595 #if K8_REV_F_SUPPORT == 0
1598 #if CONFIG_LOGICAL_CPUS==1
1599 unsigned total_cpus;
1601 if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
1602 total_cpus = verify_dualcore(nodes);
1609 /* set up cpu count and node count and enable Limit
1610 * Config Space Range for all available CPUs.
1611 * Also clear non coherent hypertransport bus range
1612 * registers on Hammer A0 revision.
1615 print_spew("coherent_ht_finalize\r\n");
1616 #if K8_REV_F_SUPPORT == 0
1617 rev_a0 = is_cpu_rev_a0();
1619 for (node = 0; node < nodes; node++) {
1622 dev = NODE_HT(node);
1624 /* Set the Total CPU and Node count in the system */
1625 val = pci_read_config32(dev, 0x60);
1626 val &= (~0x000F0070);
1627 #if CONFIG_LOGICAL_CPUS==1
1628 val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
1630 val |= ((nodes-1)<<16)|((nodes-1)<<4);
1632 pci_write_config32(dev, 0x60, val);
1634 /* Only respond to real cpu pci configuration cycles
1635 * and optimize the HT settings
1637 val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);
1638 val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) |
1639 (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) |
1640 (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT));
1641 val |= HTTC_LIMIT_CLDT_CFG |
1642 (HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) |
1643 (3 << HTTC_MED_PRI_BYP_CNT_SHIFT) |
1644 (3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
1645 pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
1647 #if K8_REV_F_SUPPORT == 0
1649 pci_write_config32(dev, 0x94, 0);
1650 pci_write_config32(dev, 0xb4, 0);
1651 pci_write_config32(dev, 0xd4, 0);
1656 print_spew("done\r\n");
1659 static int apply_cpu_errata_fixes(unsigned nodes)
1662 int needs_reset = 0;
1663 for(node = 0; node < nodes; node++) {
1666 dev = NODE_MC(node);
1667 #if K8_REV_F_SUPPORT == 0
1668 if (is_cpu_pre_c0()) {
1671 * Limit the number of downstream posted requests to 1
1673 cmd = pci_read_config32(dev, 0x70);
1674 if ((cmd & (3 << 0)) != 2) {
1677 pci_write_config32(dev, 0x70, cmd );
1680 cmd = pci_read_config32(dev, 0x7c);
1681 if ((cmd & (3 << 4)) != 0) {
1684 pci_write_config32(dev, 0x7c, cmd );
1687 /* Clock Power/Timing Low */
1688 cmd = pci_read_config32(dev, 0xd4);
1689 if (cmd != 0x000D0001) {
1691 pci_write_config32(dev, 0xd4, cmd);
1692 needs_reset = 1; /* Needed? */
1696 else if (is_cpu_pre_d0()) { // d0 later don't need it
1699 * Set Clk Ramp Hystersis to 7
1700 * Clock Power/Timing Low
1702 cmd_ref = 0x04e20707; /* Registered */
1703 cmd = pci_read_config32(dev, 0xd4);
1704 if(cmd != cmd_ref) {
1705 pci_write_config32(dev, 0xd4, cmd_ref );
1706 needs_reset = 1; /* Needed? */
1714 static int optimize_link_read_pointers(unsigned nodes)
1717 int needs_reset = 0;
1718 for(node = 0; node < nodes; node++) {
1719 device_t f0_dev, f3_dev;
1720 uint32_t cmd_ref, cmd;
1722 f0_dev = NODE_HT(node);
1723 f3_dev = NODE_MC(node);
1724 cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc);
1725 for(link = 0; link < 3; link++) {
1728 /* This works on an Athlon64 because unimplemented links return 0 */
1729 reg = 0x98 + (link * 0x20);
1730 link_type = pci_read_config32(f0_dev, reg);
1731 /* Only handle coherent links */
1732 if ((link_type & (LinkConnected | InitComplete|NonCoherent)) ==
1733 (LinkConnected|InitComplete))
1735 cmd &= ~(0xff << (link *8));
1736 cmd |= 0x25 << (link *8);
1739 if (cmd != cmd_ref) {
1740 pci_write_config32(f3_dev, 0xdc, cmd);
1747 static inline unsigned get_nodes(void)
1749 return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
1752 static int optimize_link_coherent_ht(void)
1754 int needs_reset = 0;
1758 nodes = get_nodes();
1760 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1762 needs_reset |= optimize_connection(
1763 NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
1764 NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
1767 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1769 /* optimize physical connections - by LYH */
1770 static const u8 opt_conn4[] = {
1775 needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0]));
1779 #if CONFIG_MAX_PHYSICAL_CPUS > 4
1781 static const uint8_t opt_conn6[] ={
1784 #if !CROSS_BAR_47_56
1788 needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0]));
1792 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1794 static const uint8_t opt_conn8[] ={
1803 needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0]));
1809 needs_reset |= apply_cpu_errata_fixes(nodes);
1810 needs_reset |= optimize_link_read_pointers(nodes);
1815 #if RAMINIT_SYSINFO == 1
1816 static void setup_coherent_ht_domain(void)
1818 static int setup_coherent_ht_domain(void)
1824 enable_bsp_routing();
1826 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1827 nodes = setup_smp();
1828 nodes = verify_mp_capabilities(nodes);
1829 clear_dead_routes(nodes);
1833 setup_uniprocessor();
1835 coherent_ht_finalize(nodes);
1837 #if RAMINIT_SYSINFO == 0
1838 return optimize_link_coherent_ht();